KR20050002102A - Method of manufacturing flash memory device - Google Patents

Abstract

PURPOSE: A method of manufacturing a flash memory device is provided to prevent an active region from being exposed to the outside due to mis-alignment of a floating gate mask and to increase effective surface area of a floating gate by overlaying partially the floating gate with an isolation layer. CONSTITUTION: A plurality of isolation layers(14) is formed in a semiconductor substrate(11) with a tunnel oxide layer(12) and a first polysilicon layer(13) by using an SA-STI(Self Align-Shallow Trench Isolation). A masking pattern(15) for covering completely each isolation layer and partially the first polysilicon layer is formed thereon. A second polysilicon layer(16) is formed on the entire surface of the resultant structure. A second polysilicon pattern for being partially overlaid with the isolation layer is formed by etching selectively the second polysilicon pattern using a floating gate mask as an etching mask.

Description

Flash memory device manufacturing method {Method of manufacturing flash memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a contact area between a floating gate and a control gate while preventing exposure of an active region due to misalignment during a floating gate mask operation in a NAND flash memory device. The present invention relates to a method of manufacturing a flash memory device that can increase a gate capacitive coupling ratio to a large extent.

In general, in NAND flash memory devices employing a self-aligned device isolation (SA-STI) process, the floating gate forming process is emerging as one of important processes as the design rule of the device becomes smaller. In other words, the floating gate formation process should consider the bridge phenomenon, the active attack due to the lack of overlay margin, and the minimum coupling ratio required for driving the device. It is one of the critical processes to determine the size and characteristics of the device, such as the effort to secure the (). In particular, the exposure of the active region due to misalignment during the floating gate mask operation causes the control gate formed in a subsequent process to come into direct contact with the active region, thereby preventing the control gate from controlling the floating gate.

Accordingly, the present invention provides a gate capacitive coupling ratio by increasing the contact area between the floating gate and the control gate while preventing exposure of the active region due to misalignment during the floating gate mask operation in the flash memory device. It is an object of the present invention to provide a method for manufacturing a flash memory device capable of increasing the ratio.

1A to 1D are cross-sectional views of a device for explaining a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11: semiconductor substrate 12: tunnel oxide film

13: first polysilicon layer 14: device isolation film

15: masking pattern 16: second polysilicon layer

17: dielectric film 18: conductive material layer

In the flash memory device manufacturing method according to the embodiment of the present invention for achieving the above object, a tunnel oxide film and a first polysilicon layer are formed in the active region through the self-aligned device isolation process, the substrate is formed in the field region Provided step; Forming a masking pattern partially overlapping the first polysilicon layer and completely covering the device isolation layer; Forming a second polysilicon layer on the entire structure including the masking pattern, and then patterning the second polysilicon layer in an etching process using a mask for a floating gate; And forming a dielectric layer and a conductive material layer on the entire structure including the patterned second polysilicon layer, and then forming a floating gate and a control gate by a self-aligned gate etching process.

In the above description, the masking pattern is formed by depositing polysilicon on the device isolation layer including the first polysilicon layer to a thickness of 300 to 500 Å, and then patterning the device isolation layer to sufficiently cover the device isolation layer.

The floating gate is formed by stacking a first polysilicon layer, a masking pattern, and a second polysilicon layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.

1A to 1D are cross-sectional views of devices for explaining a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a tunnel oxide film 12 and a first polysilicon layer 13 for floating gates are formed on a semiconductor substrate 11, and a nitride film (not shown) is formed on an entire structure, and then device isolation is performed. A device isolation trench is formed in the semiconductor substrate 11 by using a mask etch isolation process using a mask, and an insulating material for isolation of the device is deposited to sufficiently fill the trench, and then chemically polished (CMP) is applied to the field region. An element isolation film 14 is formed. The tunnel oxide film 12 and the first polysilicon layer 13 remain in the active region.

Referring to FIG. 1B, a masking pattern 15 partially overlapping the first polysilicon layer 13 for the floating gate formed in the active region between the device isolation layers 14 and completely covering the device isolation layer 14 is formed.

In the above, the masking pattern 15 is deposited on the device isolation layer 13 including the first polysilicon layer 13 to a thickness of 300 to 500 Å, and then patterned to sufficiently cover the device isolation layer 14. Form.

Referring to FIG. 1C, after forming the second polysilicon layer 16 for floating gate on the entire structure including the first polysilicon layer 13 on which the masking pattern 15 is formed, an etching process using a mask for the floating gate is performed. The second polysilicon layer 16 and the masking pattern 15 are patterned, and thus the patterned second polysilicon layer 16 is partially overlapped on the device isolation layer 14 together with the masking pattern 15. do.

Referring to FIG. 1D, a dielectric layer 17 and a conductive material layer 18 for control gates are formed on the entire structure including the patterned second polysilicon layer 16 and self-aligned gate etching using a mask for control gates. Process sequentially etching the underlying layers 17, 16, 15 and 13, including the conductive material layer 18 for the control gate, thereby the first polysilicon layer 13, the masking pattern 15 and the second A floating gate in which the polysilicon layer 16 is stacked is formed, and a control gate made of the conductive material layer 18 for the control gate is formed.

On the other hand, even if misalignment occurs during the floating gate mask operation, the masking pattern 15 increases the misalignment margin as much as the thickness of the masking pattern 15, but in view of the principle, the region in which misalignment occurs is a spacer. Since is formed, even if the poly over etch (poly over etch) is applied to the spacer area is thicker than the thickness of the existing masking pattern 15 to prevent the etch damage (etch damage). However, due to the application of the masking pattern 15, a poly string may be present along the protruding sidewall of the device isolation layer 14, since it may be oxidized by a subsequent process of reoxidation. It doesn't matter.

Although the above-described embodiments of the present invention have been described with reference to the NAND flash memory device, the present invention can be applied to any semiconductor device for which the coupling ratio needs to be increased.

As described above, the present invention prevents the exposure of the active region even when misalignment occurs during the floating gate mask operation in the flash memory device due to the masking pattern, and also increases the effective surface area of the floating gate due to the masking pattern to control The gate capacitive coupling ratio with the gate can be increased, thereby improving the performance and reliability of the device as well as realizing high integration of the device.

Claims (3)

Providing a substrate in which a tunnel oxide film and a first polysilicon layer are formed in an active region and a field is formed in a field region through a self-aligned device isolation process; Forming a masking pattern partially overlapping the first polysilicon layer and completely covering the device isolation layer; Forming a second polysilicon layer on the entire structure including the masking pattern, and then patterning the second polysilicon layer in an etching process using a mask for a floating gate; Forming a dielectric layer and a conductive material layer on the entire structure including the patterned second polysilicon layer, and then forming a floating gate and a control gate by a self-aligned gate etching process. The method of claim 1, The masking pattern is formed by depositing polysilicon on the device isolation layer including the first polysilicon layer to a thickness of 300 ~ 500 Å, and then patterned to cover the device isolation layer sufficiently. The method of claim 1, And the floating gate is formed by stacking the first polysilicon layer, the masking pattern, and the second polysilicon layer.