KR100865550B1 - Method for manufacturing semiconductor device having recess gate - Google Patents

Method for manufacturing semiconductor device having recess gate Download PDF

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Publication number
KR100865550B1
KR100865550B1 KR1020070049912A KR20070049912A KR100865550B1 KR 100865550 B1 KR100865550 B1 KR 100865550B1 KR 1020070049912 A KR1020070049912 A KR 1020070049912A KR 20070049912 A KR20070049912 A KR 20070049912A KR 100865550 B1 KR100865550 B1 KR 100865550B1
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KR
South Korea
Prior art keywords
mask layer
layer pattern
active region
recess
mask
Prior art date
Application number
KR1020070049912A
Other languages
Korean (ko)
Inventor
윤형순
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070049912A priority Critical patent/KR100865550B1/en
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Publication of KR100865550B1 publication Critical patent/KR100865550B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

A method for manufacturing a semiconductor device having a recess gate is provided to improve a process margin by using a line end space type mask layer pattern. An isolation layer(210) is formed to define an active region including a channel region and junction region within a semiconductor substrate(200). A first mask layer pattern(400) is formed to cover the isolation layer between an end of the active region on the semiconductor substrate and an end of an adjacent active region. The first mask layer pattern is hardened by baking or curing the first mask layer pattern. A second mask layer pattern(500) is formed to expose the channel region and to overlap the first mask layer pattern. A trench for recess channel is formed within the active region of the semiconductor substrate by performing an etch process using the second mask layer pattern and the first mask layer pattern. A recess gate is formed to be overlapped with the trench for recess channel.

Description

Method for manufacturing semiconductor device having recess gate

1A and 1B are SEM photographs showing a semiconductor device having a recess gate in the prior art.

2A through 6B are views illustrating a method of manufacturing a semiconductor device having a recess gate according to an embodiment of the present invention.

The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a recess gate.

As the design rules of devices become smaller due to the recent higher integration of DRAM cells, the size of cell transistors is reduced, and the channel length of transistors is also shortened. If the channel length of the transistor is shortened, a short channel effect occurs that causes a decrease in threshold voltage, an increase in leakage current, and a decrease in refresh characteristics. Therefore, a semiconductor device having a recess gate that suppresses short channel effects by increasing channel length has recently been proposed.

1A and 1B are diagrams illustrating a semiconductor device having a recess gate in the prior art. In particular, Figure 1b is a SEM (SEM) picture shown in Figure 1a from the top.

Referring to FIG. 1A, in the semiconductor device having the recess gate, the trench 104 is disposed at a predetermined depth from the surface of the semiconductor substrate 100 in which the active region 120 is defined by the device isolation layer 102. The gate stack 114 is arranged to overlap with the trench 104. The gate stack 114 includes a gate insulating film pattern 106, a semiconductor layer pattern 108, a metal film pattern 110, and a hard mask film pattern 112. The gate stack 114 is generally arranged in a line form, as shown in FIG. 1B, and a space of a predetermined interval is disposed between the lines. As described above, the semiconductor device having the recess gate may have a longer channel length than the semiconductor device having the planar channel, thereby reducing the short channel effect.

However, when forming the recess gates arranged in line and space form, a process margin is very weak due to a problem of forming a smaller space at the same pitch as the gate pitch. In addition, as the design rule becomes smaller, a portion A overlapping the end of the active region 120 is generated when the gate stack 114 overlapping the trench 104 is formed. As such, the portion A overlapping with the gate stack 114 may receive an attack during the etching process during the semiconductor device manufacturing process, which may cause a process margin to decrease. In order to solve this problem, a method of forming an isolated recess gate or a wave shaped recess gate for separating an overlapping active region has been proposed. However, this method has the advantage of preventing attack at the end of the active region, but there is a problem that can further reduce the process margin.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device having a recess gate capable of improving a process margin while preventing attack at the end of an active region.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device having a recess gate according to the present invention, forming a device isolation film defining an active region including a channel region and a junction region in the semiconductor substrate; Forming a first mask layer pattern on the semiconductor substrate to cover a portion of an end portion of the junction region of the active region; Modifying physical properties of the first mask layer pattern; Forming a second mask layer pattern overlying the first mask layer pattern while exposing a channel region of the semiconductor substrate; Forming a trench for a recess channel in the semiconductor substrate using the second mask layer pattern as a mask; And forming a recess gate overlapping the trench for the recess channel.

In the present invention, the mask film pattern is preferably formed of a photoresist film.

The first mask layer pattern may be modified using bake or electron beam curing.

The first mask layer pattern and the second mask layer pattern may be formed of materials having different physical properties.

The first mask layer pattern may be formed to be relatively thinner than the second mask layer pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

2A through 6B are views illustrating a method of manufacturing a semiconductor device having a recess gate according to an embodiment of the present invention.

2A and 2B, an isolation layer 210 defining a first active region 215a and a second active region 215b is formed on the semiconductor substrate 200. FIG. 2B is a diagram illustrating the cut out of FIG. 2A along the line II ′. The description thereof will be omitted below.

In detail, the trench 205 having a predetermined depth is formed in the semiconductor substrate 200. A buried insulating film is then formed to fill the trench 205. Subsequently, the buried insulating film is subjected to a planarization process, for example, a chemical mechanical polishing (CMP) process, until the surface of the semiconductor substrate 200 is exposed, thereby performing second active adjacent to the first active region 215a. An isolation layer 210 is formed so as to separate the region 215b. In this case, the first and second active regions 215a and 215b are set to include a channel region a to be formed later and a junction region b to be disposed in both the channel regions a. The channel regions a set in the first and second active regions 215a and 215b are disposed between the junction regions b, and the recess gates to be formed later overlap the channel regions. The first and second active regions 215a and 215b are disposed adjacent to each other with the device isolation layer 210 therebetween. The device isolation layer 210 may be formed using a high density plasma (HDP) film.

Referring to FIGS. 3A and 3B, a first mask layer blocking a portion d of the end of the junction region b in the first active region 215a and the second active region 215b of the semiconductor substrate 200. The pattern 300 is formed.

Specifically, the photoresist film is applied onto the semiconductor substrate 200 using a method such as spin coating. Next, a photomask is disposed on the photoresist film, and a photolithography process including an exposure process and a developing process is performed using the photomask. Then, the first mask layer pattern 300 is formed while the photoresist layer in the portion reacting with the light is removed. The first mask layer pattern 300 is formed to cover a portion of the end portion d of the junction region b and the device isolation layer 210 in the first active region 215a and the second active region 215b. The end portion region d of the junction region covered by the first mask layer pattern 300 is a region where the recess gate to be formed later overlaps. The first mask layer pattern 300 formed as described above has an area capable of sufficiently covering the end portion region d of the junction region b in the x-axis direction of the semiconductor substrate 200. In addition, the first mask layer pattern 300 may be formed to cover the device isolation layer 210 disposed between the first active region 215a and the second active region 215b. In addition, in the process of forming the recess gate, the overlap is formed so as to be located to the portion where the gate line is formed. In addition, the first mask layer pattern 300 is formed in the y-axis direction considering the overlap margin of the first active region 215a and the second active region 215b.

4A and 4B, a photo process is performed on the semiconductor substrate 200 to modify the physical properties of the first mask layer pattern 300. Specifically, an exposure process and a developing process are performed on the first mask film pattern 300 formed in FIGS. 3A and 3B. Then, the first mask film pattern 300 reacts by the exposure process and the development process using the developer, thereby changing physical properties. In this case, the method of changing the physical properties of the first mask layer pattern 300 may be performed by using a bake process or an electron beam curing process. The modified first mask layer pattern 400 prevents the modified first mask layer pattern 400 from being etched in an etching process to be subsequently performed to form a recess channel trench in the semiconductor substrate.

5A and 5B, a second mask layer pattern 500 for selectively exposing a portion of the region 510 of the semiconductor substrate 200 is formed.

Specifically, the photoresist film is coated on the semiconductor substrate 200 on which the modified first mask film pattern 400 is formed by using a spin coating method. Next, a photomask using an exposure process development process is performed on the applied photoresist film to form a second mask film pattern 500 for selectively exposing the semiconductor substrate 200. In this case, as shown in FIG. 5A, the second mask layer pattern 500 may be formed in a line and space type that traverses the active region in a straight line. In general, the line-and-space type mask film pattern is about twice as advantageous in exposure latitude as the wave type photo process margin. The region 510 exposed by the second mask layer pattern 500 is a portion where the recess channel trench is to be formed. In this case, the first mask film pattern 400 modified by the above-described physical property change process remains unaffected in the photo process proceeding to form the second mask film pattern 500. Accordingly, the first mask layer pattern 400 covering the partial region of the end portion of the junction region b in the first active region 215a and the second active region 215b remains unetched. On the other hand, it is preferable that the first mask film pattern is formed to have a thickness relatively thinner than the second mask film pattern.

6A and 6B, an etching process using the second mask layer pattern 500 as a mask is performed to form a recess channel trench 600 in the semiconductor substrate 200. The recess channel trench 600 may be formed to have a predetermined depth within the channel regions a of the first and second active regions 215a and 215b. In the etching process for forming the recess channel trench 600, a portion of the end portion d of the junction region b of the first and second active regions 215a and 215b may be formed of the modified first mask layer pattern ( Since it is covered by 400, the attack by the etching process can be prevented.

Next, the second mask film pattern 500 and the first mask film pattern 400 are removed by going through a predetermined ashing process.

7A and 7B, a gate line 720 overlapping the trench channel trench 600 may be formed. The gate line 720 may be formed in a line and space type that crosses the active region. As described above, the gate line 720 overlapping the trench channel trench 600 has a structure in which the gate insulating film 700, the conductive film 705, the metal film 710, and the hard mask film 715 are sequentially stacked. Is made of. The gate insulating film 700 may be formed of an oxide film, and the conductive film 705 may be formed of a conductive material including polysilicon. In addition, the metal film 710 may be formed of a tungsten (W) or tungsten silicide film, and the hard mask film 715 may be formed of a nitride film.

In the semiconductor device having the recess gate according to the present invention, the end portion of the active region adjacent to the isolation layer is blocked by a mask layer pattern, and then a trench for the recess channel is formed to prevent the active region end from being attacked in the etching process. can do. As a result, a trench for a recess channel may be formed using a line and space type mask without performing a mask process without a process margin.

As described so far, according to the method of manufacturing a semiconductor device having a recess gate according to the present invention, after forming a mask layer for preventing attack at the end of the active region, an etching process for forming the trench for the recess channel is performed. This can reduce the occurrence of attack in the etching process. Accordingly, the process margin may be improved by performing an etching process for forming the recess channel trench using a line-and-space type mask layer pattern having sufficient process margin.

Claims (5)

Forming an isolation layer defining an active region including a channel region and a junction region in the semiconductor substrate; Forming a first mask layer pattern on the semiconductor substrate to cover the device isolation layer between an end of an active region and an end of an adjacent active region; Curing the first mask film pattern by performing baking or electron beam curing on the first mask film pattern; Forming a second mask layer pattern overlapping the cured first mask layer pattern while exposing a channel region of the semiconductor substrate; Forming a trench for a recess channel in an active region of the semiconductor substrate by an etching process using the second mask layer pattern and the first mask layer pattern as a mask; And And forming a recess gate overlapping the trench for the recess channel. The method of claim 1, And the first mask layer pattern is formed of a photoresist layer. The method of claim 2, And the first mask layer pattern is modified using bake or electron beam curing. The method of claim 1, The first mask layer pattern and the second mask layer pattern is a method of manufacturing a semiconductor device having a recess gate, characterized in that made of a material having different physical properties. The method of claim 1, The first mask layer pattern is formed to have a thickness relatively thinner than the second mask layer pattern manufacturing method of a semiconductor device having a recess gate.
KR1020070049912A 2007-05-22 2007-05-22 Method for manufacturing semiconductor device having recess gate KR100865550B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000051433A (en) * 1999-01-22 2000-08-16 김영환 A method of forming micro-patterns in a semiconductor device
KR20050003302A (en) * 2003-06-30 2005-01-10 주식회사 하이닉스반도체 Method for manufacturing MOS transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000051433A (en) * 1999-01-22 2000-08-16 김영환 A method of forming micro-patterns in a semiconductor device
KR20050003302A (en) * 2003-06-30 2005-01-10 주식회사 하이닉스반도체 Method for manufacturing MOS transistor

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