KR20080103697A - Method for manufacturing semiconductor device having recess gate - Google Patents

Method for manufacturing semiconductor device having recess gate Download PDF

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Publication number
KR20080103697A
KR20080103697A KR1020070050746A KR20070050746A KR20080103697A KR 20080103697 A KR20080103697 A KR 20080103697A KR 1020070050746 A KR1020070050746 A KR 1020070050746A KR 20070050746 A KR20070050746 A KR 20070050746A KR 20080103697 A KR20080103697 A KR 20080103697A
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KR
South Korea
Prior art keywords
photoresist film
region
device isolation
active region
forming
Prior art date
Application number
KR1020070050746A
Other languages
Korean (ko)
Inventor
안영배
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070050746A priority Critical patent/KR20080103697A/en
Publication of KR20080103697A publication Critical patent/KR20080103697A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method of manufacturing a semiconductor device having a recess gate according to the present invention includes forming a photoresist film on a semiconductor substrate on which active regions and device isolation regions are defined; Patterning the photoresist film to form a first photoresist film pattern including an opening having a larger exposed area of the active region than an exposed area of the device isolation region; Performing a reflow process on the first photoresist film pattern to form a second photoresist film pattern that exposes a portion of the active region and blocks the device isolation region; Forming a recess trench in the semiconductor substrate by an etching process using the second photoresist film pattern as a mask; And forming a gate stack overlapping the recess trench.

Description

Method for manufacturing semiconductor device having recess gate

1 is a diagram illustrating a semiconductor device having a recess gate in the related art.

2 to 10 are views illustrating a method of manufacturing a semiconductor device having a recess gate according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a recess gate capable of improving a pattern margin when forming a recess gate.

As the design rules of devices become smaller due to the recent higher integration of DRAM cells, the size of cell transistors is reduced, and the channel length of transistors is also shortened. If the channel length of the transistor is shortened, a short channel effect occurs that causes a decrease in threshold voltage, an increase in leakage current, and a decrease in refresh characteristics. Therefore, recently, a semiconductor device having a recess gate that increases a channel length and suppresses a short channel effect has been proposed.

1 is a view illustrating a semiconductor device having a recess gate in the prior art.

Referring to FIG. 1, in the semiconductor device having the recess gate, the active region 105 is disposed on the semiconductor substrate 100 by the device isolation layer 110. In addition, a gate line 115 extending in a straight line while crossing a predetermined region of the active region 105 is arranged. In this case, a trench (not shown) having a predetermined depth is disposed in the active region 105 to overlap the gate line 115 from the surface of the semiconductor substrate 100. The gate line 115 is generally arranged in a line shape, and a space of a predetermined interval is disposed between the gate line and the gate line. The semiconductor device having the recess gate formed as described above has a longer channel length than the semiconductor device having the planar channel, thereby reducing the short channel effect.

On the other hand, the gate line extending in the form of a line is set in consideration of the margin (margin) and critical dimension uniformity (critical dimension uniformity) of the pattern. This is because simple patterns, such as line and space types, are advantageous in terms of margin and critical uniformity. However, gate lines arranged in a line-and-space form have a problem of insufficient overlay margin between the device isolation layer 110 and the gate line 115 as the process margin decreases as the degree of integration of semiconductor devices increases. If the overlay margin between the device isolation layer 110 and the gate line 115 is insufficient, a portion A of which the gate line 115 overlaps at an end portion of the active region 105 may occur. As such, the portion A where the active region 105 ends and the gate line 115 overlap with each other may be attacked in an etching process that is performed during the semiconductor device manufacturing process, thereby reducing the process margin. Problems may arise.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device having a recess gate capable of preventing attack at an end portion of an active region and improving a pattern margin.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device having a recess gate according to the present invention, forming a photoresist film on a semiconductor substrate defined active region and device isolation region; Patterning the photoresist film to form a first photoresist film pattern including an opening having a larger exposed area of an active region than an exposed area of the device isolation region; Performing a reflow process on the first photoresist film pattern to form a second photoresist film pattern that exposes a portion of the active region and blocks the device isolation region; Forming a recess trench in the semiconductor substrate by an etching process using the second photoresist layer pattern as a mask; And forming a gate stack overlapping the recess trench.

In the present invention, the forming of the first photoresist film pattern includes: disposing a wave type photomask on the photoresist film; Performing an exposure process using the photomask; And removing a predetermined region of the photoresist film modified by the exposure process.

The wave type photomask may include a protrusion in which the light transmitting region and a portion of the light blocking region protrude by a predetermined length in the light transmitting region direction.

The protrusion may be disposed at a position corresponding to an end portion of an active region in which the active region and the device isolation region are adjacent to each other.

In the reflow step, it is preferable to apply heat of a predetermined temperature to the photoresist film pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

2 to 10 are views illustrating a method of manufacturing a semiconductor device having a recess gate according to an embodiment of the present invention.

Referring to FIG. 2, an isolation layer 210 defining an active region 205 is formed on a semiconductor substrate 200.

Specifically, trenches having a predetermined depth are formed in the semiconductor substrate 200. Next, the trench is filled with an insulating film. Subsequently, a planarization process, for example, a chemical mechanical polishing (CMP) process, is performed on the insulating layer until the surface of the semiconductor substrate is exposed to form an isolation layer 210 separating the active region and the isolation region. . The device isolation layer 210 may be formed using an oxide film, for example, a high density plasma (HDP) film.

Referring to FIG. 3, a photoresist film 215 is formed on the semiconductor substrate 200 on which the device isolation film 210 is formed. The photoresist film 215 is formed by applying a photoresist material using a spin coating method. Next, the photomask 220 is disposed on the semiconductor substrate 200 on which the photoresist film 215 is formed. As illustrated in FIG. 4, the photomask 220 includes a light transmitting region a and a light blocking region c. The photomask 220 includes a protrusion in which a portion of the light blocking area c protrudes by a predetermined length b in the direction of the light transmitting area a. In this case, the protrusion of the light blocking region c has a wave type structure in which the active region and the device isolation layer are disposed at positions corresponding to the terminal portions adjacent to each other. In this case, the photomask disposed on the device isolation region is an area for improving patterning margin and improving critical dimension (CD) uniformity during the exposure process.

Next, a photolithography process including an exposure process and a developing process is performed using the photomask 220 and the illumination system. As a result, the photoresist film 215 of the portion 225 exposed to the light transmitted to the light-transmitting region a of the photomask 220 is modified.

5 and 6, the first photoresist film pattern for selectively exposing a portion of the surface d of the active region of the semiconductor substrate 200 by removing the denatured portion 225 of the photoresist film 215. To form 230. The exposed region d of the active region of the semiconductor substrate 200 exposed by the first photoresist layer pattern 230 formed as described above is formed to have a relatively larger size than the exposed region e of the device isolation region. desirable. This is to prevent the exposed region d of the active region from being covered by a photoresist reflow process to be performed later. In addition, the exposed region e of the device isolation region may be formed to have a line width that may generate a bridge in a reflow process. Then, as shown in FIG. 6, the first photoresist layer pattern 230 may have a small pattern threshold dimension CD of the long axis portion of the isolation layer.

7 and 8, the photoresist reflow process is performed on the first photoresist film pattern 230, so that the size 237 of the critical dimension CD is greater than the first photoresist film pattern 230. The second photoresist film pattern 235 reduced inwardly is formed. In this case, the exposed region (e, see FIG. 6) of the device isolation region is covered with a photoresist film during the reflow process. Accordingly, the second photoresist layer pattern 235 exposes the surface of the semiconductor substrate 200 in the region 240 where the recess trench is to be formed.

Referring to FIG. 9, a region in which the second photoresist layer pattern 235 is exposed using a mask is etched to form a recess trench 245 having a predetermined depth in the semiconductor substrate 200. Then, as shown in FIG. 10, the recess trench 245 is formed only in the active region, and is not formed in the device isolation layer 210.

Referring to FIG. 11, a gate stack 270 overlapping the recess trench 245 formed in the semiconductor substrate 200 is formed.

Specifically, a gate insulating film is formed on the semiconductor substrate 200. Next, a conductive film, a metal film, and a hard mask film are sequentially deposited on the gate insulating film. Next, the stacked structures are patterned to form a gate stack 270 having a structure in which a hard mask layer pattern 265, a metal layer pattern 260, a conductive layer pattern 255, and a gate insulating layer pattern 250 are stacked. . The gate insulating film pattern 250 may be formed of an oxide film, and the conductive film pattern 255 may be formed of a polysilicon film. In addition, the metal film pattern 260 may be formed of a tungsten film or a tungsten silicide film, and the hard mask film pattern 265 may be formed of a nitride film.

The method of manufacturing a semiconductor device having a recess gate according to the present invention can improve a phenomenon that an attack occurs in an active region adjacent to the device isolation layer due to the lack of an overlay margin between the device isolation layer and the recess gate. Particularly, a pattern for forming a recess trench on the device isolation layer by applying a photoresist reflow process, while using a wave type photomask capable of forming a small patterning threshold dimension (CD) of an active region adjacent to the device isolation layer. To prevent it from being formed. As the size of the development inspection critical dimension (DICD) of the recess trench increases on the device isolation layer, as the margin increases, the active region adjacent to the device isolation layer may be prevented from being attacked.

As described so far, according to the method of manufacturing a semiconductor device having a recess gate according to the present invention, a mask for forming a recess gate is formed only on an active region so that misalignment between the device isolation layer and the recess gate occurs. As a result, a phenomenon in which the terminal of the device isolation layer is attacked can be prevented. Accordingly, long-term overlay management of the device isolation layer can be relaxed. In addition, the photoresist reflow process may be performed to secure the critical dimension of the recess gate pattern on the active region, thereby improving the pattern margin.

Claims (4)

Forming a photoresist film on the semiconductor substrate in which the active region and the device isolation region are defined; Patterning the photoresist film to form a first photoresist film pattern including an opening having a larger exposed area of an active region than an exposed area of the device isolation region; Performing a reflow process on the first photoresist film pattern to form a second photoresist film pattern that exposes a portion of the active region and blocks the device isolation region; Forming a recess trench in the semiconductor substrate by an etching process using the second photoresist layer pattern as a mask; And Forming a gate stack overlapping the recess trench. The method of claim 1, wherein the forming of the first photoresist film pattern comprises: Disposing a wave type photomask on the photoresist film; Performing an exposure process using the photomask; And And removing a predetermined region of the photoresist film modified by the exposure process. The method of claim 2, The wave type photomask includes a protrusion in which a portion of the light blocking region protrudes by a predetermined length in a direction of the light transmitting region. The method of claim 3, And the protrusion is disposed at a position corresponding to an end portion of an active region in which the active region and the device isolation region are adjacent to each other.
KR1020070050746A 2007-05-25 2007-05-25 Method for manufacturing semiconductor device having recess gate KR20080103697A (en)

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