KR20040043152A - Driving method of plasma display panel - Google Patents

Abstract

PURPOSE: A method for driving a plasma display panel is provided to form uniform wall charges in discharge cells by equally setting up periods for applying scan pulses in line units or block units after applying reset pulses to all discharge cells. CONSTITUTION: Reset pulses of ramp waveform are applied to the first electrodes during a reset period. Scan pulses are applied to the first electrodes during an address period. Data pulses synchronized with the scan pulses are applied to an address electrode crossing the first electrode in order to select the discharge cells of emitting states during the address period. The first voltage is applied to the second electrodes adjacent to the first electrodes when the ramp waveform is applied to the first electrodes. The second voltage is applied to the second electrodes before the first scan pulses are applied to the first electrodes.

Description

Driving method of plasma display panel {DRIVING METHOD OF PLASMA DISPLAY PANEL}

The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel to improve image quality.

Recently, a plasma display panel (hereinafter referred to as "PDP"), which is easy to manufacture a large panel, has attracted attention as a flat panel display device. As a PDP, a three-electrode AC surface discharge type PDP having three electrodes and driven by an alternating voltage is typical.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a first electrode 12Y and a second electrode 12Z formed on the upper substrate 10, and an address formed on the lower substrate 18. An electrode 20X is provided.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the first electrode 12Y and the second electrode 12Z side by side. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 14. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the first electrode 12Y and the second electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower plates and the partition wall.

These discharge cells are arranged in a matrix form as shown in FIG. In FIG. 2, the discharge cells 1 are provided at the intersections of the first electrode lines Y1 to Ym, the second electrode lines Z1 to Zm, and the address electrode lines X1 to Xn. The first electrode lines Y1 to Ym are sequentially driven, and the second electrode lines Z1 to Zm are commonly driven. The address electrode lines X1 to Xn are driven by being divided into odd-numbered lines and even-numbered lines.

The three-electrode AC surface discharge type PDP is driven by being divided into a plurality of subfields, and gray scale display is performed by emitting light a number of times proportional to the weight of video data in each subfield period.

For example, when an image is displayed in 256 gray scales using 8-bit video data, one frame display period (for example, 1/60 second = about 16.7 msec) in each discharge cell 1 is shown in FIG. As shown, the data is divided into eight subfields SF1 to SF8.

Each subfield SF1 to SF8 is further divided into a reset period, an address period and a sustain period, and 1: 2: 4: 8:... The weight is given at the ratio of 128. Here, the reset period is a period for initializing the discharge cells, the address period is a period for causing selective address discharge according to the logic value of the video data, and the sustain period is such that discharge is maintained in the discharge cells in which the address discharge has occurred. It is a period. The reset period and the address period are equally assigned to each subfield period.

4 is a waveform diagram showing a conventional method for driving a PDP.

Referring to FIG. 4, the conventional driving method of the PDP is divided into a reset period, an address period, and a sustain period.

In the reset period, the reset pulse RP is commonly supplied to the first electrode lines Y1 to Ym to initialize the discharge cells. In the address period, the scan pulse SP is sequentially applied to the first electrode lines Y1 to Ym, and the data pulse DP synchronized with the scan pulse SP is applied to the address electrode line X. At this time, address discharge occurs in the discharge cells to which the scan pulse SP and the data pulse DP are applied. In the sustain period, sustain pulses SUSPy and SUSPz are alternately applied to the first electrode lines Y1 to Ym and the second electrode lines Z1 to Zm to sustain sustain discharge for a predetermined time in a discharge cell in which an address discharge occurs. Cause

The reset pulse RP applied in the reset period will now be described in detail. First, reset discharge occurs in the discharge cells in the period t1 in which the reset pulse RP rises with a predetermined slope. Therefore, predetermined wall charges are formed in the discharge cells in the period t1. In the t2 period, the wall charges formed in the t1 period are maintained with a predetermined voltage value. In the t3 period, the wall charge formed in the t1 period is maintained with the voltage value lower than the t2 period. In the period t4, the wall charges formed in the discharge cells are uniformly distributed while the voltage value gradually falls with a predetermined slope. In this way, the wall charges formed in the discharge cells during the reset period are provided with the wall cells corresponding to the amount of wall charges to the discharge cells so that address discharge can easily occur.

Following the reset period, the scan pulse SP is sequentially supplied to the first electrode lines Y1 to Ym in the address period, and the data pulse DP synchronized with the scan pulse SP is the address electrode lines X1 to Xn. Is supplied. At this time, whether or not the data pulse DP is supplied is determined by the image displayed on the panel. On the other hand, address discharge occurs in the discharge cells supplied with the scan pulse SP and the data pulse DP. In the discharge cells in which the address discharge is generated, predetermined wall charges are formed by the address discharge.

Subsequently, in the sustain period, the sustain discharges are discharged in the discharge cells in which the address discharge is generated by supplying the sustain pulses SUSPy and SUSPz to the first electrode lines Y1 to Ym and the second electrode lines Z1 to Zm alternately. To be maintained for a predetermined period of time.

However, in the conventional PDP, the time when the scan pulse SP is supplied after the reset pulse RP is supplied to the first electrode lines Y1 to Ym is set differently. That is, as shown in FIG. 5, after the reset pulse RP is applied to the Y1 th first electrode line Y1, the scan pulse SP is applied after t5 hours. In addition, the scan pulse SP is applied to the Ym / 2 th first electrode line Ym / 2 after t6 hours after the reset pulse RP is applied. In addition, the scan pulse SP is applied to the Ym-th first electrode line Ym after t7 hours after the reset pulse RP is applied. Here, the magnitudes of the times t7, t6 and t5 are determined in order of t7 > t6 > t5.

In other words, in the conventional PDP, the application order of the scan pulse SP applied to the first electrode lines Y1 to Ym after the reset pulse RP is set differently. On the other hand, the wall charges generated by the reset discharge are dissipated over time by recombination. Therefore, since the application order of the scan pulse SP applied to the first electrode lines Y1 to Ym after the reset pulse RP is applied is different, the uniformity of the discharge cells is reduced. In addition, the discharge cells to which the scan pulse SP is applied after a predetermined time after the reset pulse RP is applied to the disappearance of the wall charges generated by the reset discharge (that is, the drop in the wall voltage due to the substation charges). As a result, address discharge may not occur. In addition, after a predetermined time after the reset pulse RP is applied, the discharge cells to which the scan pulse SP is applied have weak address discharges due to the disappearance of the wall charges generated by the reset discharges. It does not occur, resulting in deterioration of image quality.

Accordingly, an object of the present invention is to provide a method for driving a plasma display panel that can improve image quality.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 illustrates a plasma display panel in which the discharge cells shown in FIG. 1 are arranged in a matrix form.

3 is a diagram illustrating a gray scale expression method of a conventional plasma display panel.

4 is a waveform diagram illustrating a method of driving the conventional plasma display panel shown in FIG. 1.

5 is a waveform diagram showing in detail a driving waveform applied to a conventional first electrode.

6 is a waveform diagram showing a driving method of a plasma display panel according to a first embodiment of the present invention;

7 is a waveform diagram showing a method of driving a plasma display panel according to a second embodiment of the present invention;

8 is a waveform diagram showing a driving method of a plasma display panel according to a third embodiment of the present invention;

9 is a waveform diagram showing a driving method of a plasma display panel according to a fourth embodiment of the present invention;

10 is a waveform diagram showing a driving method of a plasma display panel according to a fifth embodiment of the present invention;

Fig. 11 is a waveform diagram showing a driving method of a plasma display panel according to a sixth embodiment of the present invention.

12 is a waveform diagram showing a method of driving a plasma display panel according to a seventh embodiment of the present invention;

13 is a view showing a charge generated by the reset discharge of FIG.

<Description of Symbols for Main Parts of Drawings>

1: discharge cell 10: upper substrate

12Y: first electrode 12Z: second electrode

14,22 dielectric layer 16: protective film

18: lower substrate 20X: address electrode

24: partition 26: phosphor layer

In order to achieve the above object, a driving method of the plasma display panel according to the present invention includes applying a reset pulse of a ramp waveform to the first electrodes in a reset period, and applying a scan pulse to the first electrodes in an address period; Applying a data pulse synchronized with the scan pulses to the address electrode formed to intersect the first electrode to select a discharge cell to be turned on in the address period, and when the ramp waveform is applied to the first electrodes. The first voltage is applied to the second electrodes formed adjacent to the electrode, and the second voltage is applied to the second electrodes before the first scan pulse is applied to the first electrodes.

The voltage level of the second voltage is set higher than the voltage level of the first voltage.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 13.

6 is a waveform diagram illustrating a method of driving a plasma display panel according to a first embodiment of the present invention.

Referring to FIG. 6, the driving method of the PDP according to the first embodiment of the present invention is driven by being divided into a reset / address period and a sustain period. In the reset / address period, the reset pulse RP and the scan pulse SP are applied to the first electrode lines Y1 to Ym. In the sustain period, sustain pulses SUSPy and SUSPz are alternately applied to the first electrode lines Y1 to Ym and the second electrode lines Z1 to Zm.

In the PDP driving method according to the first embodiment of the present invention, the time t8 when the scan pulse SP is supplied after the reset pulse RP is supplied is the same in all the first electrode lines Y1 to Ym. Is set to. Therefore, when the scan pulse SP is supplied to all the discharge cells, uniform wall charges are formed in the discharge cells.

In detail, the reset pulse RP supplied to the Y1 th first electrode line Y1 is a period t1 during which the voltage rises to the first voltage with a predetermined slope, a period t2 for maintaining the first voltage value, and a first period. The driving is divided into a period t3 for maintaining the second voltage value lower than the voltage value and a period t4 for falling with a predetermined slope.

In the t1 period, the reset pulse RP rises to the first voltage with a predetermined slope. At this time, a reset discharge is generated in the discharge cell to form predetermined wall charges. In the t2 period, the wall charges formed in the t1 period are maintained for a predetermined time (that is, the time of t2) with the first voltage. In the t3 period, the second voltage value, which is lower than the first voltage value, is maintained for a predetermined time (that is, the time of t3) and the wall charges formed in the discharge cells are maintained. In the t4 period, the wall voltage formed in the discharge cells is uniformly distributed while the first voltage value gradually falls with a predetermined slope. After the reset pulse RP is supplied, the scan pulse SP is applied after a predetermined time t8.

On the other hand, the reset pulse RP supplied to the Y2 th first electrode line Y2 is lower than the voltage supplied in the period t1 during which the predetermined slope is displayed and rises, the period t5 for maintaining the first voltage value, and the period t5. The driving is divided into a period t3 for maintaining the second voltage value and a period t4 for falling with a predetermined slope. Here, the periods t1, t3, and t4 are set to be the same so that the scan pulse SP can be applied after a predetermined time t8 after the reset pulse RP is supplied, while the period t5 for maintaining the first voltage value. Is set greater than the period t2 in which the first voltage value is maintained in the first Y1 first electrode line Y1. Therefore, according to the driving method of the PDP according to the embodiment of the present invention, the time t8 when the scan pulse SP is applied after the reset pulse RP is supplied is the same in all the first electrode lines Y1 to Ym. Is set.

In other words, t1 and t3 of the reset pulses RP supplied to all the first electrode lines Y1 so that the scan pulses SP can be applied after a predetermined time t8 after the reset pulses RP are supplied. The period t4 is set equally in all the first electrode lines Y1 to Ym, while the periods t2, t5, t6, ..., t7 for maintaining the first voltage value are set differently. Therefore, according to the PDP according to the first embodiment of the present invention, since the address discharge occurs after the constant (uniform) wall charge is formed in all the discharge cells, the image quality can be improved.

7 is a waveform diagram illustrating a method of driving a plasma display panel according to a second embodiment of the present invention.

Referring to FIG. 7, in the method of driving a plasma display panel according to the second embodiment of the present invention, the same reset pulse RP is supplied to at least two or more first electrode lines Y. That is, in the second embodiment of the present invention, different reset pulses RP are supplied for each block.

In detail, the reset pulse RP supplied to the first block (here, the Y1 and Y2 electrodes) is a period t1 during which the voltage rises to the first voltage with a predetermined slope, a period t2 for maintaining the first voltage value, and a first period. The driving is divided into a period t3 for maintaining the second voltage value lower than the voltage value and a period t4 for falling with a predetermined slope.

In the t1 period, the reset pulse RP rises to the first voltage with a predetermined slope. At this time, a reset discharge is generated in the discharge cell to form predetermined wall charges. In the t2 period, the wall charges formed in the t1 period are maintained for a predetermined time (that is, the time of t2) with the first voltage. In the t3 period, the second voltage value, which is lower than the first voltage value, is maintained for a predetermined time (that is, the time of t3) and the wall charges formed in the discharge cells are maintained. In the t4 period, the wall voltage formed in the discharge cells is uniformly distributed while the first voltage value gradually falls with a predetermined slope. As such, when the same reset pulse RP is supplied to the first blocks Y1 and Y2, the scan pulse SP supplied to the Y1 electrode line Y1 is supplied after a time t8. In addition, the scan pulse SP supplied to the Y2 electrode line Y2 is supplied after the time t9. That is, since the reset pulses RP having the same width are applied to the electrode lines Y1 and Y2 included in the first block, the time when the scan pulse SP is applied after the reset pulse RP is different. However, since the scan pulses are sequentially applied to the electrode lines Y1 and Y2 included in the first block, the wall charges formed by the reset pulse RP are not recombined.

On the other hand, the reset pulse RP supplied to the second block (here, Y3 and Y4 electrodes) is lower than the voltage supplied in the period t1 during which it rises with a predetermined slope, the period t5 for maintaining the first voltage value, and the period t5. The driving is divided into a period t3 for maintaining the second voltage value and a period t4 for falling with a predetermined slope. Here, the periods of t1, t3, and t4 are set to be the same so that the scan pulse SP can be applied after a predetermined time (t8, t9) after the reset pulse RP is supplied, while maintaining the first voltage value. The t5 period is set larger than the t2 period of the first block. Therefore, according to the driving method of the PDP according to the embodiment of the present invention, the times t8 and t9 to which the scan pulse SP is applied after the reset pulse RP is supplied are set equally for each block.

In other words, the periods t1, t3, and t4 of the reset pulses RP supplied to all the first blocks so that the scan pulses SP can be applied after a predetermined time (t8, t9) after the reset pulses RP are supplied. Is set equal in all blocks, while periods t2, t5, ..., t6 for maintaining the first voltage value are set differently. Therefore, according to the PDP according to the first embodiment of the present invention, it is possible to form uniform wall charges in all blocks.

8 is a waveform diagram illustrating a method of driving a plasma display panel according to a third embodiment of the present invention.

Referring to FIG. 8, the driving method of the PDP according to the third embodiment of the present invention is driven by being divided into a reset / address period and a sustain period. In the reset / address period, the reset pulse RP and the scan pulse SP are applied to the first electrode lines Y1 to Ym. In the sustain period, sustain pulses SUSPy and SUSPz are alternately applied to the first electrode lines Y1 to Ym and the second electrode lines Z1 to Zm.

In the driving method of the PDP according to the third embodiment of the present invention, the time t8 when the scan pulse SP is supplied after the reset pulse RP is supplied is the same in all the first electrode lines Y1 to Ym. Is set to. Therefore, when the scan pulse SP is supplied to all the discharge cells, uniform wall charges are formed in the discharge cells.

In detail, the reset pulse RP supplied to the Y1 th first electrode line Y1 is a period t1 during which the voltage rises to the first voltage with a predetermined slope, a period t2 for maintaining the first voltage value, and a first period. The driving is divided into a period t3 for maintaining the second voltage value lower than the voltage value and a period t4 for falling with a predetermined slope.

In the t1 period, the reset pulse RP rises to the first voltage with a predetermined slope. At this time, a reset discharge is generated in the discharge cell to form predetermined wall charges. In the t2 period, the wall charges formed in the t1 period are maintained for a predetermined time (that is, the time of t2) with the first voltage. In the t3 period, the second voltage value, which is lower than the first voltage value, is maintained for a predetermined time (that is, the time of t3) and the wall charges formed in the discharge cells are maintained. In the t4 period, the wall voltage formed in the discharge cells is uniformly distributed while the first voltage value gradually falls with a predetermined slope. After the reset pulse RP is supplied, the scan pulse SP is applied after a predetermined time t8.

On the other hand, the reset pulse RP supplied to the Y2 th first electrode line Y2 is lower than the voltage supplied in the period t1 during which the predetermined slope is displayed and rises, the period t2 for maintaining the first voltage value, and the period t2. The driving is divided into a period t5 for maintaining the second voltage value and a period t4 for falling with a predetermined slope. Here, the periods of t1, t2, and t4 are equally set in all the first electrode lines Y1 to Ym so that the scan pulse SP can be applied after a predetermined time t8 after the reset pulse RP is supplied. On the other hand, the t5 period for maintaining the second voltage value is set larger than the t3 period for maintaining the second voltage value in the Y1 th first electrode line Y1. Therefore, according to the driving method of the PDP according to the embodiment of the present invention, the time t8 when the scan pulse SP is applied after the reset pulse RP is supplied is the same in all the first electrode lines Y1 to Ym. Is set.

In other words, t1 and t2 of the reset pulses RP supplied to all the first electrode lines Y1 so that the scan pulses SP can be applied after a predetermined time t8 after the reset pulses RP are supplied. The t4 periods are set the same while the periods (t3, t5, t6, ..., t7) for holding the second voltage value are set differently. Therefore, according to the PDP according to the third embodiment of the present invention, since the address discharge occurs after the constant (uniform) wall charge is formed in all the discharge cells, the image quality can be improved.

Meanwhile, in the present invention, the first and third embodiments may be mixed to perform address discharge after constant wall charge is formed in all discharge cells. That is, the period for holding the first voltage and the period for holding the second voltage can be set to be wide in order (that is, the order in which the scan pulse SP is applied).

9 is a waveform diagram illustrating a method of driving a plasma display panel according to a fourth embodiment of the present invention.

Referring to FIG. 9, in the driving method of the plasma display panel according to the fourth embodiment of the present invention, the same reset pulse RP is supplied to at least two or more first electrode lines Y. That is, in the fourth embodiment of the present invention, different reset pulses RP are supplied for each block.

In detail, the reset pulse RP supplied to the first block (here, the Y1 and Y2 electrodes) is a period t1 during which the voltage rises to the first voltage with a predetermined slope, a period t2 for maintaining the first voltage value, and a first period. The driving is divided into a period t3 for maintaining the second voltage value lower than the voltage value and a period t4 for falling with a predetermined slope.

In the t1 period, the reset pulse RP rises to the first voltage with a predetermined slope. At this time, a reset discharge is generated in the discharge cell to form predetermined wall charges. In the t2 period, the wall charges formed in the t1 period are maintained for a predetermined time (that is, the time of t2) with the first voltage. In the t3 period, the second voltage value, which is lower than the first voltage value, is maintained for a predetermined time (that is, the time of t3) and the wall charges formed in the discharge cells are maintained. In the t4 period, the wall voltage formed in the discharge cells is uniformly distributed while the first voltage value gradually falls with a predetermined slope. As such, when the same reset pulse RP is supplied to the first blocks Y1 and Y2, the scan pulse SP supplied to the Y1 electrode line Y1 is supplied after a time t8. In addition, the scan pulse SP supplied to the Y2 electrode line Y2 is supplied after the time t9. That is, since the reset pulses RP having the same width are applied to the electrode lines Y1 and Y2 included in the first block, the time when the scan pulse SP is applied after the reset pulse RP is different. However, since the scan pulses are sequentially applied to the electrode lines Y1 and Y2 included in the first block, the wall charges formed by the reset pulse RP are not recombined.

On the other hand, the reset pulse RP supplied to the second block (here Y3 and Y4 electrodes) is lower than the voltage supplied in the period t1, the period t2 maintaining the first voltage value, and the period t2 maintaining the first voltage value. The driving is divided into a period t5 for maintaining the second voltage value and a period t4 for falling with a predetermined slope. Here, the periods of t1, t2, and t4 are set equal to each other so that the scan pulse SP can be applied after a predetermined time t8, t9 after the reset pulse RP is supplied, while maintaining the second voltage value. The t5 period is set larger than the t3 period of the first block. Therefore, according to the driving method of the PDP according to the embodiment of the present invention, the times t8 and t9 to which the scan pulse SP is applied after the reset pulse RP is supplied are set equally for each block.

In other words, the period t1, t2 and t4 of the reset pulse RP supplied to all the first blocks so that the scan pulse SP can be applied after a predetermined time t8 and t9 after the reset pulse RP is supplied. Is set equal in all blocks, while periods t3, t5, ..., t6 for maintaining the first voltage value are set differently. Therefore, according to the PDP according to the first embodiment of the present invention, it is possible to form uniform wall charges in all blocks.

10 is a waveform diagram illustrating a method of driving a plasma display panel according to a fifth embodiment of the present invention.

Referring to FIG. 10, in the driving method of the plasma display panel according to the fifth embodiment of the present invention, the scan pulse SP is supplied after the reset pulse RP is supplied from all the first electrode lines Y1 to Ym. The application time point of the reset pulse RP is set differently so that the time t8 becomes the same. Therefore, when the scan pulse SP is supplied to all the discharge cells, uniform wall charges are formed in the discharge cells.

In detail, the scan pulse SP is supplied after the time t8 after the reset pulse RP is supplied to the Y1 th first electrode line Y1. The reset pulse RP supplied to the Y2 th first electrode line Y1 is applied later than the reset pulse RP supplied to the Y1 th first electrode line Y1. At this time, the supply timing of the reset pulse RP supplied to the Y2 th first electrode line Y1 is set such that the scan pulse SP may be applied after a time t8 when the reset pulse RP is applied. That is, according to the fifth embodiment of the present invention, the application time of the reset pulse RP may be set differently in all the first electrode lines Y1 to Ym to form uniform wall charges in the discharge cells. Therefore, according to the PDP according to the fifth embodiment of the present invention, since the address discharge occurs after the constant (uniform) wall charge is formed in all the discharge cells, the image quality can be improved.

Meanwhile, the first to fifth embodiments of the present invention may be applied to a dual scan plasma display panel.

For example, when the first embodiment is applied to a dual scan plasma display panel, a driving waveform shown in FIG. 11 appears.

Referring to FIG. 11, in the method of driving a plasma display panel according to a sixth embodiment of the present invention, the first electrode lines Y1 to Ym are formed of upper blocks Y1 to Ym / 2 and lower blocks Ym / 2 +. 1 to Ym). The first electrode lines Y1 to Ym / 2 included in the upper block are driven in the same manner as in the first embodiment of the present invention. In addition, the first electrode lines Ym / 2 + 1 to Ym included in the lower block are driven in the same manner as the upper block. Therefore, according to the driving method of the plasma display panel according to the sixth embodiment of the present invention, since the address discharge occurs after the constant wall charge is formed in all the discharge cells, the image quality can be improved. On the other hand, such a dual scan method can be equally applied to the second to fifth embodiments of the present invention.

12 is a waveform diagram illustrating a method of driving a plasma display panel according to a seventh embodiment of the present invention.

Referring to FIG. 12, the driving method of the PDP according to the seventh embodiment of the present invention is driven by being divided into a reset period, an address period, and a sustain period. In the reset period, the reset pulse RP is applied to the first electrode lines Y1 to Ym to form uniform wall charges in the discharge cells. In the address period, the scan pulse SP is applied to the first electrode lines Y1 to Ym, and the data pulse DP is applied to the address electrode lines X1 to Xn. At this time, address discharge occurs in the discharge cells to which the scan pulse SP and the data pulse DP are applied. In the sustain period, sustain pulses SUSPy and SUSPz are alternately applied to the first electrode lines Y1 to Ym and the second electrode lines Z1 to Zm to generate sustain discharges in the discharge cells caused by the address discharges.

In the PDP driving method according to the seventh embodiment of the present invention, when the reset pulse RP is applied to the first electrode lines Y1 to Ym, the first voltage Vz1 is applied to the second electrode lines Z1 to Zm. Is applied. In addition, when the scan pulse SP is applied to the first electrode lines Y1 to Ym, the second voltage Vz2 having a voltage value higher than the first voltage Vz1 is applied to the second electrode lines Z1 to Zm. Is approved. The second voltage Vz2 applied to the second electrode lines Z1 to Zm is supplied before the scan pulse SP is applied to the first first electrode line Y1 after the reset pulse RP ends. The second voltage Vz2 is maintained until the last scan pulse SP is supplied to the first electrode line Ym. As such, when the second voltage Vz2 is supplied to the second electrode line Z, the wall charges generated during the reset period may be prevented from disappearing, thereby causing stable address discharge.

In detail, positive wall charges are formed on the address electrode X and negative wall charges are formed on the first and second electrodes Y and Z as shown in FIG. 13 by the reset discharge generated in the reset period. do. That is, a positive reset pulse RP is applied to the first electrode Y to form negative wall charges. In addition, the first voltage Vz1 is applied to the second electrode Z formed adjacent to the first electrode Y to form negative wall charges. On the other hand, positive wall charges are formed in the address electrode X having a lower potential than the first electrode Y and the second electrode Z. FIG. After this reset period, a second voltage Vz2 having a voltage higher than the first voltage Vz1 is applied to the second electrode Z.

When a positive second voltage Vz2 is applied to the second electrode Z, recombination of negative wall charges formed on the second electrode Z is prevented. That is, a second positive voltage Vz2 is applied to the second electrode Z to maintain wall charges formed on the second electrode Z. As described above, in the third embodiment of the present invention, after the reset pulse RP is applied and before the first scan pulse SP is applied, the wall formed in the discharge cell by applying the second voltage Vz2 to the second electrode Z. This prevents recombination of charges. Therefore, according to the PDP according to the seventh embodiment of the present invention, since the stable address discharge can be caused, the PDP image quality can be improved.

As described above, according to the driving method of the plasma display panel according to the present invention, after the reset pulse is applied to all the discharge cells, the time for which the scan pulse is applied is set to be the same for each line or block to uniform wall charge in the discharge cells. Can be formed. Therefore, stable address discharge can be caused in the discharge cells to which the data pulse is applied in the address period.

In addition, according to the driving method of the plasma display panel according to the present invention, the recombination of the wall charges generated by the reset discharge is prevented, and thus stable address discharge can be generated in the address period. That is, according to the plasma display panel according to the present invention, the image quality of the plasma display panel can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (2)

Applying a reset pulse of a ramp waveform to the first electrodes in the reset period; Applying a scan pulse to the first electrodes in an address period; Applying a data pulse synchronized with the scan pulses to an address electrode formed to intersect the first electrode to select a discharge cell to be turned on in the address period; Applying a first voltage to second electrodes formed adjacent to the first electrode when the ramp waveform is applied to the first electrodes; And applying a second voltage to the second electrodes before the first scan pulse is applied to the first electrodes. The method of claim 1, And the voltage level of the second voltage is set higher than the voltage level of the first voltage.