KR20040042060A - Method for forming the metal line in semiconductor device - Google Patents
Method for forming the metal line in semiconductor device Download PDFInfo
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- KR20040042060A KR20040042060A KR1020020070183A KR20020070183A KR20040042060A KR 20040042060 A KR20040042060 A KR 20040042060A KR 1020020070183 A KR1020020070183 A KR 1020020070183A KR 20020070183 A KR20020070183 A KR 20020070183A KR 20040042060 A KR20040042060 A KR 20040042060A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 공정 중 금속배선 형성방법에 관한 것으로,실리콘기판 상에 금속 배선을 형성하고, 그 금속 배선의 상부 양 측벽에 금속 배선 형성물질과 같은 물질로 이루어진 스페이서를 형성함으로써, 상기 금속 배선의 상부 면적이 넓어져 후속 금속배선을 연결하기 위한 비아(via) 형성 시, 금속 배선에 대한 비아의 오버레이 마진을 확보할 수 있고, 그에 따라 비아 형성을 위한 마스크 오정렬에 따른 불량을 방지하여 공정 수율 및 소자동작의 신뢰성을 향상시킬 수 있도록 하는 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring during the manufacturing process of a semiconductor device, by forming a metal wiring on the silicon substrate, by forming a spacer made of the same material as the metal wiring forming material on the upper sidewalls of the metal wiring, When the upper area of the metal wiring is widened, when forming vias for connecting subsequent metal wirings, an overlay margin of vias to the metal wirings can be secured, thereby preventing defects due to mask misalignment for forming vias. The present invention relates to a method for forming metal wirings to improve process yield and reliability of device operation.
최근 반도체 소자의 사이즈가 작아짐에 따라 반도체소자의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 상하의 도전배선과 이를 연결하는 비아(via)는 소자가 고집적화 되어감에 따라 자체의 크기와 주요 배선과의 간격이 미세화되고 있다.Recently, as the size of semiconductor devices decreases, the trend of high integration of semiconductor devices is greatly influenced by the development of fine pattern formation technology, and the upper and lower conductive wirings and vias connecting them have their own sizes as the devices become highly integrated. The spacing between and the main wiring is becoming smaller.
그런데, 상기 상하의 도전배선을 연결하기 위한 비아를 형성하는 공정에 있어서는, 상하의 도전배선 사이에 상하의 도전배선을 절연하기 위해 형성된 층간절연막 상부에 감광막 패턴 즉, 층간절연막 상부에 비아 형성영역이 정의되도록 감광막 패턴을 형성한 다음, 이를 마스크로 층간절연막을 식각하여 상하의 도전배선을 연결하는 비아를 형성하고 있다.However, in the process of forming the vias for connecting the upper and lower conductive wirings, the photosensitive film pattern is defined on the interlayer insulating film formed to insulate the upper and lower conductive wirings between the upper and lower conductive wirings, that is, the via forming region is formed on the interlayer insulating film. After the pattern is formed, an interlayer insulating layer is etched using a mask to form vias connecting upper and lower conductive wirings.
그러나, 상기 종래 기술에 의한 비아 형성방법에 따르면, 상기 감광막 패턴 형성 시, 감광막 패턴이 상하의 도전배선 크기와 어긋나게 오정렬되어 형성되어, 이를 식각마스크로 비아 형성을 위한 식각공정 시, 하부의 도전배선이 미세화되어 하부 도전배선의 크기와 일치되지 않게 식각되어, 상하 도전배선이 어긋나게 연결되어 반도체소자의 불량이 발생하는 문제가 있다.However, according to the via forming method according to the prior art, when the photoresist pattern is formed, the photoresist pattern is misaligned with the size of the upper and lower conductive wirings, and when the etching process is performed for forming vias with an etching mask, There is a problem of miniaturization and etching so as to be inconsistent with the size of the lower conductive wiring, so that the upper and lower conductive wiring are connected to each other and the defect of the semiconductor device occurs.
이하, 첨부된 도면을 참고로 하여 금소배선의 마진 부족 현상에 대한 문제점을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the problem of the margin shortage phenomenon of gold wire.
도 1은 종래의 반도체소자의 금속배선 형성방법에 의해 형성된 금속배선의 문제점을 설명하기 위해 나타낸 공정 단면도이다.1 is a cross-sectional view illustrating a problem of metal wiring formed by a metal wiring forming method of a conventional semiconductor device.
종래 기술에 의한 금속배선 형성방법에 따르면, 우선, 도 1에 도시된 바와 같이, 실리콘기판(1) 상에 상·하부간에 전기적으로 전도선의 역할을 하는 금속배선(3,11)이 다층으로 형성되는 경우에 그 사이를 층간절연막(7)에 의해 절연시키고 있으며, 그 층간절연막(7)에 비아(9) 형성 영역을 정의하는 감광막 패턴(미도시함)을 형성하여 그 부위를 식각하여 층간절연막(7) 내에 상·하부 금속배선(3,11)이 서로 연결되도록 비아(9)를 형성한다.According to the metal wire forming method according to the prior art, first, as shown in FIG. 1, metal wires 3 and 11, which serve as conductive wires between the upper and lower parts on the silicon substrate 1, are formed in multiple layers. In this case, the interlayer insulating film 7 is insulated therebetween, and a photosensitive film pattern (not shown) defining a region for forming the vias 9 is formed in the interlayer insulating film 7 and the portions are etched to etch the interlayer insulating film. The vias 9 are formed in the 7 so that the upper and lower metal wirings 3 and 11 are connected to each other.
그러나, 상기 종래 기술에 의하면, 반도체소자가 점차적으로 고집적화 됨에 따라 반도체 기판 상의 금속 배선이 미세화되어 상기 상·하부 금속 배선을 연결하기 위한 비아 형성 시에 감광막 패턴 즉, 마스크 오정렬로 인하여 "A"와 같이, 상부 금속배선과 하부 금속배선이 연결되지 않아 소자의 불량이 발생되는 문제점이 있었다.However, according to the prior art, as the semiconductor devices are gradually integrated, the metal wirings on the semiconductor substrate become finer, so that when the vias are formed to connect the upper and lower metal wirings, the photoresist pattern, i.e., the mask misalignment, is used. Likewise, there is a problem in that a defect of the device occurs because the upper metal wiring and the lower metal wiring are not connected.
그 결과, 반도체소자의 공정 수율 및 소자동작의 신뢰성이 저하되는 문제점이 있었다.As a result, there is a problem that the process yield and the reliability of device operation of the semiconductor device are lowered.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의목적은 금속 배선 형성공정에 있어서, 금속 배선의 상부 양 측벽에 금속배선 형성물질과 같은 물질로 이루어진 스페이서에 의해 금속 배선의 상부 면적이 넓어져서, 후속 서로 다른 금속배선을 연결하기 위한 비아(via) 형성 시, 금속 배선에 대한 비아의 오버레이 마진을 확보할 수 있으며, 이에 따라, 비아를 형성하기 위한 마스크 오정렬에 따른 불량을 방지하도록 하는 반도체소자의 금속배선 형성방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form an upper portion of a metal wiring by spacers made of a material such as a metal wiring forming material on both sidewalls of the upper portion of the metal wiring. As the area is increased, overlay margins of vias with respect to the metal lines can be secured when vias are connected to subsequent metal lines, thereby preventing defects due to misalignment of masks to form vias. It is to provide a method for forming a metal wiring of a semiconductor device.
도 1은 종래의 반도체소자의 금속배선 형성방법에 의해 형성된 금속배선의 문제점을 설명하기 위해 나타낸 공정 단면도이다.1 is a cross-sectional view illustrating a problem of metal wiring formed by a metal wiring forming method of a conventional semiconductor device.
도 2a 내지 도 2f는 본 발명의 일 실시예에 따른 반도체소자의 금속배선 형성방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.2A through 2F are cross-sectional views sequentially illustrating a method of forming metal wirings of a semiconductor device according to an embodiment of the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 실리콘기판 110 : 제 1층간절연막100 silicon substrate 110 first interlayer insulating film
120 : 하부 금속 배선 135 : 스페이서120: lower metal wiring 135: spacer
140 : 제 2층간절연막 150 : 비아(via)140: second interlayer insulating film 150: via
상기 목적을 달성하기 위하여, 본 발명은 반도체소자 제조 공정에 있어서, 실리콘기판 상부에 형성된 제 1층간절연막 내에 하부 금속배선을 형성하는 단계와, 상기 제 1층간절연막의 상부 일부분을 다운 플로우 방식으로 선택적 식각하는 단계와, 상기 선택적 식각된 제 1층간절연막 상부에 금속물질을 증착하는 단계와, 상기 제 1층간절연막 상부가 노출되도록 금속물질을 블랭크 에치백하여 하부 금속배선 양측벽에 스페이서를 형성하는 단계를 포함하여 이루어진 특징으로 하는 반도체소자의 금속배선 형성방법을 제공한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, the method comprising: forming a lower metal wiring in a first interlayer insulating film formed on an upper surface of a silicon substrate; Etching, depositing a metal material on the selectively etched first interlayer insulating film, and blank-etching the metal material to expose the upper portion of the first interlayer insulating film to form spacers on both side walls of the lower metal wiring. It provides a method for forming metal wiring of a semiconductor device comprising a.
즉, 상기 본 발명에 의한 금속 배선 형성방법에 의하면, 상기 하부 금속배선의 상부 양 측벽에 금속배선 형성물질과 같은 물질로 이루어진 스페이서를 형성하여 금속 배선의 상부 면적을 넓힘으로써, 후속 서로 다른 금속 배선을 연결하기 위한 비아(via) 형성 시, 비아를 형성하기 위한 마스크 오정렬에 따른 금속배선의 오버레이 마진을 확보할 수 있게 되는 것이다.That is, according to the metal wiring forming method according to the present invention, by forming a spacer made of the same material as the metal wiring forming material on the upper sidewalls of the lower metal wiring to increase the upper area of the metal wiring, subsequent different metal wiring When vias are formed to connect the vias, overlay margins of the metal lines may be secured due to misalignment of the masks to form the vias.
상기 본 발명에 의한 금속배선 형성방법에 있어서, 상기 제 1층간절연막의 상부 일부분은 CxFy와 O2및 Ar 가스를 혼합한 혼합가스를 식각가스로 사용하여 다운 플로우 방식으로 선택적 식각하는 것이 바람직하다. 이러한 공정에 의하여, 금속배선의 상부 양측의 제 1층간절연막 일부분이 제거되어 금속배선 상부 일부분이 노출된다.In the metal wiring forming method according to the present invention, it is preferable that the upper portion of the first interlayer insulating film is selectively etched in a downflow manner using a mixed gas of CxFy, O 2 and Ar gas as an etching gas. By this process, a portion of the first interlayer insulating film on both sides of the upper portion of the metal wiring is removed to expose the upper portion of the metal wiring.
이하, 첨부한 도면을 참조하 여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따른 반도체소자의 제조방법을 순차적으로 나타낸 단면도이다.2A through 2F are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to the present invention.
우선, 도 2a에 도시된 바와 같이, 소정의 하부구조를 가지고 있는 반도체기판(100) 상에 제 1층간절연막(110)의 일부인 제 1산화막(112)을 PE-TEOS, BPSG, SOG, FSG, HDP 및 HLD 등의 산화물을 이용하여 증착하고 그 위해 감광막을 도포한 다음, 노광 및 현상공정을 진행하여 하부 금속배선 형성 영역이 정의되도록 감광막 패턴(미도시함)을 형성한다.First, as shown in FIG. 2A, the first oxide film 112, which is a part of the first interlayer insulating film 110, is formed on the semiconductor substrate 100 having a predetermined substructure, such as PE-TEOS, BPSG, SOG, FSG, and the like. Deposition is performed using oxides such as HDP and HLD, and a photoresist film is applied thereon, followed by an exposure and development process to form a photoresist pattern (not shown) to define a lower metal wiring formation region.
그리고, 상기 감광막 패턴(미도시함)을 식각마스크로 제 1산화막(112)을 선택적으로 식각하고, 결과물 전체에 Al, Cu 및 W 등과 같은 금속물질을 증착한 다음 에치백(etch back)하여 하부 금속 배선(120)을 형성한다.The first oxide layer 112 may be selectively etched using the photoresist pattern (not shown) as an etch mask, a metal material such as Al, Cu, and W is deposited on the entire resultant, and then etched back. The metal wiring 120 is formed.
그 다음, 상기 하부 금속 배선(120)이 형성된 결과물 전체에 제1층간절연막(110)의 일부인 제 2산화막(114)을 제 1산화막(112)과 동일한 산화물을 증착한 다음, 제 1산화막(112) 상부까지 화학기계적 연마 공정을 진행하여 결과물을 평탄화하여 제 1층간절연막(110)을 형성한다.Subsequently, a second oxide film 114 which is a part of the first interlayer insulating film 110 is deposited on the entire resultant material on which the lower metal wiring 120 is formed, and then the same oxide as the first oxide film 112 is deposited. A chemical mechanical polishing process is performed to the upper part to planarize the resultant to form the first interlayer insulating film 110.
이어서, 도 2b에 도시된 바와 같이, 상기 제 1층간절연막(110) 내에 형성된 하부 금속 배선(120)의 상부 양측벽의 제 1층간절연막(110)을 소정 부분 CxFy와 O2및 Ar 가스를 혼합한 혼합가스를 식각가스로 사용하여 다운 플로우(down flow) 방식으로 선택적 식각한다. 이때, 상기 제 1층간절연막(110)의 상부 소정부분이 식각되어 하부 금속 배선(120)의 상부 일부분이 노출된다.Subsequently, as shown in FIG. 2B, a predetermined portion CxFy, O 2, and Ar gas are mixed in the first interlayer insulating film 110 of both upper walls of the lower metal wiring 120 formed in the first interlayer insulating film 110. Selective etching is performed by using a mixed gas as an etching gas in a downflow manner. In this case, an upper predetermined portion of the first interlayer insulating layer 110 is etched to expose an upper portion of the lower metal wire 120.
그리고, 도 2c에 도시된 바와 같이, 상기 하부 금속 배선(120)의 상부 일부분이 노출된 결과물 전체에 하부 금속 배선(120) 형성물질과 동일한 금속물질(130)을 증착하여 노출된 하부 금속 배선(120)의 상부를 덮는다.As shown in FIG. 2C, the lower metal wiring exposed by depositing the same metal material 130 as the material forming the lower metal wiring 120 on the entire exposed portion of the lower metal wiring 120 is exposed. Cover top of 120).
이어서, 도 2d에 도시된 바와 같이, 상기 제 1층간절연막(110) 상부가 노출되도록 하부 금속 배선(120) 상부의 금속물질(130)을 블랭크 에치백(blank etch back)하여 하부 금속배선(120) 양측벽에 스페이서(135)를 형성한다. 이때, 상기 하부 금속 배선(120) 양측벽에 형성된 스페이서(135)는 하부 금속 배선(120)의 상부 넓이를 증가시켜 후속 공정에 의해 형성될 하부 금속 배선(120)에 대한 비아(미도시함)의 오버레이 마진을 확보한다.Subsequently, as illustrated in FIG. 2D, the metal material 130 on the lower metal wiring 120 is blank etched back so that the upper portion of the first interlayer insulating layer 110 is exposed, so that the lower metal wiring 120 The spacer 135 is formed on both side walls. In this case, the spacers 135 formed on both sidewalls of the lower metal wires 120 increase the upper width of the lower metal wires 120 to form vias for the lower metal wires 120 to be formed by a subsequent process (not shown). To secure the overlay margin.
그 다음, 도 2e에 도시된 바와 같이, 상기 스페이서(135)에 의해 하부 금속 배선(120)의 상부 넓이가 증가된 결과물 상에 후속 공정에 공정에 의해 형성될 상부 금속 배선(미도시함)과 절연하기 위해 PE-TEOS, BPSG, SOG 및 FSG 등의 산화물을 이용하여 제 2층간절연막(140)을 형성한다.Next, as shown in FIG. 2E, an upper metal wiring (not shown) to be formed by a process in a subsequent process on the resultant of which the upper width of the lower metal wiring 120 is increased by the spacer 135. In order to insulate, a second interlayer insulating layer 140 is formed using oxides such as PE-TEOS, BPSG, SOG, and FSG.
그리고, 도 2f에 도시된 바와 같이, 상기 제 2층간절연막(140) 상부에 상부 금속배선(미도시함)과 하부 금속 배선(120)을 연결시켜줄 비아(via) 형성을 위한 감광막 패턴(미도시함)을 형성하고 이를 마스크로 제 2층간절연막(140)을 선택적으로 식각하여 하부 금속 배선과 연결되는 비아(150)를 형성한다. 이때, "B"와 같이 마스크 정렬이 소정 부분 어긋나도 하부 금속 배선(120)의 상부 넓이가 스페이서(135)에 의해 증가되어 비아(150)와 하부 금속 배선(120)이 어긋나는 즉, 소자의 불량상태를 최소화 할 수 있다.As shown in FIG. 2F, a photoresist pattern (not shown) for forming a via to connect an upper metal wire (not shown) and a lower metal wire 120 to the second interlayer insulating layer 140 is illustrated. The second interlayer dielectric layer 140 is selectively etched using a mask to form vias 150 connected to the lower metal lines. At this time, even if the mask alignment is shifted by a predetermined portion, such as "B", the upper area of the lower metal interconnection 120 is increased by the spacer 135 so that the via 150 and the lower metal interconnection 120 are misaligned. The state can be minimized.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 금속배선 형성방법을 이용하게 되면, 금속배선의 상부 양 측벽에 금속 배선 형성물질과 같은 물질로 이루어진 스페이서를 형성하여 금속 배선의 상부 면적을 증가시킬 수 있게 된다.Therefore, as described above, when the metal wiring forming method of the semiconductor device according to the present invention is used, spacers made of the same material as the metal wiring forming material are formed on both upper sidewalls of the metal wiring to increase the upper area of the metal wiring. You can do it.
그 결과, 후속 서로 다른 금속 배선을 연결하기 위한 비아(via) 형성 시, 비아를 형성하기 위한 마스크 오정렬에 따른 금속배선의 오버레이 마진을 확보하게 되어, 마스크 오정렬에 따른 소자의 불량을 방지하여 공정 수율 및 소자동작의 신뢰성을 향상시키는 효과가 있다.As a result, when forming vias for connecting subsequent metal wirings, the overlay margin of the metal wirings according to the mask misalignment for forming the vias is secured, thereby preventing the defect of the device due to the mask misalignment, thereby increasing the process yield. And it is effective to improve the reliability of the device operation.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020070183A KR20040042060A (en) | 2002-11-12 | 2002-11-12 | Method for forming the metal line in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200452108Y1 (en) * | 2009-02-06 | 2011-02-01 | 주식회사 씨.월드 | The seat brake system which is established in the folding chair back of chair |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200452108Y1 (en) * | 2009-02-06 | 2011-02-01 | 주식회사 씨.월드 | The seat brake system which is established in the folding chair back of chair |
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