CN118280916A

CN118280916A - Semiconductor device and method of forming the same

Info

Publication number: CN118280916A
Application number: CN202211711040.8A
Authority: CN
Inventors: 吴轶超
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2024-07-02

Abstract

The invention provides a method for forming a semiconductor device, which comprises the following steps: providing a substrate to be processed; forming a first side wall on a substrate to be processed, wherein a graph projected onto the surface of the substrate to be processed by the first side wall is annular, the first side wall comprises a plurality of first parts which are parallel to each other, and the first parts are distributed along a first direction; forming a second side wall layer on the side wall surface and the top surface of the first part and the surface of the substrate to be processed, wherein a patterned layer with a pattern opening is formed on the surface of the second side wall layer, and the pattern opening exposes the second side wall layer on the top surface and the side wall surface of the first part; etching back the second side wall layer until the top surface of the first part is exposed, and forming a second side wall on the surface of the side wall of the first part; removing the first part after forming the second side wall; after the first part is removed, etching the substrate to be processed by taking the second side wall as a mask, and opening the opening in the substrate to be processed; to enhance the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device and a method for forming the same.

Background

Double-Patterning (DP) is gaining wide acceptance and application as a solution in the fabrication of semiconductor devices. Double-Patterning (DP) overcomes the K1 limitation by pitch chipping (pitch fragmentation) and is thus widely used in the fabrication of semiconductor devices. Currently, there are Self-aligned Double Patterning (SADP) techniques, litho-Etch-Litho-Etch (LELE) and Freeze-coat-Etch (LFL) techniques in Double-Patterning (DP) techniques.

As semiconductor fabrication technology has become more sophisticated, significant changes have also been made to integrated circuits, and the number of components integrated on the same chip has increased from the first tens, hundreds, to millions today. In order to meet the requirement of circuit density, the fabrication process of semiconductor integrated circuit chips forms various types of complex devices on a substrate by using a batch process technology and connects them to each other to have a complete electronic function, and at present, an ultra-low k interlayer dielectric layer is mostly used between wires as a dielectric material for isolating each metal interconnect, and an interconnection structure is used for providing wiring between devices on the IC chip and the entire package. In this technique, a device such as a Field Effect Transistor (FET) is first formed on a semiconductor substrate surface, and then an interconnect structure is formed in a back-end-of-line (BackEndofLine, BEOL) for integrated circuit fabrication, and a double patterning technique is widely used in forming the interconnect structure.

As predicted by moore's law, the ever shrinking dimensions of semiconductor substrates and the use of interconnect structures to connect transistors is a necessary option in order to increase the performance of devices where more transistors are formed on the semiconductor substrate. However, compared with the miniaturization and integration of components, the number of conductor wires in a circuit is continuously increased, the formation quality of an interconnection structure greatly affects the reliability of circuit connection, and the normal operation of a semiconductor device can be affected in severe cases.

Disclosure of Invention

The invention solves the problem of providing a semiconductor device and a forming method thereof so as to improve the performance of the semiconductor device.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising the steps of: providing a substrate to be processed; forming a first side wall on the substrate to be processed, wherein a graph projected onto the surface of the substrate to be processed by the first side wall is annular, the first side wall comprises a plurality of first parts which are parallel to each other, and the first parts are distributed along a first direction; forming a second side wall layer on the side wall surface and the top surface of the first part and the surface of the substrate to be processed, wherein a patterned layer with a pattern opening is formed on the surface of the second side wall layer, and the pattern opening exposes the second side wall layer on the top surface and the side wall surface of the first part; etching the second side wall layer until the top surface of the first part is exposed, and forming a second side wall on the side wall surface of the first part; removing the first part after forming the second side wall; and after the first part is removed, etching the substrate to be processed by taking the second side wall as a mask, and opening the opening in the substrate to be processed.

Optionally, the substrate to be processed includes: the device comprises a substrate, a dielectric layer positioned on the substrate and a sacrificial layer positioned on the dielectric layer.

Optionally, etching the substrate to be processed with the second side wall as a mask includes: etching the sacrificial layer, forming a sacrificial layer opening in the sacrificial layer, and exposing the surface of the dielectric layer at the bottom of the sacrificial layer opening; and continuing to etch the exposed dielectric layer along the sacrificial layer opening, and forming the opening in the dielectric layer.

Optionally, before continuing etching the exposed dielectric layer along the sacrificial layer opening, the method further includes: and etching the second side wall layer until the first side wall is exposed, and forming a mask side wall on the side wall surface of the first side wall.

Optionally, a conductive layer is formed within the opening.

Optionally, the material of the conductive layer is one or a combination of more than one of copper, aluminum, cobalt, tungsten and ruthenium.

Correspondingly, the invention also provides a method for forming the semiconductor device, which comprises the following steps: providing a substrate, wherein a dielectric layer and a sacrificial layer positioned on the dielectric layer are arranged on the substrate; forming a plurality of first side walls which are arranged in a separated mode on the sacrificial layer, wherein a graph projected onto the surface of the substrate by the first side walls is annular, the first side walls comprise a plurality of first parts which are parallel to each other, and the first parts are distributed along a first direction; forming a transition opening in the sacrificial layer, wherein the bottom surface of the transition opening exposes the surface of the dielectric layer; forming a second side wall on the side wall surface of the transition opening; removing the first part, and forming a second side wall opening exposing the surface of the sacrificial layer between the second side walls; and etching the dielectric layer at the bottom of the transition opening, the sacrificial layer at the bottom of the second side wall opening and the dielectric layer along the transition opening and the second side wall opening, and forming an opening in the dielectric layer.

Optionally, before forming the transition opening in the sacrificial layer, forming a first pattern layer on the sacrificial layer and on a portion of the first portion, the first pattern layer having a first pattern opening therein exposing a portion of the first portion and the sacrificial layer between the first portions.

Optionally, the step of forming a transition opening in the sacrificial layer includes: and etching the exposed sacrificial layer by taking the first pattern layer and the first part as masks, and forming the transition opening in the sacrificial layer.

Optionally, after forming the transition opening and before forming the second side wall, the method further includes: and removing the first graph layer.

Optionally, after forming the second side wall, before removing the first portion, the method further includes: and forming a second graph layer on the sacrificial layer and part of the second side wall, wherein a second graph opening is formed in the second graph layer, and the second graph opening exposes part of the first part and the second side wall on the side wall surface of the first part.

Optionally, a conductive layer is formed within the opening.

Correspondingly, the invention further provides a forming method of the semiconductor device, which comprises the following steps: providing a substrate, wherein a dielectric layer and a sacrificial layer are arranged on the substrate; forming a first side wall on the sacrificial layer, wherein the first side wall comprises a plurality of first parts which are parallel to each other, the first parts are distributed along a first direction, a second part connected with the first parts, the second parts are distributed along a second direction, and the first direction is perpendicular to the second direction; forming a second side wall on the side wall surface of the first part, wherein the second side wall comprises third parts which are distributed in parallel along the first direction; removing the first part to expose the surface of the sacrificial layer at the bottom of the first part; forming a pattern layer on the sacrificial layer and part of the third part, wherein the pattern layer is internally provided with a pattern opening, and the pattern opening exposes the third part; etching the sacrificial layer and the dielectric layer at the bottom of the sacrificial layer by using the pattern layer and the third part as masks to form an opening in the dielectric layer

Optionally, a conductive layer is formed within the opening.

Optionally, before forming the second sidewall on the sidewall surface of the first portion, the method further includes: forming a second graphic layer on the first portion, the second graphic layer covering the first portion; and removing the second part exposed by the second pattern layer until the surface of the sacrificial layer is exposed.

Optionally, the pattern layer and the second pattern layer adopt the same mask.

Compared with the prior art, the technical scheme of the invention has the following advantages:

In the technical scheme of the method, a first side wall is formed on the substrate to be processed, a graph projected onto the surface of the substrate to be processed by the first side wall is annular, the first side wall comprises a plurality of first parts which are parallel to each other, and the first parts are distributed along a first direction; forming a second side wall layer on the side wall surface and the top surface of the first part and the surface of the substrate to be processed; forming a patterned layer with a pattern opening on the surface of the second side wall layer, wherein the pattern opening exposes the top surface of the first part and the second side wall layer on the surface of the side wall; after the patterned layer is formed, etching back the second side wall layer until the top surface of the first part is exposed, and forming a second side wall on the surface of the side wall of the first part; removing the first part after forming the second side wall; after the first portion is removed, the second side wall is used as a mask to etch the substrate to be processed, and an opening is formed in the substrate to be processed, wherein the pattern opening of the patterning layer only exposes the surface of the first portion, and the second side wall layer on the side wall of the first portion only can be arranged along the direction parallel to the first portion, so that the first portion is removed, and when the second side wall is used as the mask to etch the substrate to be processed, the opening formed in the substrate to be processed only can be arranged along the first direction, so that the conductive layer finally formed in the opening can only be distributed along the first direction in parallel, the problem of end connection of the conductive layer is solved, the occurrence of circuit short circuit is avoided, and the electrical property of a semiconductor device is effectively improved.

Drawings

Fig. 1 to 5 are schematic views showing a structure of a forming process of a semiconductor device;

fig. 6 to 18 are schematic views showing a structure of a forming process of a semiconductor device in the first embodiment of the present invention;

Fig. 19 to 30 are schematic views showing a structure of a forming process of a semiconductor device in a second embodiment of the present invention;

fig. 31 to 42 are schematic views showing a structure of a forming process of a semiconductor device in a third embodiment of the present invention.

Detailed Description

As described in the background art, the quality of the semiconductor device formed with the metal line is poor, which affects the use of the semiconductor device to some extent, and the specific forming process is shown in fig. 1 to 5.

Referring to fig. 1-2, fig. 2 is a cross-sectional view of fig. 1 at A-A. A substrate 100 is provided, wherein the substrate 100 is provided with a dielectric layer 101 and a sacrificial layer 102 positioned on the dielectric layer 101, a plurality of core layers 103 which are arranged in a discrete manner are formed on the sacrificial layer 102, and a first side wall 104 is formed on the side wall of the core layer 103.

Referring to fig. 3, the view direction of fig. 3 is identical to the view direction of fig. 2, the core layer 103 is removed, the sacrificial layer 102 is etched by using the first sidewall 104 as a mask, a first opening 105 is formed in the sacrificial layer 102, the bottom of the first opening 105 exposes the surface of the dielectric layer 101, and a second sidewall 106 is formed on the sidewall of the first opening 105.

Referring to fig. 4 and fig. 5, fig. 4 is a cross-sectional view of fig. 5 A-A, the etched sacrificial layer 102 is removed, the dielectric layer 101 is etched by the second sidewall 106, a second opening is formed in the dielectric layer 101, and a conductive layer 107 is formed in the second opening.

However, referring to fig. 5, after the conductive layer 107 is formed, the conductive layer 107 is connected at the end (the dotted line in the figure) of the conductive layer 107, which causes a short circuit, and thus causes failure of the semiconductor device, and degrades the performance of the semiconductor device.

On the basis, the invention provides a method for forming a semiconductor device.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

First embodiment

Fig. 6 to 18 are schematic views showing a structure of a forming process of a semiconductor device in the first embodiment of the present invention.

First, referring to fig. 6, a substrate to be processed is provided.

In this embodiment, the substrate to be processed includes: a substrate 200, a dielectric layer 201 on the substrate 200, and a sacrificial layer 202 on the dielectric layer 201.

In this embodiment, the material of the dielectric layer 201 is silicon nitride.

In other embodiments, the material of the dielectric layer 201 may be one or a combination of silicon oxide and silicon nitride.

In this embodiment, the material of the sacrificial layer 202 is silicon oxide.

In other embodiments, the material of the sacrificial layer 202 may also be one or more of silicon oxide, amorphous silicon, and silicon nitride.

Referring to fig. 7 and 8, a core layer 203 is formed on the sacrificial layer 202.

Fig. 7 is a top view of fig. 8, and fig. 8 is a cross-sectional view of fig. 7 at A-A.

The core layer 203 is a plurality of core layers 203 and the plurality of core layers 203 are separately arranged on the sacrificial layer 202.

Fig. 7 shows only two of the core layers 203.

Referring to fig. 9, a first sidewall 204 is formed on the sacrificial layer 202.

The view direction of fig. 9 coincides with the view direction of fig. 7.

The first side wall 204 is formed on a side wall surface of the core layer 203.

In this embodiment, the step of forming the first sidewall 204 includes: forming an initial first film layer (not shown) on the sidewalls and top surface of the core layer 203; the initial first film layer is etched back to form the first sidewall 204 on the sidewall of the core layer 203.

In this embodiment, the process of forming the initial first film layer is a chemical vapor deposition process.

In other embodiments, the process of forming the initial first film layer may also be one or more combinations of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.

In this embodiment, the material of the first sidewall 204 is titanium nitride.

In other embodiments, the material of the first sidewall 204 may be one or a combination of titanium nitride and titanium oxide.

Referring to fig. 10, the core layer 203 is removed, the surface of the sacrificial layer 202 at the bottom of the core layer 203 is exposed, and a first sidewall 204 is formed on the substrate to be processed.

The view direction of fig. 10 coincides with the view direction of fig. 9.

In this embodiment, the first sidewall 204 has a ring shape projected onto the surface of the substrate to be processed, and the first sidewall 204 includes a plurality of first portions 204a parallel to each other, and the plurality of first portions 204a are arranged along a first direction.

In this embodiment, the first side wall 204 further includes a plurality of second portions 204b parallel to each other, the first portions 204a are connected end to end with the second portions 204b, the second portions 204b are distributed perpendicular to the first portions 204a, the second portions 204b are distributed along a second direction, and the first direction is perpendicular to the second direction.

In this embodiment, the first direction is set as the X direction, and the second direction is set as the Y direction.

Referring to fig. 11, a second sidewall layer 205 is formed on the sidewall surface and the top surface of the first portion 204a and the surface of the substrate to be processed, and a patterned layer 206 having a pattern opening 207 is formed on the surface of the second sidewall layer 205, where the pattern opening 207 exposes the second sidewall layer 205 on the top surface and the sidewall surface of the first portion 204 a.

In this embodiment, the material of the second sidewall layer 205 is titanium oxide.

In other embodiments, the material of the second sidewall layer 205 may be titanium oxide or titanium nitride or a combination thereof

Referring to fig. 12, the second sidewall layer 205 is etched back until the top surface of the first portion 204a is exposed, and a second sidewall 208 is formed on the sidewall surface of the first portion 204 a.

In this embodiment, the surface of the sacrificial layer 202 between the adjacent second side walls 208 is also exposed.

Referring to fig. 13, the patterned layer 206 is removed.

In this embodiment, the process of removing the patterned layer 206 is an ashing process.

In other embodiments, the process of removing the patterned layer 206 may also be a wet etching process or a dry etching process.

Referring to fig. 14, the first portion 204a is removed.

In this embodiment, after the first portion 204a is removed, the surface of the sacrificial layer 202 at the bottom of the first portion 204a is exposed.

After the first portion is removed, the substrate to be processed is etched by using the second sidewall as a mask, and an opening is formed in the substrate to be processed, see fig. 15 to 17.

Referring to fig. 15, the sacrificial layer 202 is etched, a sacrificial layer opening 209 is formed in the sacrificial layer 202, and the bottom of the sacrificial layer opening 209 exposes the surface of the dielectric layer 201.

In this embodiment, the ratio of the etching rate of the sacrificial layer 202 to the etching rate of the second sidewall layer 205 is greater than 100.

In other embodiments, the ratio of the etching rate of the sacrificial layer 202 to the etching rate of the second sidewall layer 205 may be less than 100; however, when the ratio of the etching rate of the sacrificial layer 202 to the etching rate of the second sidewall layer 205 is less than 50, the second sidewall layer 205 may be consumed earlier than the sacrificial layer 202, so that the sacrificial layer opening 209 cannot be defined.

In this embodiment, the etching selection ratio of the sacrificial layer 202 to the second sidewall layer 205 is reasonably selected, so that the shape of the second sidewall layer 205 is not damaged in the process of etching the sacrificial layer 202, and the subsequent pattern is accurately transferred to form a pad, thereby being beneficial to forming a semiconductor device with high quality.

Referring to fig. 16, the second sidewall layer 205 is etched back until the first sidewall 204 is exposed, and a mask sidewall 210 is formed on the sidewall surface of the first sidewall 204.

In this embodiment, a mask sidewall 210 is formed on a sidewall surface of the second portion 204 b.

Referring to fig. 17, etching is continued along the sacrificial layer opening 209 to expose the dielectric layer 201, and the opening 211 is formed in the dielectric layer 201.

In this embodiment, the dielectric layer 201 is etched with the sacrificial layer 202, the mask sidewall 210 and the first sidewall 204 as masks, and the opening 211 is formed in the dielectric layer 201.

In this embodiment, in the process of forming the opening 211, by reasonably selecting the etching rates of the sacrificial layer 202, the mask sidewall 210, the first sidewall 204 and the dielectric layer 201, the sacrificial layer 202, the mask sidewall 210 and the first sidewall 204 (i.e. the second portion 204 b) are consumed simultaneously in the process of forming the opening 211, and the etching process can just stop on the surface of the dielectric layer 201; meanwhile, the sacrificial layer 202, the mask side wall 210 and the first side wall 204 (i.e. the second portion 204 b) can be consumed without an additional etching process, so that the mask is reduced, the production efficiency is improved, the production period is shortened, and the application range is wider.

In this embodiment, the openings 211 can only be distributed in parallel along the first direction (X) within the dielectric layer 201 under the intervention of the patterned layer 206.

Referring to fig. 18, a conductive layer 212 is formed in the opening 211.

In this embodiment, the material of the conductive layer 212 is copper.

In other embodiments, the material of the conductive layer 212 may also be one or more of copper, aluminum, cobalt, tungsten, and ruthenium.

In this embodiment, the step of forming the conductive layer 212 includes: forming an initial conductive layer (not shown) in the fourth opening 211 and on the dielectric layer 201; the initial conductive layer is planarized to expose the surface of the dielectric layer 201, and the conductive layer 212 is formed within the dielectric layer 201.

In this embodiment, the process of forming the initial conductive layer is an electroless plating process.

In other embodiments, the process of forming the initial conductive layer includes one or more combinations of an electroless plating process, a chemical vapor deposition process, and an atomic layer deposition process.

In this embodiment, since the patterned opening 207 of the patterned layer 206 only exposes the surface of the first portion 204a, the second sidewall layer 208 on the sidewall of the first portion 204a can only be arranged along a direction parallel to the first portion 204a, so that the first portion 204a is removed, and when the substrate to be processed is etched with the second sidewall 208 as a mask, the opening 211 formed in the substrate to be processed can only be arranged along the first direction, so that the conductive layer 212 finally formed in the opening 211 can only be distributed in parallel along the first direction, thereby eliminating the problem of end connection of the conductive layer 212, avoiding the occurrence of circuit short-circuits, and effectively improving the electrical performance of the semiconductor device.

Second embodiment

Fig. 19 to 30 are schematic views showing a structure of a forming process of a semiconductor device in a second embodiment of the present invention.

First, referring to fig. 19, a substrate 300 is provided, and the substrate 300 has a dielectric layer 301 and a sacrificial layer 302 thereon.

Referring to fig. 20 and 21, a core layer 303 is formed on the sacrificial layer 302.

Fig. 20 is a top view of fig. 21, and fig. 21 is a cross-sectional view of fig. 20 at A-A.

The core layer 303 is a plurality of core layers 303 and the plurality of core layers 303 are separately arranged on the sacrificial layer 302.

Fig. 20 shows only two of the core layers 303.

Referring to fig. 22, a first sidewall 304 is formed on the sacrificial layer 302.

The view direction of fig. 22 coincides with the view direction of fig. 20.

The first sidewall 304 is formed on a sidewall surface of the core 303.

In this embodiment, the step of forming the first sidewall 304 includes: forming an initial first film layer (not shown) on the sidewalls and top surface of the core layer 303; the initial first film layer is etched back, and the first sidewall 304 is formed on the sidewall of the core layer 303.

In this embodiment, the material of the first sidewall 304 is titanium nitride.

In other embodiments, the material of the first sidewall 304 may be one or a combination of two of titanium nitride and titanium oxide.

Referring to fig. 23, the core layer 303 is removed, the surface of the sacrificial layer 302 at the bottom of the core layer 303 is exposed, and a first sidewall 304 is formed on the sacrificial layer 302.

The view direction of fig. 23 coincides with the view direction of fig. 22.

In this embodiment, the first sidewall 304 is projected to the surface of the substrate to be processed in a ring shape, the first sidewall 304 includes a plurality of first portions 304a parallel to each other, and the plurality of first portions 304a are arranged along a first direction.

In this embodiment, the first side wall 304 further includes a plurality of second portions 304b parallel to each other, the first portions 304a are connected end to end with the second portions 304b, the second portions 304b are distributed perpendicular to the first portions 304a, the second portions 304b are distributed along a second direction, and the first direction is perpendicular to the second direction.

In the present embodiment, the first direction is set as the X direction, the second direction is set as the Y direction, and in the present embodiment, the length dimension of the first portion 304a in the first direction is L.

Referring to fig. 24, a first pattern layer 305 is formed on the sacrificial layer 302 and a portion of the first portion 304a, wherein the first pattern layer 305 has a first pattern opening 306 therein, and the first pattern opening 306 exposes a portion of the first portion 304a and the sacrificial layer 302 between the first portions 304 a.

In the present embodiment, the width dimension of the first pattern opening 306 in the first direction (X) is D.

Referring to fig. 23 and 24, in the first direction (X), the width dimension (D) of the first pattern opening 306 is 20 to 40 angstroms larger than the length dimension (L) of the first portion 304 a; when the difference between the width dimension (D) of the first pattern opening 306 and the length dimension (L) of the first portion 304a is smaller than 20 angstroms, the dimension of the first pattern opening 306 is smaller, resulting in that the conductive layer finally formed in the dielectric layer is too short to meet the practical process requirement; when the difference between the width dimension (D) of the first pattern opening 306 and the length dimension (L) of the first portion 304a is greater than 40 angstroms, the first pattern opening 306 is larger in size, so that the second portion 304b is also exposed, thereby causing the ends of the conductive layer finally formed in the dielectric layer to be still connected together, resulting in occurrence of a short circuit.

In this embodiment, after the core layer 303 is removed, the first pattern layer 305 is formed on the sacrificial layer 302 and a portion of the first side wall 304, where the first pattern layer 305 has the first pattern opening 306 therein, the first pattern opening 306 exposes the first portion 304a and the sacrificial layer 302 between the first portions 304a, and the first pattern layer 305 is utilized to expose only the first portion 304a of the first side wall 304 arranged along the first direction, so as to prepare for forming a conductive layer in the dielectric layer 301 corresponding to the bottom of the first portion 304a only later, thereby solving the problem of end connection of the conductive layer.

Referring to fig. 25, the exposed sacrificial layer 302 is etched by using the first pattern layer 305 and the first portion 304a as masks, and a transition opening 307 is formed in the sacrificial layer 302, where the transition opening 307 and the first portion 304a are arranged along a first direction.

In this embodiment, the transition opening 307 exposes a surface of the dielectric layer 301 at the bottom.

Referring to fig. 26, a second sidewall 308 is formed on a sidewall surface of the transition opening 307.

In this embodiment, after forming the transition opening 307, before forming the second sidewall 308, the method further includes: the first graphics layer 305 is removed.

Referring to fig. 27, a second pattern layer 309 is formed on the sacrificial layer 302 and a portion of the second sidewall 308, where the second pattern layer 309 has a second pattern opening 310 therein, and the second pattern opening 310 exposes a portion of the first portion 304a and the second sidewall 308 on a sidewall surface of the first portion 304 a.

Referring to fig. 23 and 27 in combination, in the first direction, the length dimension (d) of the second pattern opening 310 is 40 to 200 angstroms greater than the length dimension (L) of the first portion 304 a; when the difference between the length dimension (d) of the second pattern opening 310 and the length dimension (L) of the first portion 304a is smaller than 40 angstroms, the dimension of the second pattern opening 310 is smaller, resulting in that the conductive layer finally formed in the dielectric layer is too short to meet the practical process requirements; when the length dimension (d) of the second pattern opening 310 is greater than 40 a by more than 200a than the length dimension (L) of the first portion 304a, the second pattern opening 310 is larger in size, such that the second sidewall 308 of the second portion 304b is also exposed, thereby causing the ends of the conductive layers finally formed in the dielectric layer to be still connected together, resulting in occurrence of a short circuit.

In this embodiment, the second pattern opening 310 simultaneously exposes the surface of the dielectric layer 301 between the second sidewalls 308.

Referring to fig. 28, the first portion 304a is removed, and a second sidewall opening 311 exposing the surface of the sacrificial layer 302 is formed between the second sidewalls 308.

Referring to fig. 29, along the transition opening 307 and the second sidewall opening 311, the dielectric layer 301 at the bottom of the transition opening 307 and the sacrificial layer 302 and the dielectric layer 301 at the bottom of the second sidewall opening 311 are etched, so that an opening 312 is formed in the dielectric layer 301.

In this embodiment, under the mutual intervention of the first pattern layer 305 and the second pattern layer 309, the opening 312 can only be formed in the dielectric layer 301 between the dielectric layer 301 at the bottom of the first portion 304a and the second sidewall 308, and since the first portion 304a is parallel distributed along the first direction and the dielectric layer 301 between the second sidewalls 308 is isolated by the second sidewall 308, during the process of etching the dielectric layer 301 to form the opening 312, the opening 312 in the dielectric layer 301 at the bottom of the first portion 304a cannot form a connection with the opening 312 in the dielectric layer 301 between the second sidewalls 308, and thus, when a conductive layer is formed in the opening 312, the conductive layer cannot form a connection, so that the problem of end connection of the conductive layer is eliminated, the occurrence of circuit short circuit is avoided, and the electrical performance of the semiconductor device is effectively improved.

In this embodiment, in the process of forming the opening 312, the sacrificial layer 302 exposed by the second sidewall opening 311 is etched first until the surface of the dielectric layer 301 is exposed; the second graphics layer 309 is then removed; and continuing to etch the exposed dielectric layer 301 by using the second sidewall 308 and the sacrificial layer 302 as masks, forming the opening 312 in the dielectric layer 301, and consuming the second sidewall 308 and the sacrificial layer 302 to the surface of the dielectric layer 301 exposed from the bottom.

Referring to fig. 30, a conductive layer 313 is formed in the opening 312.

In this embodiment, the material of the conductive layer 313 is copper.

In other embodiments, the material of the conductive layer 313 may also be one or more of copper, aluminum, cobalt, tungsten, and ruthenium.

In this embodiment, the step of forming the conductive layer 313 includes: forming an initial conductive layer (not shown) within the opening 312 and over the dielectric layer 301; the initial conductive layer is planarized until the surface of the dielectric layer 301 is exposed, and the conductive layer 313 is formed within the dielectric layer 301.

Third embodiment

Referring first to fig. 31, a substrate 400 is provided, and the substrate 400 has a dielectric layer 401 and a sacrificial layer 402 on the dielectric layer 401.

Referring to fig. 32 and 33, a core layer 403 is formed on the sacrificial layer 402.

Fig. 32 is a top view of fig. 33, and fig. 33 is a cross-sectional view of fig. 32 at A-A.

The core layer 403 is a plurality and the plurality of core layers 403 are separately arranged on the sacrificial layer 402.

Fig. 33 shows only two of the core layers 403.

Referring to fig. 34, a first sidewall 404 is formed on the sacrificial layer 402.

The view direction of fig. 34 coincides with the view direction of fig. 32.

The first sidewall 404 is formed on a sidewall surface of the core layer 403.

In this embodiment, the step of forming the first sidewall 404 includes: forming an initial first film layer (not shown) on the sidewalls and top surface of the core layer 403; the initial first film layer is etched back to form the first sidewall 404 on the sidewall of the core layer 403.

In this embodiment, the material of the first sidewall 404 is titanium nitride.

In other embodiments, the material of the first sidewall 404 may be one or a combination of titanium nitride and titanium oxide.

Referring to fig. 35, the core layer 403 is removed, the surface of the sacrificial layer 402 at the bottom of the core layer 403 is exposed, and a first sidewall 404 is formed on the sacrificial layer 402.

In this embodiment, the first side wall 404 includes a plurality of first portions 404a parallel to each other, and the plurality of first portions 404a are distributed along a first direction, and the plurality of second portions 404b connected to the first portions 404a are distributed along a second direction, where the first direction is perpendicular to the second direction.

In this embodiment, the first direction is perpendicular to the second direction.

In other embodiments, the first direction and the second direction may be disposed non-perpendicularly and non-parallel.

In the present embodiment, in the first direction, the length dimension of the first portion 404a is L.

Referring to fig. 36, a second pattern layer 405 is formed on the first portion 404a, and the second pattern layer 405 covers the first portion 404a.

In this embodiment, in the first direction, the width dimension of the second graphic layer 405 is D.

In the present embodiment, the width dimension (D) of the second pattern layer 405 is 40 to 200 angstroms larger than the length dimension (L) of the first portion 404a in the first direction; the difference between the width dimension (D) of the second pattern layer 405 and the length dimension (L) of the first portion 404a is less than 40 angstroms, and at this time, the width dimension (D) of the second pattern layer 405 is smaller, so that the conductive layer finally formed in the dielectric layer is too short to meet the practical process requirements; the difference between the width dimension (D) of the second patterned layer 405 and the length dimension (L) of the first portion 404a is greater than 200 angstroms so that the second portion 304b also covers in, resulting in the ends of the conductive layers eventually formed within the dielectric layer being still connected together, resulting in the occurrence of a short circuit.

Referring to fig. 37, the second portion 404b of the second pattern layer 405 is removed until the surface of the sacrificial layer 402 is exposed.

In this embodiment, the second portion 404b is removed by the intervention of the second graphics layer 405, thereby avoiding graphics transfer along the second portion 404 b.

Referring to fig. 38, a second sidewall 406 is formed on a sidewall surface of the first portion 404a, and the second sidewall 406 includes third portions 406a that are parallel distributed along the first direction.

In this embodiment, the second side wall 406 further includes a fourth portion 406b connected to the third portion 406 a.

In this embodiment, the second pattern layer 405 is removed before the second sidewall 406 is formed.

Referring to fig. 39, the first portion 404a is removed, and the surface of the sacrificial layer 402 at the bottom of the first portion 404a is exposed.

Referring to fig. 40, a pattern layer 407 is formed on the sacrificial layer 402 and a portion of the third portion 406a, the pattern layer 407 has a pattern opening 408 therein, and the pattern opening 408 exposes the third portion 406a.

The pattern layer 406 and the second pattern layer 404 use the same mask.

In this embodiment, the exposed sacrificial layer 402 is removed by first etching through the patterned layer 407, and a portion of the exposed sacrificial layer 402 is exposed after the first portion 404a is removed, and a portion of the sacrificial layer is between the third portions 406 a; and there is no connection between the exposed sacrificial layers 402, so that there is no connection between the openings when the openings are formed in the dielectric layer 401 during the pattern transfer.

Referring to fig. 41, the sacrificial layer 402 and the dielectric layer 401 at the bottom of the sacrificial layer 402 are etched by using the pattern layer 407 and the third portion 407a as masks, and an opening 409 is formed in the dielectric layer 401.

In this embodiment, the openings 409 are formed to be distributed in parallel along the first direction in the dielectric layer 401.

In this embodiment, during the process of etching the dielectric layer 401 to form the opening 409, the sacrificial layer 402 and the second sidewall 406 are both consumed at the same time.

In this embodiment, the ratio of the etching rate of the dielectric layer 401 to the etching rate of the sacrificial layer 402 is greater than 100.

In other embodiments, the pattern cannot be transferred effectively when the ratio of the etching rate of the dielectric layer 401 to the etching rate of the sacrificial layer 402 is less than 20.

In this embodiment, the ratio of the etching rate of the dielectric layer 401 to the etching rate of the second sidewall 406 is greater than 100.

In other embodiments, the ratio of the etching rate of the dielectric layer 401 to the etching rate of the second sidewall 406 is less than 100, and when the ratio of the etching rate of the dielectric layer 401 to the etching rate of the second sidewall 406 is less than 50, the pattern cannot be effectively transferred.

In this embodiment, by reasonably controlling the etching rate relationship among the dielectric layer 401, the sacrificial layer 402 and the second side wall 406, the morphology of the second side wall 406 is not damaged in the process of removing the sacrificial layer 402; meanwhile, in the process of removing and etching the dielectric layer 401 to form the opening 409, the sacrificial layer 402 and the second side wall 406 can be consumed in the process of forming the opening 409 without an additional etching process, so that the use of a mask is reduced, the production efficiency is improved, the production period is shortened, and the method has a wider application range.

Referring to fig. 42, a conductive layer 410 is formed in the opening 409.

In this embodiment, the method of forming the conductive layer 410 includes: forming an initial conductive layer (not shown) within the opening 409 and over the dielectric layer 401; the initial conductive layer is planarized until the surface of the dielectric layer 401 is exposed, and the conductive layer 410 is formed within the dielectric layer 401.

In this embodiment, the material of the conductive layer 410 is copper.

In other embodiments, the material of the conductive layer 410 may also be one or more of copper, aluminum, cobalt, tungsten, and ruthenium.

In this embodiment, the intervention of the pattern layer 406 and the second pattern layer 404 makes the opening 409 formed in the dielectric layer 401 only distribute along the first direction after the pattern is continuously transferred, so as to ensure that the conductive layer 410 finally formed in the opening 409 can only distribute in parallel along the first direction in the dielectric layer 401, thereby eliminating the problem of end connection of the conductive layer 410, avoiding the occurrence of short circuit, and effectively improving the electrical performance of the semiconductor device.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of forming a semiconductor device, comprising the steps of:

providing a substrate to be processed;

Forming a first side wall on the substrate to be processed, wherein a graph projected onto the surface of the substrate to be processed by the first side wall is annular, the first side wall comprises a plurality of first parts which are parallel to each other, and the first parts are distributed along a first direction;

Forming a second side wall layer on the side wall surface and the top surface of the first part and the surface of the substrate to be processed, wherein a patterned layer with a pattern opening is formed on the surface of the second side wall layer, and the pattern opening exposes the second side wall layer on the top surface and the side wall surface of the first part;

Etching the second side wall layer until the top surface of the first part is exposed, and forming a second side wall on the side wall surface of the first part;

Removing the first part after forming the second side wall;

and after the first part is removed, etching the substrate to be processed by taking the second side wall as a mask, and opening the opening in the substrate to be processed.

2. The method of forming a semiconductor device according to claim 1, wherein the substrate to be processed comprises: the device comprises a substrate, a dielectric layer positioned on the substrate and a sacrificial layer positioned on the dielectric layer.

3. The method for forming a semiconductor device according to claim 2, wherein etching the substrate to be processed with the second sidewall as a mask comprises: etching the sacrificial layer, forming a sacrificial layer opening in the sacrificial layer, and exposing the surface of the dielectric layer at the bottom of the sacrificial layer opening; and continuing to etch the exposed dielectric layer along the sacrificial layer opening, and forming the opening in the dielectric layer.

4. The method of forming a semiconductor device of claim 3, further comprising, prior to continuing etching the exposed dielectric layer along the sacrificial layer opening: and etching the second side wall layer until the first side wall is exposed, and forming a mask side wall on the side wall surface of the first side wall.

5. The method of forming a semiconductor device according to claim 1, wherein a conductive layer is formed in the opening.

6. The method of forming a semiconductor device according to claim 5, wherein the conductive layer is made of one or more of copper, aluminum, cobalt, tungsten, and ruthenium.

7. A method of forming a semiconductor device, comprising the steps of:

Providing a substrate, wherein a dielectric layer and a sacrificial layer positioned on the dielectric layer are arranged on the substrate;

Forming a plurality of first side walls which are arranged in a separated mode on the sacrificial layer, wherein a graph projected onto the surface of the substrate by the first side walls is annular, the first side walls comprise a plurality of first parts which are parallel to each other, and the first parts are distributed along a first direction;

forming a transition opening in the sacrificial layer, wherein the bottom surface of the transition opening exposes the surface of the dielectric layer;

forming a second side wall on the side wall surface of the transition opening;

removing the first part, and forming a second side wall opening exposing the surface of the sacrificial layer between the second side walls;

and etching the dielectric layer at the bottom of the transition opening, the sacrificial layer at the bottom of the second side wall opening and the dielectric layer along the transition opening and the second side wall opening, and forming an opening in the dielectric layer.

8. The method of forming a semiconductor device of claim 7, further comprising forming a first pattern layer over the sacrificial layer and over a portion of the first portion, the first pattern layer having a first pattern opening therein exposing a portion of the first portion and the sacrificial layer therebetween, prior to forming a transition opening in the sacrificial layer.

9. The method of forming a semiconductor device of claim 8, wherein forming a transition opening in the sacrificial layer comprises: and etching the exposed sacrificial layer by taking the first pattern layer and the first part as masks, and forming the transition opening in the sacrificial layer.

10. The method of forming a semiconductor device of claim 8, further comprising, after forming the transition opening, prior to forming the second sidewall: and removing the first graph layer.

11. The method of forming a semiconductor device of claim 10, further comprising, after forming the second sidewall, before removing the first portion: and forming a second graph layer on the sacrificial layer and part of the second side wall, wherein a second graph opening is formed in the second graph layer, and the second graph opening exposes part of the first part and the second side wall on the side wall surface of the first part.

12. The method of forming a semiconductor device according to claim 7, wherein a conductive layer is formed in the opening.

13. A method of forming a semiconductor device, comprising the steps of:

Providing a substrate, wherein a dielectric layer and a sacrificial layer are arranged on the substrate;

forming a first side wall on the sacrificial layer, wherein the first side wall comprises a plurality of first parts which are parallel to each other, the first parts are distributed along a first direction, a second part connected with the first parts, the second parts are distributed along a second direction, and the first direction is perpendicular to the second direction;

Forming a second side wall on the side wall surface of the first part, wherein the second side wall comprises third parts which are distributed in parallel along the first direction;

Removing the first part to expose the surface of the sacrificial layer at the bottom of the first part;

Forming a pattern layer on the sacrificial layer and part of the third part, wherein the pattern layer is internally provided with a pattern opening, and the pattern opening exposes the third part;

And etching the sacrificial layer and the dielectric layer at the bottom of the sacrificial layer by taking the pattern layer and the third part as masks, and forming an opening in the dielectric layer.

14. The method of forming a semiconductor device according to claim 13, wherein a conductive layer is formed in the opening.

15. The method of forming a semiconductor device of claim 14, further comprising, prior to forming a second sidewall on a sidewall surface of the first portion:

Forming a second graphic layer on the first portion, the second graphic layer covering the first portion;

and removing the second part exposed by the second pattern layer until the surface of the sacrificial layer is exposed.

16. The method of claim 15, wherein the pattern layer and the second pattern layer are formed using the same reticle.