US20050275109A1 - Semiconductor device and fabricating method thereof - Google Patents
Semiconductor device and fabricating method thereof Download PDFInfo
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- US20050275109A1 US20050275109A1 US11/160,594 US16059405A US2005275109A1 US 20050275109 A1 US20050275109 A1 US 20050275109A1 US 16059405 A US16059405 A US 16059405A US 2005275109 A1 US2005275109 A1 US 2005275109A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title description 12
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000007787 solid Substances 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 abstract description 11
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000002184 metal Substances 0.000 description 20
- 229910052751 metal Inorganic materials 0.000 description 20
- 238000005530 etching Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 9
- 238000000151 deposition Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to an integrated circuit and fabricating method thereof. More particularly, the present invention relates to a semiconductor device and method of fabricating the same.
- FIG. 1 is a top view showing the layout of conventional metal interconnects.
- the contact plug 20 in FIG. 1 has a critical dimension greater than the metal line 10 so that more metal lines 10 can be packed within the limited surface area of a chip.
- the alignment tolerance in the process of forming the contact opening is greatly reduced. Should an alignment error occur, a neighboring conductive structure such as the conductive layer of a gate structure may be exposed leading to a possible short circuit between a subsequently formed contact plug and the conductive structure.
- the overlay tolerance in photolithographic processing of the metal lines 10 is relatively small. Any minor misalignment will likely lead to an unwanted electrical connection or short-circuit between a metal line 10 and a neighboring plug.
- the present invention is to provide a semiconductor device and manufacturing method thereof for increasing overlay tolerance of metal interconnects.
- This invention is to provide a semiconductor device and manufacturing method thereof for preventing a short circuit between a contact plug and a neighboring conductive structure.
- the invention provides a method of manufacturing a semiconductor device.
- a conductive structure, spacers and a dielectric layer are formed over a substrate.
- a portion of the cap layer of the conductive structure, a portion of the spacer and a portion of the dielectric layer are removed by etching to form a funnel-shaped opening.
- the shoulder portion of the conductive layer within the conductive structure exposed by the funnel-shaped opening is removed to form a shoulder recess.
- a liner layer is formed on the sidewall of the funnel-shaped opening and then a bottom plug is formed in the funnel-shaped opening.
- another dielectric layer is formed over the substrate.
- a top plug is formed in the dielectric layer such that the top plug and the bottom plug are electrically connected.
- a wire line is formed on the upper surface of the substrate.
- the contact/via plug is fabricated by combining two sections together, namely, a bottom plug and a top plug.
- the top plug has a critical dimension smaller than the junction portion of the funnel shaped bottom plug, the alignment tolerance with respect to the bottom plug in the photolithographic process for forming the top plug opening is increased. Furthermore, with the top plug having a smaller critical dimension, the wire lines above the top plugs can have a larger alignment tolerance so that the probability of having a short circuit due to misalignment is lowered considerably.
- the shoulder chamfer or shoulder recess in the conductive layer of the conductive structure permits the formation of a thicker liner layer in this area. Therefore, the section between the bottom plug and the conductive layer, in particular, between the conductive layer and the shoulder section can have a thicker isolating liner layer for preventing plug/conductive layer short circuit.
- the semiconductor device comprises a plurality of conductive structures, a plurality of bottom plugs, a plurality of top plugs, a plurality of wire lines, a liner layer and a dielectric layer.
- the conductive structures are formed over a substrate.
- the bottom plugs have a funnel shape. Furthermore, the bottom plugs are positioned between neighboring conductive structures and are electrically connected to the substrate.
- the liner layer is set up between the neighboring conductive structures and the bottom plug.
- the top plug is set up over the bottom plug.
- the junction between the bottom plug and the top plug has a critical dimension greater than the top plug.
- the wire lines are electrically connected to the respective top lugs.
- the dielectric layer is set up between the conductive structures, between the bottom plugs, between the top plugs and between the wire lines.
- FIG. 1 is a top view showing the layout of conventional metal interconnects.
- FIGS. 2A through 2F are schematic cross-sectional views showing the progression of steps for fabricating metal interconnects according to one preferred embodiment of this invention.
- FIG. 3 is a top view of FIG. 2F .
- FIGS. 2A through 2F are schematic cross-sectional views showing the progression of steps for fabricating metal interconnects according to one preferred embodiment of this invention.
- a plurality of conductive structures 210 is formed over a substrate 200 .
- Each conductive structure 210 at least comprises a conductive layer 206 and a cap layer 208 .
- the conductive layer 206 further comprises a polysilicon layer 202 and a metal silicide layer 204 , for example.
- the cap layer 208 is a silicon nitride layer, for example.
- spacers 212 are formed on the sidewalls of the conductive structures 210 .
- the spacers 212 are silicon nitride layers formed by performing a chemical vapor deposition operation, for example.
- a dielectric layer 214 is formed over the substrate 100 .
- the dielectric layer 214 is formed, for example, by depositing dielectric material over the cap layer 208 and into the space between the spacers on the conductive structures 210 . This is followed by performing a chemical-mechanical polishing to remove the dielectric material above the cap layer 208 .
- the dielectric layer 214 is fabricated using silicon oxide or borophosphosilicate glass (BPSG), for example.
- a photoresist layer 216 is formed over the substrate 200 .
- the photoresist layer 216 has an opening 218 that exposes the dielectric layer 214 between two neighboring conductive structures 210 .
- an anisotropic etching operation is carried out using an etchant having a high selectivity ratio between the dielectric layer 214 and the cap layer 208 .
- the exposed dielectric layer 214 and a portion of the cap layer 212 and the spacers 212 are removed so that the shoulder section such as the metal silicide layer 204 of the conductive layer 206 is exposed.
- the opening 222 has a funnel shape after the etching operation.
- the photoresist layer 215 is removed.
- a portion of the exposed conductive layer 206 that is, the shoulder portion of the metal silicide layer 204 is removed so that a shoulder chamfer or a shoulder recess 224 is formed.
- a liner material layer 226 is formed over the substrate 200 to cover the dielectric layer 214 , the cap layer 208 and the sidewall and bottom section of the funnel-shaped opening 222 .
- the liner material layer 226 is fabricated using an insulating material such as silicon nitride or silicon oxide.
- the liner material layer 226 is formed, for example, by performing a chemical vapor deposition.
- the liner material layer 226 is fabricated using a material that differs from a subsequently formed dielectric layer 230 .
- an anisotropic back etching is carried out to remove the liner material layer 228 over the dielectric layer 214 and the cap layer 208 and at the bottom of the funnel-shaped opening 222 .
- the liner material layer 226 a on the sidewalls of the funnel-shaped opening 222 is retained to serve as a liner layer. Since the conductive layer 206 has a shoulder chamfer or a shoulder recess 224 , the liner layer 226 a at the shoulder section of the conductive layer 206 is the thickest.
- a conductive layer 228 is formed over the substrate to cover the dielectric layer 214 and the conductive structure 210 and fill the funnel-shaped opening 222 .
- the conductive layer 228 is fabricated using a metal material including tungsten or doped polysilicon, for example.
- a chemical-mechanical polishing operation is performed to remove the conductive layer 228 above the dielectric layer 214 and the conductive structure 210 .
- a conductive layer 228 a is retained within the funnel-shaped opening 333 to form a bottom plug.
- the dielectric layer 230 is formed over the substrate 200 .
- the dielectric layer 230 has an opening 232 that exposes a portion of the bottom plug 228 a .
- the opening 232 has a critical dimension smaller than the open end of the funnel-shaped opening 222 .
- the dielectric layer 230 is a silicon oxide layer formed, for example, by performing a chemical vapor deposition.
- the liner layer 226 a is fabricated using a material that differs from the dielectric layer 230 .
- the liner layer 226 a may serve as an etching stop layer to prevent any over-etching in processing the dielectric layer 230 .
- another conductive layer is formed over the substrate 200 to cover the dielectric layer 230 and fill the opening 232 .
- the conductive layer inside the opening 232 forms a top plug 234 b .
- the conductive layer is fabricated using a metal material including, tungsten or doped polysilicon layer, for example. Thereafter, photolithographic and etching processes are carried out to pattern the conductive layer and form a plurality of wire lines 234 a.
- FIG. 2F is a schematic cross-sectional view of a semiconductor device structure according to a preferred embodiment of this invention.
- FIG. 3 is a top view of FIG. 2F .
- the semiconductor device comprises a plurality of conductive structures 210 , a plurality of bottom plugs 228 a , a plurality of top plugs 234 b , a plurality of wire lines 234 a , a liner layer 226 a and a pair of dielectric layers 214 and 230 .
- the conductive structures 210 are formed over a substrate 200 .
- the bottom plugs 228 a is a solid block with a funnel shape.
- the bottom plugs 228 are positioned between neighboring conductive structures 210 and electrically connected to the substrate 200 .
- the liner layer 226 a is set up between neighboring conductive structures 210 and the bottom plugs 228 a .
- the top plugs 234 b which are solid blocks with a cylindrical shape, are set up over the respective bottom plugs 228 a .
- the junction portion of the bottom plug 228 a connected to the top plug 234 b has a critical dimension greater than the top plug 234 b .
- the wire lines 234 a are electrically connected to respective top plugs 234 b .
- the dielectric layer 214 is set up between the conductive structures 210 and between the bottom plugs 228 a .
- the dielectric layer 230 is set up between the top plugs 234 b and the wire lines 234 a.
- the conductive structures 210 are gate structures that comprises a gate dielectric layer (not shown), a polysilicon layer 202 , a metal silicide layer 204 and a cap layer 212 .
- the wire lines 234 a are bit lines and the top plug 234 b and the bottom plug 228 a together constitute a bit line contact.
- the contact/via plug is formed by combining two plug sections together, namely, a bottom plug 228 a and a top plug 234 b .
- the aspect ratio of the contact/via opening in the process of forming the contact/via is reduced.
- an anisotropic etching process is performed to remove a portion of the dielectric layer 214 , the cap layer 208 and the spacers 212 and form a funnel-shaped opening 222 .
- the photolithographic process for forming the opening 232 in the dielectric layer 230 can have a higher alignment tolerance with respect to the bottom plug 228 a .
- the wire lines 234 a above the top plugs 234 b can have a larger alignment tolerance so that the probability of having a short circuit due to misalignment is lowered considerably.
- the shoulder chamfer or shoulder recess 224 in the conductive layer 206 of the conductive structure 210 permits the formation of a thicker liner layer 226 a in this area.
- the section between the bottom plug 228 a and the conductive layer 206 in particular, between the conductive layer 206 and the shoulder section can have a thicker isolating liner layer 226 a for preventing plug/conductive layer short circuit.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor device and method of manufacturing the same are disclosed. A conductive structure, spacers and a dielectric layer are formed on a substrate. Thereafter, a portion of the cap layer, a portion of the spacers and a portion of the dielectric layer of the conductive structure are removed to form a funnel-shaped opening. The shoulder section of the conductive layer exposed by the funnel-shaped opening is removed to form a shoulder recess. A liner layer is formed on the sidewall of the funnel-shaped opening and then a bottom plug is formed inside the funnel-shaped opening. Another dielectric layer is formed over the substrate. A top plug is formed in the dielectric layer such that the top plug and the bottom plug are electrically connected. Finally, a wire line is formed over the substrate.
Description
- This application is a divisional of a prior application Ser. No. 10/605,306, filed Sep. 22, 2003, which claims the priority benefit of Taiwan application serial no. 921191 09, filed on Jul. 14, 2003.
- 1. Field of the Invention
- The present invention relates to an integrated circuit and fabricating method thereof. More particularly, the present invention relates to a semiconductor device and method of fabricating the same.
- 2. Description of the Related Art
- Typically, integrated circuit devices are interconnected via metal interconnects. The conventional method of fabricating metal interconnects includes forming a metal plug in a dielectric layer and then forming a metal line over a substrate to connect with the metal plug.
FIG. 1 is a top view showing the layout of conventional metal interconnects. As the level of integration for semiconductor devices continues to increase, the aspect ratio of contact openings must be reduced to avoid difficulties encountered while carrying out etching and material deposition. At present, thecontact plug 20 inFIG. 1 has a critical dimension greater than themetal line 10 so thatmore metal lines 10 can be packed within the limited surface area of a chip. - With the
contact plug 20 having a larger critical dimension, the alignment tolerance in the process of forming the contact opening is greatly reduced. Should an alignment error occur, a neighboring conductive structure such as the conductive layer of a gate structure may be exposed leading to a possible short circuit between a subsequently formed contact plug and the conductive structure. - Furthermore, with the critical dimension of the
contact plug 20 greater than themetal line 10 and the pitch between neighboringmetal line 10 reduced, the overlay tolerance in photolithographic processing of themetal lines 10 is relatively small. Any minor misalignment will likely lead to an unwanted electrical connection or short-circuit between ametal line 10 and a neighboring plug. - Accordingly, the present invention is to provide a semiconductor device and manufacturing method thereof for increasing overlay tolerance of metal interconnects.
- This invention is to provide a semiconductor device and manufacturing method thereof for preventing a short circuit between a contact plug and a neighboring conductive structure.
- To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a semiconductor device. First, a conductive structure, spacers and a dielectric layer are formed over a substrate. Thereafter, a portion of the cap layer of the conductive structure, a portion of the spacer and a portion of the dielectric layer are removed by etching to form a funnel-shaped opening. The shoulder portion of the conductive layer within the conductive structure exposed by the funnel-shaped opening is removed to form a shoulder recess. A liner layer is formed on the sidewall of the funnel-shaped opening and then a bottom plug is formed in the funnel-shaped opening. Afterwards, another dielectric layer is formed over the substrate. A top plug is formed in the dielectric layer such that the top plug and the bottom plug are electrically connected. Finally, a wire line is formed on the upper surface of the substrate.
- In this invention, the contact/via plug is fabricated by combining two sections together, namely, a bottom plug and a top plug. With this setup, the aspect ratio of the contact/via opening in the process of forming the contact/via is very much reduced. Hence, the process of etching out contact/via openings and the deposition of conductive material into the opening thereafter is greatly simplified.
- Because the top plug has a critical dimension smaller than the junction portion of the funnel shaped bottom plug, the alignment tolerance with respect to the bottom plug in the photolithographic process for forming the top plug opening is increased. Furthermore, with the top plug having a smaller critical dimension, the wire lines above the top plugs can have a larger alignment tolerance so that the probability of having a short circuit due to misalignment is lowered considerably.
- In addition, the shoulder chamfer or shoulder recess in the conductive layer of the conductive structure permits the formation of a thicker liner layer in this area. Therefore, the section between the bottom plug and the conductive layer, in particular, between the conductive layer and the shoulder section can have a thicker isolating liner layer for preventing plug/conductive layer short circuit.
- This invention also provides a semiconductor device. The semiconductor device comprises a plurality of conductive structures, a plurality of bottom plugs, a plurality of top plugs, a plurality of wire lines, a liner layer and a dielectric layer. The conductive structures are formed over a substrate. The bottom plugs have a funnel shape. Furthermore, the bottom plugs are positioned between neighboring conductive structures and are electrically connected to the substrate. The liner layer is set up between the neighboring conductive structures and the bottom plug. The top plug is set up over the bottom plug. The junction between the bottom plug and the top plug has a critical dimension greater than the top plug. The wire lines are electrically connected to the respective top lugs. The dielectric layer is set up between the conductive structures, between the bottom plugs, between the top plugs and between the wire lines.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
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FIG. 1 is a top view showing the layout of conventional metal interconnects. -
FIGS. 2A through 2F are schematic cross-sectional views showing the progression of steps for fabricating metal interconnects according to one preferred embodiment of this invention. -
FIG. 3 is a top view ofFIG. 2F . - Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
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FIGS. 2A through 2F are schematic cross-sectional views showing the progression of steps for fabricating metal interconnects according to one preferred embodiment of this invention. As shown inFIG. 2A , a plurality ofconductive structures 210 is formed over asubstrate 200. Eachconductive structure 210 at least comprises aconductive layer 206 and acap layer 208. Theconductive layer 206 further comprises apolysilicon layer 202 and a metal silicide layer 204, for example. Thecap layer 208 is a silicon nitride layer, for example. Thereafter,spacers 212 are formed on the sidewalls of theconductive structures 210. Thespacers 212 are silicon nitride layers formed by performing a chemical vapor deposition operation, for example. Adielectric layer 214 is formed over the substrate 100. Thedielectric layer 214 is formed, for example, by depositing dielectric material over thecap layer 208 and into the space between the spacers on theconductive structures 210. This is followed by performing a chemical-mechanical polishing to remove the dielectric material above thecap layer 208. Thedielectric layer 214 is fabricated using silicon oxide or borophosphosilicate glass (BPSG), for example. - As shown in
FIG. 2B , aphotoresist layer 216 is formed over thesubstrate 200. Thephotoresist layer 216 has anopening 218 that exposes thedielectric layer 214 between two neighboringconductive structures 210. Using thephotoresist layer 216 as an etching mask, an anisotropic etching operation is carried out using an etchant having a high selectivity ratio between thedielectric layer 214 and thecap layer 208. Ultimately, the exposeddielectric layer 214 and a portion of thecap layer 212 and thespacers 212 are removed so that the shoulder section such as the metal silicide layer 204 of theconductive layer 206 is exposed. Because the etchant has a high etching selectivity ratio between thedielectric layer 214 and thecap layer 208/thespacers 212, a low etching rate for thecap layer 208 and thespacers 212 but a high etching rate for thedielectric layer 214, theopening 222 has a funnel shape after the etching operation. - As shown in
FIG. 2C , the photoresist layer 215 is removed. A portion of the exposedconductive layer 206, that is, the shoulder portion of the metal silicide layer 204 is removed so that a shoulder chamfer or ashoulder recess 224 is formed. Thereafter, aliner material layer 226 is formed over thesubstrate 200 to cover thedielectric layer 214, thecap layer 208 and the sidewall and bottom section of the funnel-shapedopening 222. Theliner material layer 226 is fabricated using an insulating material such as silicon nitride or silicon oxide. Theliner material layer 226 is formed, for example, by performing a chemical vapor deposition. Preferably, theliner material layer 226 is fabricated using a material that differs from a subsequently formeddielectric layer 230. - As shown in
FIG. 2D , an anisotropic back etching is carried out to remove theliner material layer 228 over thedielectric layer 214 and thecap layer 208 and at the bottom of the funnel-shapedopening 222. Theliner material layer 226 a on the sidewalls of the funnel-shapedopening 222 is retained to serve as a liner layer. Since theconductive layer 206 has a shoulder chamfer or ashoulder recess 224, theliner layer 226 a at the shoulder section of theconductive layer 206 is the thickest. Thereafter, aconductive layer 228 is formed over the substrate to cover thedielectric layer 214 and theconductive structure 210 and fill the funnel-shapedopening 222. Theconductive layer 228 is fabricated using a metal material including tungsten or doped polysilicon, for example. - As shown in
FIG. 2E , a chemical-mechanical polishing operation is performed to remove theconductive layer 228 above thedielectric layer 214 and theconductive structure 210. Hence, aconductive layer 228 a is retained within the funnel-shaped opening 333 to form a bottom plug. Thereafter, thedielectric layer 230 is formed over thesubstrate 200. Thedielectric layer 230 has anopening 232 that exposes a portion of thebottom plug 228 a. Theopening 232 has a critical dimension smaller than the open end of the funnel-shapedopening 222. Thedielectric layer 230 is a silicon oxide layer formed, for example, by performing a chemical vapor deposition. In general, theliner layer 226 a is fabricated using a material that differs from thedielectric layer 230. Thus, even if there is some misalignment when theopening 232 is formed via a photolithographic process, theliner layer 226 a may serve as an etching stop layer to prevent any over-etching in processing thedielectric layer 230. - As shown in
FIG. 2F , another conductive layer is formed over thesubstrate 200 to cover thedielectric layer 230 and fill theopening 232. The conductive layer inside the opening 232 forms atop plug 234 b. The conductive layer is fabricated using a metal material including, tungsten or doped polysilicon layer, for example. Thereafter, photolithographic and etching processes are carried out to pattern the conductive layer and form a plurality ofwire lines 234 a. -
FIG. 2F is a schematic cross-sectional view of a semiconductor device structure according to a preferred embodiment of this invention.FIG. 3 is a top view ofFIG. 2F . As shown inFIGS. 2F and 3 , the semiconductor device comprises a plurality ofconductive structures 210, a plurality of bottom plugs 228 a, a plurality oftop plugs 234 b, a plurality ofwire lines 234 a, aliner layer 226 a and a pair ofdielectric layers conductive structures 210 are formed over asubstrate 200. The bottom plugs 228 a is a solid block with a funnel shape. The bottom plugs 228 are positioned between neighboringconductive structures 210 and electrically connected to thesubstrate 200. Theliner layer 226 a is set up between neighboringconductive structures 210 and the bottom plugs 228 a. The top plugs 234 b, which are solid blocks with a cylindrical shape, are set up over the respective bottom plugs 228 a. The junction portion of thebottom plug 228 a connected to thetop plug 234 b has a critical dimension greater than thetop plug 234 b. The wire lines 234 a are electrically connected to respectivetop plugs 234 b. Thedielectric layer 214 is set up between theconductive structures 210 and between the bottom plugs 228 a. Thedielectric layer 230 is set up between thetop plugs 234 b and thewire lines 234 a. - When this invention is applied to fabricate a memory device, the
conductive structures 210 are gate structures that comprises a gate dielectric layer (not shown), apolysilicon layer 202, a metal silicide layer 204 and acap layer 212. In this case, thewire lines 234 a are bit lines and thetop plug 234 b and thebottom plug 228 a together constitute a bit line contact. - In this invention, the contact/via plug is formed by combining two plug sections together, namely, a
bottom plug 228 a and atop plug 234 b. With this setup, the aspect ratio of the contact/via opening in the process of forming the contact/via is reduced. Hence, the process of etching out contact/via openings and the deposition of conductive material into the opening thereafter is very much simplified. Note also that an anisotropic etching process is performed to remove a portion of thedielectric layer 214, thecap layer 208 and thespacers 212 and form a funnel-shapedopening 222. Since the funnel-shapedopening 222 has a critical dimension larger than theopening 232, the photolithographic process for forming theopening 232 in thedielectric layer 230 can have a higher alignment tolerance with respect to thebottom plug 228 a. Furthermore, with theopening 232 having a smaller critical dimension, thewire lines 234 a above the top plugs 234 b can have a larger alignment tolerance so that the probability of having a short circuit due to misalignment is lowered considerably. - In addition, the shoulder chamfer or
shoulder recess 224 in theconductive layer 206 of theconductive structure 210 permits the formation of athicker liner layer 226 a in this area. Thus, the section between thebottom plug 228 a and theconductive layer 206, in particular, between theconductive layer 206 and the shoulder section can have a thicker isolatingliner layer 226 a for preventing plug/conductive layer short circuit. - It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims (6)
1. A semiconductor device, comprising:
a substrate;
a plurality of conductive structures formed on the substrate;
a plurality of bottom plugs set up between neighboring conductive structures and electrically connected to the substrate;
a liner layer set up between the neighboring conductive structures and the conductive bottom plugs;
a plurality of top plugs set up over the respective bottom plugs, wherein the junction portion of the bottom plug connected to the top plug has a critical dimension greater than the top plug;
a plurality of wire lines connected electrically to the respective top plugs; and
a dielectric layer set up between the conductive structure, between the bottom plugs and between the top plugs and between the wire lines.
2. The semiconductor device of claim 1 , wherein the bottom plug is a solid block with a funnel shape.
3. The semiconductor device of claim 1 , wherein the top plug is a solid block with a cylindrical shape.
4. The semiconductor device of claim 1 , wherein each conductive structure further comprises a conductive layer with a shoulder recess.
5. A semiconductor device, comprising:
a substrate;
a plurality of conductive structures on the substrate with each conductive structure comprising a conductive layer and a cap layer, wherein the conductive layer of every pair of neighboring conductive structures has a recess shoulder;
a plurality of conductive plugs set up between neighboring conductive structures and electrically connected to the substrate; and a liner layer set up between neighboring conductive structures and the conductive plugs.
6. The semiconductor device of claim 5 , wherein the conductive plug is a solid block with a funnel shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US11/160,594 US20050275109A1 (en) | 2003-07-14 | 2005-06-30 | Semiconductor device and fabricating method thereof |
Applications Claiming Priority (4)
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TW92119109 | 2003-07-14 | ||
TW092119109A TWI223380B (en) | 2003-07-14 | 2003-07-14 | Semiconductor device and method of fabricating the same |
US10/605,306 US6933229B2 (en) | 2003-07-14 | 2003-09-22 | Method of manufacturing semiconductor device featuring formation of conductive plugs |
US11/160,594 US20050275109A1 (en) | 2003-07-14 | 2005-06-30 | Semiconductor device and fabricating method thereof |
Related Parent Applications (1)
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US10/605,306 Division US6933229B2 (en) | 2003-07-14 | 2003-09-22 | Method of manufacturing semiconductor device featuring formation of conductive plugs |
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US20050275109A1 true US20050275109A1 (en) | 2005-12-15 |
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US10/605,306 Expired - Lifetime US6933229B2 (en) | 2003-07-14 | 2003-09-22 | Method of manufacturing semiconductor device featuring formation of conductive plugs |
US11/160,594 Abandoned US20050275109A1 (en) | 2003-07-14 | 2005-06-30 | Semiconductor device and fabricating method thereof |
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US10/605,306 Expired - Lifetime US6933229B2 (en) | 2003-07-14 | 2003-09-22 | Method of manufacturing semiconductor device featuring formation of conductive plugs |
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US (2) | US6933229B2 (en) |
TW (1) | TWI223380B (en) |
Cited By (2)
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US20090134525A1 (en) * | 2007-11-23 | 2009-05-28 | Jong-Wan Ma | Semiconductor device having a filling pattern around a storage structure and method of forming the same |
US20140332809A1 (en) * | 2011-03-04 | 2014-11-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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US20080272410A1 (en) * | 2007-05-02 | 2008-11-06 | Chung-Te Lin | Self-Aligned Spacer Contact |
KR100890400B1 (en) * | 2007-05-03 | 2009-03-26 | 삼성전자주식회사 | Conductive structure and method for forming the same, and non-volatile memory device including the conductive structure and method for forming the same |
US9735134B2 (en) | 2014-03-12 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with through-vias having tapered ends |
CN105720039B (en) * | 2014-12-04 | 2020-05-08 | 中芯国际集成电路制造(上海)有限公司 | Interconnect structure and method of forming the same |
JP2016174064A (en) * | 2015-03-17 | 2016-09-29 | 株式会社東芝 | Semiconductor device and semiconductor device manufacturing method |
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US6235593B1 (en) * | 1999-02-18 | 2001-05-22 | Taiwan Semiconductor Manufacturing Company | Self aligned contact using spacers on the ILD layer sidewalls |
US6486067B1 (en) * | 1999-10-29 | 2002-11-26 | Taiwan Semiconductor Manufacturing Company | Method for improving the electrical isolation between the contact and gate in a self-aligned contact MOSFET device structure |
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US6348709B1 (en) * | 1999-03-15 | 2002-02-19 | Micron Technology, Inc. | Electrical contact for high dielectric constant capacitors and method for fabricating the same |
JP4807894B2 (en) * | 1999-05-31 | 2011-11-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP3759895B2 (en) * | 2001-10-24 | 2006-03-29 | 松下電器産業株式会社 | Etching method |
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- 2003-07-14 TW TW092119109A patent/TWI223380B/en not_active IP Right Cessation
- 2003-09-22 US US10/605,306 patent/US6933229B2/en not_active Expired - Lifetime
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- 2005-06-30 US US11/160,594 patent/US20050275109A1/en not_active Abandoned
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US6235593B1 (en) * | 1999-02-18 | 2001-05-22 | Taiwan Semiconductor Manufacturing Company | Self aligned contact using spacers on the ILD layer sidewalls |
US6486067B1 (en) * | 1999-10-29 | 2002-11-26 | Taiwan Semiconductor Manufacturing Company | Method for improving the electrical isolation between the contact and gate in a self-aligned contact MOSFET device structure |
US6486033B1 (en) * | 2001-03-16 | 2002-11-26 | Taiwan Semiconductor Manufacturing Company | SAC method for embedded DRAM devices |
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US20090134525A1 (en) * | 2007-11-23 | 2009-05-28 | Jong-Wan Ma | Semiconductor device having a filling pattern around a storage structure and method of forming the same |
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US20140332809A1 (en) * | 2011-03-04 | 2014-11-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US9905557B2 (en) * | 2011-03-04 | 2018-02-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
TW200503154A (en) | 2005-01-16 |
US6933229B2 (en) | 2005-08-23 |
US20050012218A1 (en) | 2005-01-20 |
TWI223380B (en) | 2004-11-01 |
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