KR20040038237A - Electrode and Method for fabricating of poly-TFT using the same - Google Patents

Abstract

PURPOSE: A fabrication method of a polycrystal TFT using an electrode is provided to design a surface of an electrode directly contacted with an amorphous preceding film in projection shape instead of a flat type, in order to supply a uniform contact area between the electrode and the amorphous preceding film, thereby applying a uniform electric field. CONSTITUTION: A silicon insulating material is deposited on a substrate(300), and a buffer layer(302) is formed. After depositing an amorphous silicon on the buffer layer(302), an amorphous preceding film(304) is defined through a dehydrogenation process. On one side and other side of the amorphous preceding film(304) where a catalyst metal is deposited, an electrode is disposed. Sides of the electrode contacted with the amorphous preceding film(304) can be configured as plural projections. The electrode can be divided in plural, so as to independently apply electric fields. A high voltage is applied to the electrode while maintaining a certain temperature, and crystallization is carried out.

Description

Electrode and Method for Fabricating Poly-crystalline Thin Film Transistor Using the Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline thin film transistor for a liquid crystal display device, and more particularly, to a shape of an electrode used when crystallizing an active layer of a thin film transistor, a method of manufacturing a polycrystalline thin film transistor using the same, and a method of manufacturing a polycrystalline thin film transistor including the same. .

Generally, in order to form a polycrystalline silicon thin film, pure amorphous silicon (intrinsic amorphous silicon) in a predetermined method, that is, plasma silicon vapor deposition (Plasma chemical vapor deposition) or LPCVD (Low pressure CVD) method of amorphous silicon with a thickness of 500 Å on the insulating substrate After the film was deposited, a method of crystallizing it was used. Crystallization methods can be classified into three categories as follows.

First, laser annealing is a method of growing polycrystalline silicon by applying a laser to a substrate on which an amorphous silicon thin film is deposited.

Second, solid phase crystallization (hereinafter referred to as SPC) method is a method of forming polycrystalline silicon by heat-treating amorphous silicon for a long time at a high temperature.

Third, the metal induced crystallization (MIC) method is a method of forming a polycrystalline silicon by depositing a metal on amorphous silicon, a large-area glass substrate can be used.

The first method, laser heat treatment, is a method of forming polycrystalline silicon, which is currently widely studied, which supplies laser energy to a substrate on which amorphous silicon is deposited to make the amorphous silicon in a molten state, and then forms polycrystalline silicon by cooling.

The second method, solid crystallization, forms a buffer layer with a predetermined thickness to prevent diffusion of impurities on a quartz substrate that can withstand high temperatures of 600 ° C. or higher, deposits amorphous silicon on the buffer layer, and then As a method of obtaining polycrystalline silicon by heat treatment at high temperature for a long time, as described above, since the solid phase crystallization is performed for a long time at a high temperature, a desired polycrystalline silicon phase cannot be obtained, and the grain growth direction is irregular, so that the polycrystalline silicon is applied to a thin film transistor. The breakdown voltage of the device is lowered due to the irregular growth of the gate insulating layer to be connected to the gate, and the grain size of the polycrystalline silicon is extremely uneven to degrade the electrical characteristics of the device, and an expensive quartz substrate should be used. There is a problem.

The third method, metal-induced crystallization, can form polycrystalline silicon using a low-cost, large-area glass substrate, but it ensures the reliability of the film because metal residues are likely to exist in the network inside the polycrystalline silicon. Although it is difficult, a new application of the MIC method is attempting to apply crystallized polycrystalline silicon to thin film transistors and switching elements of liquid crystal displays.

A more advanced crystallization method of the MIC method is an electric field-metal induction method (FE-MIC) in which amorphous silicon is formed into crystalline chamber silicon by applying a high voltage, and the main heat generated from the metal by the high voltage.

The field induction crystallization method is to deposit a metal on the amorphous silicon, and by applying a direct current high voltage to the metal to generate a columnar heat to play a catalytic role in the amorphous silicon crystallization. In this case, the metal is called a catalyst metal.

Hereinafter, a method of crystallizing amorphous silicon by the FE-MIC method will be described with reference to the accompanying drawings.

1A to 1C is It is process sectional drawing which shows the conventional silicon crystal process using the FE-MIC method in order.

First, as shown in FIG. 1A, a silicon insulating material such as silicon oxide (SiO ₂ ) is deposited on the substrate 10 to form a buffer layer 12.

The buffer layer 12 is for blocking an alkali-based material eluted to the substrate 10 during the process, and is useful when the substrate is formed of an alkali-based material.

Next, amorphous silicon is deposited on the buffer layer 12, and then dehydrogenation is performed to form the amorphous preceding film 14.

As shown in FIG. 1B, a process of depositing a catalyst metal 16 such as nickel (Ni) on the surface of the amorphous preceding film 14 is performed.

As shown in FIG. 1C, the positive electrode 18 and the negative electrode 20 are contacted and applied to one side and the other side of the amorphous preceding film on which the catalytic metal is deposited at a predetermined temperature. The process of crystallizing the amorphous preceding film 14 is performed.

When the process as described above is completed, as shown in FIG. 1D, the polysilicon layer 24 including the plurality of crystal grains 20 and the grain boundaries 22 may be formed.

However, in the conventional crystallization method, since the surface of the electrode is flat, the electrode and the amorphous preceding film are in two-dimensional contact, which may cause non-uniformity of the electric field along the length of the electrode.

As a result, a problem arises in that the crystal state is also unevenly distributed.

The present invention has been proposed for the purpose of solving the above-described problems, firstly, by designing a projection shape without forming a flat surface of the electrode in direct contact with the amorphous preceding film, uniformity between the electrode and the amorphous preceding film By providing a contact area to apply a uniform electric field, and secondly, the electric field is monitored at each electrode part by using a multiple power supply method in which the electrode is divided into a plurality of electrodes and an electric field is independently applied to each divided electrode. In order to control each electric field independently, a uniform distribution of current flows during crystallization to obtain uniformity of crystallization.

1A to 1D are cross-sectional views illustrating a conventional polycrystalline silicon crystallization process according to a process sequence;

2 is a view for explaining a method for crystallizing amorphous silicon by the FE-MIC method,

3 is a cross-sectional view schematically showing the configuration of an electrode according to a first embodiment of the present invention,

4 is a view for explaining a method for crystallizing amorphous silicon using an electrode according to a second embodiment of the present invention,

5A to 5H are cross-sectional views illustrating a manufacturing process of a polycrystalline thin film transistor according to the present invention in a process sequence.

<Description of the symbols for the main parts of the drawings>

104 or 106: electrode for high voltage application

108: turning

The electrode for electric field metal induction crystallization according to the first aspect of the present invention for achieving the above object is composed of a plurality of protrusions in contact with the preceding film for crystallization.

The field-metal-induced crystallization electrode according to the second aspect of the present invention is configured by dividing a plurality of (+) electrodes and (-) electrodes on one side and the other side of the preceding film to be crystallized, and configured to connect independent power sources, respectively. .

Polycrystalline thin film transistor manufacturing method according to the present invention using the above-described electrode comprises the steps of forming an amorphous precursor film by depositing amorphous silicon on the entire surface of the substrate; Depositing a catalytic metal on top of the amorphous silicon; Forming an electrode for high voltage application in which the catalyst metal is located on one side and the other side of the amorphous preceding film and the electric field is evenly distributed on the amorphous preceding film; Applying a high voltage to the electrode to crystallize an amorphous preceding film to form a polycrystalline silicon thin film; Patterning the polycrystalline silicon thin film in an island shape to form an active layer; Forming a gate insulating film, which is a second insulating film, on the active layer; Forming a gate electrode on the active layer over the gate insulating film; Doping an active layer on both sides of the gate electrode to form an ohmic contact region; Forming an interlayer insulating film on an entire surface of the substrate on which the ohmic contact region is formed, thereby forming a first contact hole and a second contact hole exposing a portion of the ohmic contact region; Forming a source electrode and a drain electrode respectively contacting the ohmic region contact region through the first contact hole and the second contact hole.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example 1

The first embodiment of the present invention is characterized in that the surface of the electrode in contact with the amorphous preceding film is formed with a plurality of projections.

2 is a plan view showing the shape of an amorphous preceding film and an electrode for crystallizing amorphous silicon.

As shown, the amorphous preceding film 102 subjected to the dehydrogenation process described above is formed on the substrate 100. Next, although not shown, a catalytic metal is deposited on top of the amorphous preceding film.

At temperatures of about 500 ° C. to 550 ° C., negative electrodes and positive electrodes are disposed on both sides of the amorphous preceding film, and a high voltage is applied to perform crystallization.

At this time, the shape of the electrode in contact with the amorphous preceding film is as follows in the configuration of FIG.

3 is a view showing a cross-sectional configuration of an electrode according to the first embodiment of the present invention. As shown, the surface of the electrode 104 or 106 is formed of a plurality of projections 108, the projections 108 ) May be configured in various shapes, the cross section of the end of which includes a circle or a triangle.

When the projection 108 contacts the electrode 104 or 106 with the amorphous preceding film (102 in FIG. 2), the protrusion 108 has superior contact characteristics as compared with the flat contact surface, The distribution can also be made uniform.

At this time, the sharper the end of the projection takes a large electric field, the contact shape can be variously modified.

The electrode configured in the shape as described above has the advantage that can eliminate the nonuniformity of the electric field in the conventional longitudinal direction.

Modifications of the first embodiment will be described below with reference to the second embodiment.

Second Embodiment

A second embodiment of the present invention is characterized in that the electrode is divided into a plurality of configurations.

4 is a plan view for explaining the configuration of an electrode according to a second embodiment of the present invention.

As shown in the drawing, after the dehydrogenation process is performed on the substrate 200, a catalyst metal is deposited on the amorphous precursor film 202, and the number of pieces separated on one side and the other of the amorphous precursor film 202 (+) is increased. The electrode 204 and the negative electrode 206 are formed.

At this time, a plurality of divided (+) electrode 204 and (-) electrode 206 are configured to face each other by the same number, each configured in a manner of applying an electric field independently.

That is, the positive electrode 204 and the negative electrode 206 consist of independent power sources 208 for each of the divided electrodes, and this configuration monitors the electric field distribution applied according to the position of the amorphous preceding film 202. Make it possible.

Therefore, during the crystallization, each power source 208 measures an amount of current, and then applies an electric field differently to each electrode so as to achieve uniform crystallization as a whole.

The crystallization process of the polycrystalline thin film transistor using the electrodes mentioned in the first and second embodiments as described above will be described below with reference to FIGS. 5A to 5H.

5A through 5H are cross-sectional views illustrating a method of manufacturing a polycrystalline silicon thin film transistor including an active layer crystallized using an electrode of the present invention, in a process sequence.

First, as shown in FIG. 5A, a silicon insulating material is deposited on the substrate 300 to form a buffer layer 302.

After depositing amorphous silicon (a-Si: H) on the buffer layer 302, a dehydrogenation process is performed to form an amorphous preceding film 304.

As shown in FIG. 5B, a process of depositing a catalyst metal 306 such as nickel on the amorphous preceding film 304 is performed.

Next, an electrode is formed on one side and the other side of the amorphous preceding film 304 on which the catalytic metal 306 is deposited. The shape of the electrode is in contact with the amorphous preceding film 304 as shown in FIG. 5C. The surface may be composed of a plurality of projections 307, as shown in Figure 5d may be divided into a plurality of electrodes 310 may be configured to apply an electric field independently of each other.

After the electrode is configured as described above, crystallization is performed by applying a high voltage to the electrode while maintaining a temperature of 500 ° C to 550 ° C.

Although not shown, when the crystallization is completed, a process of removing the catalytic metal is performed.

As shown in FIG. 5E, the crystallized silicon layer is patterned to form an island-shaped active layer 314.

Subsequently, silicon nitride (SiN ₂ ) or silicon oxide (SiO ₂ ) is deposited on the active layer 314 to form a gate insulating layer 316.

The active layer 314 may be divided into two regions: a first active region 314a serving as an active channel layer and a second active region 314b which is doped with impurities and becomes an ohmic region.

As illustrated in FIG. 5F, a low-resistance metal including aluminum (Al) and an aluminum alloy is deposited and patterned on the entire surface of the substrate 300 on which the gate insulating layer 316 is formed to correspond to the first active region. The gate electrode 318 is formed on the gate insulating film 316.

Subsequently, the second active region 314b is formed as an ohmic region by doping n + or p + impurity ions onto the entire surface of the substrate 300 on which the gate electrode 318 is formed.

In this case, when the ion doping is performed using an implantation method, the surface of the second active region 314b doped with the impurity ions is severely damaged.

Accordingly, the activation process is performed at a predetermined temperature to restore the surface of the second active region 314b to its original state, and to spread the doped ions evenly.

In some cases, the gate insulating layer 316 may be etched using the gate electrode 318 as an etch stopper.

Next, as shown in FIG. 5G, the insulating material as described above is deposited on the entire surface of the substrate 300 on which the gate electrode 318 is formed to form the interlayer insulating film 320.

Subsequently, the interlayer insulating layer 320 is patterned to expose the first contact hole 322 and the second contact hole 324 that respectively expose the second active region 314b on both sides of the first active region 314a. Form.

Next, as shown in FIG. 5H, copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), and tantalum (Ta) are formed on the entire surface of the substrate 300 on which the interlayer insulating film 320 is formed. And depositing and patterning one selected from the group of conductive metals including titanium (Ti) and the like to form a source electrode 326 and a drain electrode 328 respectively contacting the exposed second active region 314b.

Through the process as described above it can be produced a polycrystalline thin film transistor according to the present invention.

As described above, by modifying the shape of the electrode for applying a high voltage to the amorphous leading film, the electric field can be evenly distributed over the entire surface of the amorphous preceding film, and an active layer having an evenly distributed grain can be obtained. There is an effect to manufacture an improved polycrystalline thin film transistor.

Claims (5)

In the electrode used to crystallize amorphous silicon by a field-metal induced crystallization method, An electrode for electric field-metal induction crystallization, in which a surface contacting a preceding film for crystallization is composed of a plurality of protrusions. In the electrode used to crystallize amorphous silicon by a field-metal induced crystallization method, An electrode for electric field-metal induction crystallization, which is formed by dividing a plurality of (+) electrodes and (-) electrodes on one side and the other side of the preceding film to be crystallized, and configured to connect independent power sources. Depositing amorphous silicon on the entire surface of the substrate to form an amorphous preceding film; Depositing a catalytic metal on top of the amorphous silicon; Forming an electrode for high voltage application in which the catalyst metal is located on one side and the other side of the amorphous preceding film and the electric field is evenly distributed on the amorphous preceding film; Applying a high voltage to the electrode to crystallize an amorphous preceding film to form a polycrystalline silicon thin film; Patterning the polycrystalline silicon thin film in an island shape to form an active layer; Forming a gate insulating film, which is a second insulating film, on the active layer; Forming a gate electrode on the active layer over the gate insulating film; Doping an active layer on both sides of the gate electrode to form an ohmic contact region; Forming an interlayer insulating film on an entire surface of the substrate on which the ohmic contact region is formed, thereby forming a first contact hole and a second contact hole exposing a portion of the ohmic contact region; Forming a source electrode and a drain electrode respectively contacting the ohmic region contact region through the first contact hole and the second contact hole; Polycrystalline thin film transistor manufacturing method comprising a. The method of claim 3, wherein The electrode is a polycrystalline thin film transistor manufacturing method of the surface formed with a plurality of projections. The method of claim 3, wherein The electrode may be configured by dividing a plurality of (+) electrodes and (-) electrodes on one side and the other side of the amorphous preceding layer, and configured to connect independent power sources, respectively.