KR20040025817A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

Info

Publication number
KR20040025817A
KR20040025817A KR1020030059429A KR20030059429A KR20040025817A KR 20040025817 A KR20040025817 A KR 20040025817A KR 1020030059429 A KR1020030059429 A KR 1020030059429A KR 20030059429 A KR20030059429 A KR 20030059429A KR 20040025817 A KR20040025817 A KR 20040025817A
Authority
KR
South Korea
Prior art keywords
wiring
center
connecting portion
distance
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020030059429A
Other languages
English (en)
Korean (ko)
Inventor
무라타토모오
야부키시노부
야마시타타케오
Original Assignee
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가부시키가이샤 히타치세이사쿠쇼
Publication of KR20040025817A publication Critical patent/KR20040025817A/ko
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020030059429A 2002-09-20 2003-08-27 반도체장치 및 그 제조방법 Ceased KR20040025817A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2002-00274466 2002-09-20
JP2002274466A JP4373065B2 (ja) 2002-09-20 2002-09-20 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
KR20040025817A true KR20040025817A (ko) 2004-03-26

Family

ID=31986958

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030059429A Ceased KR20040025817A (ko) 2002-09-20 2003-08-27 반도체장치 및 그 제조방법

Country Status (5)

Country Link
US (1) US7245019B2 (https=)
JP (1) JP4373065B2 (https=)
KR (1) KR20040025817A (https=)
CN (1) CN100336198C (https=)
TW (1) TW200405515A (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7071097B2 (en) * 2004-07-09 2006-07-04 International Business Machines Corporation Method for improved process latitude by elongated via integration
JP4801333B2 (ja) * 2004-07-23 2011-10-26 パナソニック株式会社 電源配線構造および該電源配線構造を備えた半導体集積回路
US7332812B2 (en) * 2005-04-14 2008-02-19 Infineon Technologies Ag Memory card with connecting portions for connection to an adapter
JP4796817B2 (ja) * 2005-10-31 2011-10-19 エルピーダメモリ株式会社 基本セル設計方法、レイアウト設計方法、設計装置およびプログラム
US7685480B1 (en) * 2007-06-18 2010-03-23 Netlogic Microsystems, Inc. Content addressable memory having redundant row isolated noise circuit and method of use
JP2010003712A (ja) * 2007-08-09 2010-01-07 Renesas Technology Corp 半導体装置、半導体装置の配置配線方法、及びデータ処理システム
US7886240B2 (en) * 2008-01-29 2011-02-08 International Business Machines Corporation Modifying layout of IC based on function of interconnect and related circuit and design structure
JP2010187005A (ja) * 2010-03-30 2010-08-26 Fujitsu Semiconductor Ltd 複数の配線層を有する半導体回路の端子層設定に用いられる端子延長用コンポーネント
US8533641B2 (en) * 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions
US10020261B2 (en) * 2016-10-14 2018-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Split rail structures located in adjacent metal layers
US10964639B2 (en) 2017-10-20 2021-03-30 Samsung Electronics Co., Ltd. Integrated circuits including via array and methods of manufacturing the same
DE102020105474A1 (de) 2020-03-02 2021-09-02 Infineon Technologies Ag Integrierter Schaltkreis

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01186655A (ja) * 1988-01-14 1989-07-26 Fujitsu Ltd 半導体集積回路
JP3221383B2 (ja) 1997-12-17 2001-10-22 日本電気株式会社 半導体装置の多層配線構造
JP2000077634A (ja) * 1998-09-02 2000-03-14 Seiko Epson Corp 半導体装置
JP2001044196A (ja) 1999-07-30 2001-02-16 Fujitsu Ltd 半導体装置
JP3822009B2 (ja) * 1999-11-17 2006-09-13 株式会社東芝 自動設計方法、露光用マスクセット、半導体集積回路装置、半導体集積回路装置の製造方法、および自動設計プログラムを記録した記録媒体

Also Published As

Publication number Publication date
US20040056280A1 (en) 2004-03-25
JP2004111771A (ja) 2004-04-08
US7245019B2 (en) 2007-07-17
CN100336198C (zh) 2007-09-05
CN1487580A (zh) 2004-04-07
TW200405515A (en) 2004-04-01
JP4373065B2 (ja) 2009-11-25
TWI314351B (https=) 2009-09-01

Similar Documents

Publication Publication Date Title
US10002860B2 (en) Integrated circuit and standard cell library
KR100646298B1 (ko) 반도체 기억 장치 및 그 제조 방법
US6525350B1 (en) Semiconductor integrated circuit basic cell semiconductor integrated circuit using the same
US6307222B1 (en) Power/ground metallization routing in a semiconductor device
JP3461443B2 (ja) 半導体装置、半導体装置の設計方法、記録媒体および半導体装置の設計支援装置
JP3179800B2 (ja) 半導体集積回路装置
CN112786583B (zh) 包括集成标准单元结构的集成电路
KR102899035B1 (ko) 반도체 장치
US7476915B2 (en) Semiconductor integrated circuit including a first region and a second region
KR20040025817A (ko) 반도체장치 및 그 제조방법
JPH09162279A (ja) 半導体集積回路装置およびその製造方法
KR100384745B1 (ko) 반도체집적회로장치
JP3917683B2 (ja) 半導体集積回路装置
KR102912934B1 (ko) 반도체 장치, 반도체 장치의 레이아웃 디자인 방법 및 반도체 장치의 제조 방법
KR100306335B1 (ko) 반도체집적회로장치
JP2009272340A (ja) 半導体集積回路
KR102923643B1 (ko) 반도체 장치, 반도체 장치의 레이아웃 디자인 방법 및 반도체 장치의 제조 방법
CN114446945A (zh) 半导体装置
JP2000223575A (ja) 半導体装置の設計方法、半導体装置および半導体装置の製造方法
JP2006324485A (ja) 半導体集積回路並びにその設計方法および製造方法
EP1009031B1 (en) Semiconductor integrated circuit device and method of producing the same
JPH0250626B2 (https=)
JPH04306863A (ja) 半導体集積回路装置
JP2004086303A (ja) 半導体集積回路装置のレイアウト設計方法
KR19980042654A (ko) 반도체집적회로장치

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20030827

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20080821

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 20030827

Comment text: Patent Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20100721

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20101014

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20100721

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I