KR20040021731A - A pga package - Google Patents
A pga package Download PDFInfo
- Publication number
- KR20040021731A KR20040021731A KR1020020051336A KR20020051336A KR20040021731A KR 20040021731 A KR20040021731 A KR 20040021731A KR 1020020051336 A KR1020020051336 A KR 1020020051336A KR 20020051336 A KR20020051336 A KR 20020051336A KR 20040021731 A KR20040021731 A KR 20040021731A
- Authority
- KR
- South Korea
- Prior art keywords
- package
- semiconductor chip
- substrate
- bumps
- semiconductor
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로, 더욱 상세하게는 반도체 패키지의 크기를 축소화 할 수 있는 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly to a semiconductor package capable of reducing the size of the semiconductor package.
일반적으로 반도체 패키지라 함은 각종 전자 회로 및 배선이 적층되어 형성된 단일 소자 및 집적 회로 등의 반도체칩을 먼지, 습기, 전기적, 기계적 부하 등의 각종 외부 환경으로부터 보호하고 상기 반도체칩의 전기적 성능을 최적화, 극대화시키기 위해 리드프레임(Lead Frame)이나 인쇄회로기판(Printed Circuit Board)등을 이용해 메인보드(Main Board)로의 신호 입/출력 단자를 형성하고 봉지수단을 이용하여 몰딩(Molding)한 것을 말한다.In general, a semiconductor package is to protect a semiconductor chip such as a single device and an integrated circuit formed by stacking various electronic circuits and wirings from various external environments such as dust, moisture, electrical and mechanical loads, and to optimize the electrical performance of the semiconductor chip. In order to maximize, it means that a signal input / output terminal to a main board is formed using a lead frame or a printed circuit board, and molded using a sealing means.
이러한 반도체 패키지는 최근 반도체칩의 진보된 집적화 기술과 전자기기의 소형화에 따라서 이를 뒷받침하기 위해 경박단소(輕薄短少)화의 추세에 있으며, 이와 같은 반도체패키지는 실장방법에 따라 삽입형과 표면실장(Surface Mount Technology, SMT)형으로 분류하게 된다. 삽입형으로서 대표적인 것은 DIP(Dual In-Line Package), PGA(Pin Grid Array)등이 있고, 표면 실장형으로서 대표적인 것은 QFP(Quad Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic Leaded Chip Carrier), BGA(Ball GridArray) 등이 있다.These semiconductor packages are in the trend of light and thin in order to support them according to the recent integration technology of semiconductor chips and miniaturization of electronic devices, and such semiconductor packages are inserted and surface mounted according to the mounting method. Mount Technology, SMT). Representative insert types include DIP (Dual In-Line Package) and PGA (Pin Grid Array), and surface mount types include QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrier) and CLCC (Ceramic Leaded Chip Carrier). ) And Ball Grid Array (BGA).
이러한 반도체 패키지는 섭스트레이트(Substrate)로서 인쇄회로기판을 이용한 PGA 반도체 패키지, BGA 반도체 패키지와 리드프레임을 이용한 어레이형 반도체패키지로 분류할 수 있으며 이중에서도 리드프레임을 이용한 어레이형 반도체패키지의 구조를 첨부된 도1을 참조하여 설명하면 다음과 같다.Such a semiconductor package can be classified into a PGA semiconductor package using a printed circuit board, an array type semiconductor package using a BGA semiconductor package and a lead frame as a substrate, and the structure of the array type semiconductor package using a lead frame is attached. Referring to Figure 1 as follows.
도 1은 일반적인 피.지.에이 패키지를 보여주는 측면도로써, 반도체 칩(12)이 기판(14)의 상면위로 실장된 후, 금속 재질의 리드(16)가 씌워져 기판의 상면에서 반도체 칩(12)이 실장된 부분을 밀봉한 것을 기본적 구조로 한다.FIG. 1 is a side view illustrating a typical P.A package. After the semiconductor chip 12 is mounted on the top surface of the substrate 14, a metal lead 16 is covered to cover the semiconductor chip 12 on the top surface of the substrate. It is a basic structure that sealed this mounted part.
반도체 칩(12)은 범프(12a)를 아래 방향으로 한 상태에서 플럭스를 이용하여 실장되는 플립칩 기술이 적용되어 기판(14) 상면의 칩실장부 위에 실장되며, 반도체 칩과 기판의 상면 사이에는 밀봉부재(18)로 언더필 공정을 수행하여 범프(12a)들이 부착된 칩 실장부분을 밀봉한다. 반도체 칩의 범프(12a)들은 핀(20)들과 대응되어 전기적으로 연결되어 있다.The semiconductor chip 12 is mounted on the chip mounting portion of the upper surface of the substrate 14 by applying a flip chip technology in which the bump 12a is mounted using the flux with the bump 12a in the downward direction, and between the semiconductor chip and the upper surface of the substrate. The underfill process is performed with the sealing member 18 to seal the chip mounting portion to which the bumps 12a are attached. The bumps 12a of the semiconductor chip are electrically connected to the pins 20.
이러한 구조의 패키지에 따르면, 패키지(10)의 크기는 칩(12)의 크기와 핀(20)의 개수에 의해 정해진다. 칩이 대용량화되어 감에 따라 칩의 크기가 증가하고, 핀(20)의 개수가 증가함과 동시에 패키지 크기가 증가하게 된다. 이러한 패키기 크기의 증가는 패키지개발 비용의 증가는 물론 시스템 전체 크기의 증가를 초래하게 된다.According to the package of this structure, the size of the package 10 is determined by the size of the chip 12 and the number of pins (20). As the chip becomes larger, the size of the chip increases, the number of the pins 20 increases, and the package size increases. This increase in package size not only increases the cost of package development but also increases the overall size of the system.
본 발명은 이와 같은 종래의 문제점을 해결하기 위한 것으로, 그 목적은 단자핀의 구조 개선을 통해 패키지의 크기를 획기적으로 줄일 수 있도록 하는데 그 목적이 있다.The present invention is to solve such a conventional problem, the object of the present invention is to significantly reduce the size of the package by improving the structure of the terminal pin.
도 1은 일반적인 피지에이 패키지의 구성을 보여주는 단면도;1 is a cross-sectional view showing the configuration of a typical Fiji package;
도 2는 본 발명의 바람직한 실시예에 따른 피지에이 패키지의 단면도이다.2 is a cross-sectional view of a Fiji package according to a preferred embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
110 : 반도체 칩110: semiconductor chip
120 : 제1기판120: first substrate
130 : 제2기판130: second substrate
상술한 목적을 달성하기 위한 본 발명의 특징에 의하면, 피지에이 패키지는 범프들이 구비된 반도체 칩; 상기 반도체 칩이 상기 범프를 통하여 실장되는 상면과 상기 범프와 전기적으로 연결되는 핀들이 수직으로 돌출된 하면을 포함하는 제1기판; 상기 반도체 칩이 상기 범프를 통하여 실장되는 하면과, 상기 범프와 전기적으로 연결되는 핀들이 수직으로 돌출된 상면을 포함하는 제2기판을 갖는다.According to a feature of the present invention for achieving the above object, the Fiji package includes a semiconductor chip having bumps; A first substrate including an upper surface on which the semiconductor chip is mounted through the bumps and a lower surface on which pins electrically connected to the bumps protrude vertically; The semiconductor substrate has a second substrate including a lower surface on which the semiconductor chip is mounted through the bumps and an upper surface on which pins electrically connected to the bumps protrude vertically.
이하, 첨부된 도면 도 2를 참조하면서 본 발명의 실시예를 보다 상세히 설명한다. 상기 도면들에 있어서 동일한 기능을 수행하는 구성요소에 대해서는 동일한 참조 번호가 병기되어 있다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are given to components that perform the same function.
도 2는 본 발명의 실시예에 따른 피지에이 패키지의 외관을 보여주는 도면이다.2 is a view showing the appearance of a Fiji package according to an embodiment of the present invention.
도 2를 참고하면, 피지에이 패키지(100)는 반도체 칩(110), 제1기판(120) 그리고 제2기판(130)으로 이루어진다. 상기 반도체 칩(110)은 다수의 범프(112)들이 상면과 하면에 형성된다.Referring to FIG. 2, the Fiji A package 100 includes a semiconductor chip 110, a first substrate 120, and a second substrate 130. The semiconductor chip 110 has a plurality of bumps 112 formed on an upper surface and a lower surface thereof.
상기 제1기판(120)은 상기 반도체 칩(110)이 상기 범프(112)를 통하여 실장되는 칩 실장부를 갖는 상면(122)과, 상기 범프(112)와 전기적으로 연결되는 핀(124)들이 수직으로 돌출된 하면(126)을 갖는다. 상기 제2기판(130)은 상기 반도체 칩(110)이 상기 범프(112)를 통하여 실장되는 칩 실장부를 갖는 하면(132)과, 상기 범프(112)와 전기적으로 연결되는 핀(134)들이 수직으로 돌출된 상면(136)을 갖는다.The first substrate 120 has an upper surface 122 having a chip mounting portion on which the semiconductor chip 110 is mounted through the bump 112, and pins 124 electrically connected to the bump 112 are vertical. Has a bottom surface 126 protruded. The second substrate 130 has a lower surface 132 having a chip mounting portion in which the semiconductor chip 110 is mounted through the bump 112, and pins 134 electrically connected to the bump 112 are vertical. It has a top surface 136 protruded.
이처럼, 본 발명의 바람직한 실시예에 따른 피지에이 패키지(100)는 일면에 칩 실장부(chip mount area)가 형성되고, 그 반대면에 격자형태의 외부접속용 핀(124,134 ; pin)들이 돌출되어 형성된 기판(120,130)들에 반도체 칩(110)이 플립 본딩(Flip bonding)된다.As such, in the Fiji A package 100 according to the preferred embodiment of the present invention, a chip mount area is formed on one surface, and pins 124 and 134 for external connection in a lattice form protrude on the opposite surface. The semiconductor chip 110 is flip bonded to the formed substrates 120 and 130.
이처럼, 본 발명의 피지에이 패키지는 기판이 반도체 칩의 양면으로 설치됨으로, 전체적인 사이즈를 감소시킬 수 있고, 재료비 절감으로 인한 원가 감소를 얻을 수 있다.As such, in the Fiji package of the present invention, since the substrate is installed on both sides of the semiconductor chip, the overall size can be reduced, and the cost can be reduced due to the material cost reduction.
여기서 본 발명의 구조적인 특징은 반도체 칩의 양면으로 기판이 연결되는데 있다.The structural feature of the present invention is that the substrate is connected to both sides of the semiconductor chip.
이상에서, 본 발명에 따른 피지에이 패키지의 구성 및 작용을 상기한 설명및 도면에 따라 도시하였지만 이는 예를 들어 설명한 것에 불과하며 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 다양한 변화 및 변경이 가능함은 물론이다.In the above, the configuration and operation of the Fiji A package according to the present invention is shown in accordance with the above description and drawings, but this is merely described for example, and various changes and modifications are possible within the scope without departing from the spirit of the present invention. Of course.
이와 같은 본 발명의 피지에이 패키지에 의하면, 패키지의 크기를 획기적으로 축소시킬 수 있는 효과가 있다.According to the Fiji package of the present invention as described above, there is an effect that can significantly reduce the size of the package.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020051336A KR20040021731A (en) | 2002-08-29 | 2002-08-29 | A pga package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020051336A KR20040021731A (en) | 2002-08-29 | 2002-08-29 | A pga package |
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| Publication Number | Publication Date |
|---|---|
| KR20040021731A true KR20040021731A (en) | 2004-03-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020051336A KR20040021731A (en) | 2002-08-29 | 2002-08-29 | A pga package |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200449796Y1 (en) * | 2008-04-08 | 2010-08-11 | 김석헌 | A hole-cup used for golf putting |
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2002
- 2002-08-29 KR KR1020020051336A patent/KR20040021731A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200449796Y1 (en) * | 2008-04-08 | 2010-08-11 | 김석헌 | A hole-cup used for golf putting |
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