KR20040011255A - Method for forming gate oxide layer of semiconductor device - Google Patents
Method for forming gate oxide layer of semiconductor device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000010408 film Substances 0.000 claims abstract description 133
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 54
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 54
- 239000010703 silicon Substances 0.000 claims abstract description 54
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 25
- 239000010409 thin film Substances 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 6
- -1 nitrogen ions Chemical class 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract 1
- 229910001882 dioxygen Inorganic materials 0.000 abstract 1
- 238000004140 cleaning Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
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Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 초박막 게이트산화막을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an ultra-thin gate oxide film.
최근 반도체 소자의 고집적화 및 복잡화 추세와 함께 저 전력소모 및 고신뢰성이 요구되고 있다. 이러한 요구를 충족시키기 위해 단채널효과(short channel effect)를 억제하고 출력 전류를 향상시키면서 게이트산화막의 두께를 줄여나가는 방향으로 연구가 진행되고 있으며, 이와 동시에 반도체 소자의 동작 전압을 낮출 필요가 있다.Recently, with the trend of high integration and complexity of semiconductor devices, low power consumption and high reliability are required. In order to meet such demands, research is being conducted toward reducing the thickness of the gate oxide film while suppressing short channel effects and improving output current, and at the same time, it is necessary to lower the operating voltage of the semiconductor device.
게이트산화막은 일반적으로 로 내에서 열산화화하여 형성하고 있는데 이러한 로를 이용한 열산화법에서는 20Å 정도 두께의 게이트산화막을 형성하는 데 소요되는 시간이 수 분 이내로 짧기 때문에 20Å 이하의 두께를 재현성있게 형성하는 것이 불가능하다. 따라서, 20Å 이하의 초박막 게이트산화막을 형성하기 위해서는 진공 상태나 저압 상태에서 열산화가 이루어지도록 기존의 로를 개조하거나 또는 급속열처리(RTA:rapid thermal annealing) 장비를 이용하여야 하나, 이러한 로의 개조 또는 RTA 장비를 이용하면 공정 비용이 많이 드는 문제점이 있다.The gate oxide film is generally formed by thermal oxidation in a furnace. In the thermal oxidation method using the furnace, since the time required to form a gate oxide film having a thickness of about 20 ms is short within several minutes, a thickness of 20 dB or less is reproducibly formed. It is impossible. Therefore, in order to form an ultra-thin gate oxide film of 20 kV or less, an existing furnace must be retrofitted or a rapid thermal annealing (RTA) device can be used to perform thermal oxidation in a vacuum or low pressure state. The use of equipment has the problem of high process costs.
그러면, 종래 반도체 소자의 게이트산화막 형성 방법에 대해 간략히 설명한다. 도 1a 내지 도 1d는 종래 반도체 소자의 게이트산화막 형성 방법을 도시한 단면도이다.Next, a method of forming a gate oxide film of a conventional semiconductor device will be briefly described. 1A to 1D are cross-sectional views illustrating a gate oxide film forming method of a conventional semiconductor device.
먼저, 도 1a에 도시한 바와 같이, 실리콘웨이퍼(1)의 소정영역에 로코스 공정이나 트렌치 공정으로 형성된 필드 산화막(2)에 의해 액티브 영역이 정의된 실리콘웨이퍼를 산소분위기의 로 내에서 열산화하여 실리콘웨이퍼(1)의 액티브 영역에 제1게이트산화막(3a,3b)을 형성한다.First, as shown in FIG. 1A, a silicon wafer in which an active region is defined by a field oxide film 2 formed in a predetermined region of a silicon wafer 1 by a LOCOS process or a trench process is thermally oxidized in a furnace of an oxygen atmosphere. The first gate oxide films 3a and 3b are formed in the active region of the silicon wafer 1.
이 때 필드 산화막(22)을 경계로 하여 이웃하는 두 액티브 영역을 각각 제1액티브 영역(100) 및 제2액티브 영역(200)이라 할 때, 제1 및 제2액티브 영역에는 각각 동작전압이 서로 다른 소자를 형성하고 따라서 게이트산화막 역시 제1 및 제2액티브 영역에서 서로 다른 두께로 형성하기로 한다.In this case, when the two active regions adjacent to the field oxide film 22 as the boundaries are referred to as the first active region 100 and the second active region 200, respectively, the operating voltages are different from each other in the first and second active regions. Different devices are formed and therefore gate oxide films are also formed in different thicknesses in the first and second active regions.
설명의 편의상 제1액티브 영역(100)에 형성된 제1게이트산화막을 3a라 칭하고, 제2액티브 영역(200)에 형성된 제1게이트산화막을 3b라 칭한다.For convenience of description, the first gate oxide film formed on the first active region 100 is referred to as 3a, and the first gate oxide film formed on the second active region 200 is referred to as 3b.
다음, 제2액티브 영역(200)에는 제1게이트산화막(3a)보다 두께가 더 얇은 제2게이트산화막(3b)을 형성하기 위해, 도 1b에 도시된 바와 같이, 제2액티브 영역(200)을 노출시키는 감광막 패턴(4)을 제1액티브 영역(100)의 제1게이트산화막(3a) 상에 형성한다.Next, to form a second gate oxide film 3b thinner than the first gate oxide film 3a in the second active region 200, as shown in FIG. 1B, the second active region 200 is formed. An exposed photosensitive film pattern 4 is formed on the first gate oxide film 3a of the first active region 100.
다음, 도 1c에 도시된 바와 같이, 감광막 패턴(4)을 마스크로 하여 노출된 제2액티브 영역(200)의 제1게이트산화막(3b)을 식각하고, 감광막 패턴(4)을 제거한 후 세정공정을 수행한다. 그런데, 세정공정이 진행되는 동안 공기 중에 노출된 제2액티브 영역(200)의 실리콘웨이퍼 표면에는 자연산화막(5)이 10Å 정도의 두께로 형성되며, 이러한 자연산화막은 의도한 것이 아니라 자연적으로 성장하는 것으로서 그 두께를 제어하는 것이 불가능하다.Next, as illustrated in FIG. 1C, the first gate oxide film 3b of the exposed second active region 200 is etched using the photoresist pattern 4 as a mask, and the photoresist pattern 4 is removed, followed by a cleaning process. Do this. However, during the cleaning process, a natural oxide film 5 is formed on the surface of the silicon wafer of the second active region 200 exposed in the air to a thickness of about 10Å, and the natural oxide film is not intended but grows naturally. It is impossible to control the thickness thereof.
다음, 도 1d에 도시된 바와 같이, 실리콘웨이퍼(1)를 산소 분위기의 로 내에서 열산화하여 제2액티브 영역(200)의 자연산화막(5) 상에 제2게이트산화막(6)을 10~20Å 정도로 얇게 성장시키며, 이 때 제1액티브 영역(100)의 제1게이트산화막(3a)도 함께 성장된다.Next, as illustrated in FIG. 1D, the silicon wafer 1 is thermally oxidized in a furnace of an oxygen atmosphere to form the second gate oxide film 6 on the natural oxide film 5 of the second active region 200. The first gate oxide layer 3a of the first active region 100 is also grown at the same time.
그러나, 상술한 바와 같이 일반적인 열산화막법으로 20Å 이하 두께의 게이트산화막을 재현성있게 형성하는 것이 불가능하며, 또한 제어불가능한 자연산화막이 10Å 정도의 두께로 이미 형성되어 있기 때문에 20Å 이하의 초박막 게이트산화막을 재현성있게 형성하는 것은 불가능한 문제점이 있었다.However, as described above, it is impossible to form a gate oxide film having a thickness of 20 kPa or less by a general thermal oxidation method, and since an uncontrollable natural oxide film is already formed to a thickness of about 10 kPa, an ultra-thin gate oxide film of 20 kPa or less is reproducible. There was a problem that was impossible to form.
또한, 게이트산화막의 두께가 점점 얇아지면서 게이트산화막의 총 두께에서 자연산화막이 차지하는 비율이 점점 높아지기 때문에, 자연산화막의 두께를 최소화할 필요가 있다.In addition, as the thickness of the gate oxide film becomes thinner and thinner, the ratio of the natural oxide film to the total thickness of the gate oxide film is gradually increased. Therefore, it is necessary to minimize the thickness of the natural oxide film.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 장비의 개조 없이 기존의 로를 이용하여 20Å 이하의 초박막 게이트산화막을 재현성 있게 형성하는 데 있다.The present invention is to solve the problems as described above, the object is to reproducibly form an ultra-thin gate oxide film of 20 Å or less using an existing furnace without modification of the equipment.
도 1a 내지 도 1d는 종래 게이트산화막 형성 방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a conventional method for forming a gate oxide film.
도 2a 내지 2c는 본 발명의 제1실시예에 따른 게이트산화막 형성 방법을 도시한 단면도이다.2A through 2C are cross-sectional views illustrating a method of forming a gate oxide film according to a first embodiment of the present invention.
도 3a 내지 3d는 본 발명의 제2실시예에 따른 게이트산화막 형성을 도시한 단면도이다.3A through 3D are cross-sectional views illustrating gate oxide film formation in accordance with a second embodiment of the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 초박막 게이트산화막을 형성하고자 하는 실리콘웨이퍼 상에 질소가 함유된 산화막을 형성하거나, 또는 질소 이온을 주입하여 실리콘웨이퍼 내에 질소가 존재하도록 한 다음, 그 위에 열산화법으로 게이트산화막을 형성하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, an oxide film containing nitrogen is formed on a silicon wafer to form an ultra-thin gate oxide film, or nitrogen ions are injected to allow nitrogen to exist in the silicon wafer. A gate oxide film is formed on the thermal oxidation method.
이 때 실리콘웨이퍼 내에 존재하는 질소는 게이트산화막의 성장률을 저하시키는 역할을 하기 때문에 자연산화막 및 게이트산화막의 두께를 조절하여 20Å 이하의 초박막 게이트산화막을 재현성있게 형성하는 것이 가능해진다.At this time, since the nitrogen present in the silicon wafer serves to decrease the growth rate of the gate oxide film, it is possible to reproducibly form an ultra-thin gate oxide film of 20 kV or less by controlling the thickness of the natural oxide film and the gate oxide film.
즉, 본 발명에 따른 반도체 소자의 게이트산화막 형성방법은, 실리콘웨이퍼 상에 질소가 함유된 희생산화막을 형성하는 단계; 희생산화막을 식각하여 실리콘웨이퍼를 노출시키는 단계; 실리콘웨이퍼를 산소분위기의 로 내에서 열산화하여 노출된 실리콘웨이퍼 상에 게이트산화막을 형성하는 단계를 포함하는 이루어진다.That is, the method for forming a gate oxide film of a semiconductor device according to the present invention includes forming a sacrificial oxide film containing nitrogen on a silicon wafer; Etching the sacrificial oxide film to expose the silicon wafer; And thermally oxidizing the silicon wafer in a furnace of an oxygen atmosphere to form a gate oxide film on the exposed silicon wafer.
또는, 필드 산화막에 의해 소자 분리 영역 및 액티브 영역이 정의되고, 액티브 영역이 후막영역과 박막영역으로 구분된 실리콘웨이퍼에서, 후막영역 및 박막영역의 실리콘웨이퍼 상에 질소가 포함된 제1게이트산화막을 형성하는 단계; 박막영역의 실리콘웨이퍼 상에 형성된 제1게이트산화막을 식각하여 박막영역의 실리콘웨이퍼를 노출시키는 단계; 실리콘웨이퍼를 산소분위기의 로 내에서 열산화하여 노출된 박막영역의 실리콘웨이퍼 상에 제1게이트산화막보다 얇은 두께로 제2게이트산화막을 형성하는 단계를 포함하여 이루어진다.Alternatively, in a silicon wafer in which a device isolation region and an active region are defined by a field oxide film, and the active region is divided into a thick film region and a thin film region, a first gate oxide film containing nitrogen is formed on the silicon wafer of the thick film region and the thin film region. Forming; Etching the first gate oxide film formed on the silicon wafer in the thin film region to expose the silicon wafer in the thin film region; And thermally oxidizing the silicon wafer in the furnace of the oxygen atmosphere to form a second gate oxide film on the exposed silicon wafer in a thinner region than the first gate oxide film.
이하, 본 발명에 따른 게이트산화막 형성 방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a gate oxide film according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 2c는 본 발명의 제1실시예에 따른 게이트산화막 형성 방법을 도시한 단면도이다.2A through 2C are cross-sectional views illustrating a method of forming a gate oxide film according to a first embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 실리콘웨이퍼(11)를 NO 가스 또는 N2O 가스 분위기의 로 내에서 열처리하여 실리콘웨이퍼(11) 표면에 희생 산화막으로서 질소가 함유된 산화막(이하 NO막 이라 칭한다)(13)을 형성한다. 이 때 열처리는 800~950℃의 온도에서 1시간 이내의 시간동안 수행하는 것이 바람직하며, 더욱 바람직하게는 5~45분 동안 수행한다.First, as shown in FIG. 2A, the silicon wafer 11 is heat-treated in a furnace in an NO gas or N 2 O gas atmosphere, and an oxide film containing nitrogen as a sacrificial oxide film on the surface of the silicon wafer 11 (hereinafter referred to as NO film). 13). At this time, the heat treatment is preferably performed for a time within 1 hour at a temperature of 800 ~ 950 ℃, more preferably 5 to 45 minutes.
다음, 도 2b에 도시된 바와 같이 NO막(13)을 식각하여 제거하는데, 이 때 NO막(13)으로부터 실리콘웨이퍼(11) 내로 침투한 질소는 NO막(13)의 제거 후에도 잔류한다. 설명의 편의상 도 2b에서 질소를 N으로 표시하여 도시한다.Next, as illustrated in FIG. 2B, the NO film 13 is etched and removed. At this time, nitrogen that has penetrated into the silicon wafer 11 from the NO film 13 remains after removal of the NO film 13. For convenience of explanation, nitrogen is shown as N in FIG. 2B.
다음, 도 2c에 도시된 바와 같이, 실리콘웨이퍼(11)를 산소 분위기에서 열산화하여 노출된 실리콘웨이퍼(11) 표면에 게이트산화막(16)을 얇게 성장시킨다. 이러한 게이트산화막(16)의 성장 시 잔류 질소가 산화막의 성장률을 저하시키기 때문에 동일한 두께의 산화막을 성장시키는 데 소요되는 공정시간이 잔류 질소가 없는 종래에 비해 길어진다. 따라서, 게이트산화막(16)을 원하는 두께로 얇게, 일예로 15Å 정도의 두께로 재현성있게 성장시키는 것이 용이해진다.Next, as shown in FIG. 2C, the silicon oxide 11 is thermally oxidized in an oxygen atmosphere to grow the gate oxide layer 16 thinly on the exposed silicon wafer 11 surface. Since the residual nitrogen decreases the growth rate of the oxide film during the growth of the gate oxide film 16, the process time required to grow the oxide film having the same thickness is longer than in the prior art without residual nitrogen. Therefore, it becomes easy to grow the gate oxide film 16 thinly to a desired thickness and reproducibly to a thickness of about 15 microseconds, for example.
다음으로, 도 3a 내지 3d는 본 발명의 제2실시예에 따른 게이트산화막 형성을 도시한 단면도이다.3A to 3D are cross-sectional views illustrating the formation of a gate oxide film according to the second embodiment of the present invention.
최근 소형화 및 복잡화된 반도체 소자의 동작전압을 더욱 낮추다보니 서로 다른 두 동작전압에 함께 동작하는 소자가 요구되기도 하고, 동작전압이 서로 다른 두 소자가 하나의 칩 내에 공존하기도 한다. 후자의 경우 하나의 칩을 저전압영역과 고전압영역으로 구분하고, 각각의 영역에 게이트산화막의 두께를 서로 다르게, 즉 저전압영역에서는 게이트산화막의 두께를 얇게, 고전안영역에서는 게이트산화막의 두께를 두껍게 형성한다.Recently, as the operation voltage of a miniaturized and complicated semiconductor device is further lowered, devices that operate together at two different operating voltages are required, and two devices having different operating voltages coexist in one chip. In the latter case, one chip is divided into a low voltage region and a high voltage region, and the thickness of the gate oxide is different in each region, that is, the thickness of the gate oxide is thin in the low voltage region and thick in the high eye region. do.
본 발명의 제2실시예에서는 인접하는 두 액티브 영역에 게이트산화막을 서로 다른 두께로 형성한다.In the second embodiment of the present invention, gate oxide films are formed in two adjacent active regions with different thicknesses.
먼저, 도 3a에 도시한 바와 같이, 실리콘웨이퍼(21)의 소정영역에 로코스 공정이나 트렌치 공정으로 필드 산화막(22)을 형성하여, 실리콘웨이퍼(21)에서 필드 산화막이 형성된 부분을 소자 분리 영역으로, 그 외의 부분을 액티브 영역으로 정의한다.First, as shown in FIG. 3A, the field oxide film 22 is formed in a predetermined region of the silicon wafer 21 by a LOCOS process or a trench process, so that the portion where the field oxide film is formed in the silicon wafer 21 is formed in an element isolation region. The other part is defined as an active area.
이 때 필드 산화막(22)을 경계로 하여 이웃하는 두 액티브 영역을 각각 제1액티브 영역(100) 및 제2액티브 영역(200)이라 할 때, 제1 및 제2액티브 영역에는 각각 동작전압이 서로 다른 소자를 형성하고 따라서 게이트산화막 역시 제1 및 제2액티브 영역에서 서로 다른 두께로 형성하기로 한다.In this case, when the two active regions adjacent to the field oxide film 22 as the boundaries are referred to as the first active region 100 and the second active region 200, respectively, the operating voltages are different from each other in the first and second active regions. Different devices are formed and therefore gate oxide films are also formed in different thicknesses in the first and second active regions.
다음, NO 가스 또는 N2O 가스 분위기의 로 내에서 실리콘웨이퍼(21)를 열처리하여 실리콘웨이퍼(21) 상에 제1게이트산화막으로서 질소가 함유된 산화막(이하 NO막 이라 칭한다)(23a,23b)을 형성한다. 이 때, 열처리는 800~950℃의 온도에서 1시간 이내의 시간동안 수행하는 것이 바람직하며, 더욱 바람직하게는 5~45분 동안 수행한다.Next, the silicon wafer 21 is heat-treated in a furnace in an NO gas or N 2 O gas atmosphere, and oxide films containing nitrogen as a first gate oxide film on the silicon wafer 21 (hereinafter referred to as NO films) 23a and 23b. ). At this time, the heat treatment is preferably performed for a time within 1 hour at a temperature of 800 ~ 950 ℃, more preferably for 5 to 45 minutes.
설명의 편의상 제1액티브 영역(100)에 형성된 NO막을 23a라 칭하고, 제2액티브 영역(200)에 형성된 NO막을 23b라 칭한다.For convenience of explanation, the NO film formed in the first active region 100 is referred to as 23a, and the NO film formed in the second active region 200 is referred to as 23b.
다음, 제2액티브 영역(200)에는 제1게이트산화막인 NO막(23a)보다 두께가 더 얇은 제2게이트산화막을 형성하기 위해, 도 3b에 도시된 바와 같이, 제2액티브 영역(200)을 노출시키는 감광막 패턴(24)을 제1액티브 영역(100)의 NO막(23a) 상에 형성한다.Next, in order to form a second gate oxide film having a thickness thinner than that of the NO film 23a which is the first gate oxide film, the second active region 200 is formed in the second active region 200, as shown in FIG. 3B. An exposed photosensitive film pattern 24 is formed on the NO film 23a of the first active region 100.
다음, 도 3c에 도시된 바와 같이, 감광막 패턴(24)을 마스크로 하여 노출된 제2액티브 영역(200)의 NO막(23b)을 식각하고, 감광막 패턴(24)을 제거한 후 세정공정을 수행한다. 그런데, 세정공정이 진행되는 동안 공기 중에 노출된 제2액티브 영역(200)의 실리콘웨이퍼 표면에는 자연산화막(25)이 형성되기는 하나, 제1게이트산화막으로서 일반적인 열산화막인 실리콘산화막을 형성하는 종래의 경우에 비해 자연산화막(25)의 두께가 훨씬 얇게 형성된다.Next, as shown in FIG. 3C, the NO film 23b of the exposed second active region 200 is etched using the photoresist pattern 24 as a mask, the photoresist pattern 24 is removed, and a cleaning process is performed. do. However, although the natural oxide film 25 is formed on the surface of the silicon wafer of the second active region 200 exposed to the air during the cleaning process, a conventional oxide oxide silicon oxide film is formed as a first gate oxide film. Compared to the case, the thickness of the natural oxide film 25 is much thinner.
이는, 본 발명에서와 같이 제1게이트산화막으로서 NO막을 형성할 경우, NO막으로부터 질소가 기판 내로 침투되어 제2액티브 영역(200) 상의 NO막(13b)을 제거한 후에도 기판 내에 질소가 잔류하는데, 이러한 잔류 질소가 자연산화막의 성장률을 저하시키기 때문이다.This is because when the NO film is formed as the first gate oxide film as in the present invention, nitrogen penetrates into the substrate from the NO film and nitrogen remains in the substrate even after the NO film 13b on the second active region 200 is removed. This is because such residual nitrogen lowers the growth rate of the natural oxide film.
다음, 도 3d에 도시된 바와 같이, 실리콘웨이퍼(21)를 산소 분위기에서 열산화하여 제2액티브 영역(200) 표면에 제2게이트산화막(26)을 얇게 성장시키며, 이 때 제1액티브 영역(100)의 NO막(23a)도 함께 성장된다. 제2게이트산화막(26)의 성장 시에도 잔류 질소가 산화막의 성장률을 저하시키기 때문에 동일한 두께의 산화막을 성장시키는 데 소요되는 공정시간이 잔류 질소가 없는 종래에 비해 길어진다. 따라서, 제2게이트산화막(26)을 원하는 두께로 얇게, 일예로 15Å 정도의 두께로 재현성있게 성장시키는 것이 용이해진다.Next, as illustrated in FIG. 3D, the silicon wafer 21 is thermally oxidized in an oxygen atmosphere to grow the second gate oxide layer 26 thinly on the surface of the second active region 200, and at this time, the first active region ( The NO film 23a of 100 is also grown together. Even when the second gate oxide film 26 is grown, the process time required to grow an oxide film having the same thickness is longer than in the conventional case in which residual nitrogen reduces the growth rate of the oxide film. Therefore, it becomes easy to grow the second gate oxide film 26 thinly to a desired thickness, for example, to a thickness of about 15 kPa.
한편, 상술한 바와 같은 제1 및 제2실시예에서, NO막을 형성하는 대신에 실리콘웨이퍼에 질소 이온을 주입할 수도 있다. 질소 이온을 주입하는 경우, 얇은 게이트산화막을 형성하고자 하는 영역의 실리콘웨이퍼에 20~30 keV의 에너지로 2.0×1014~ 5.0×1015개/cm2의 양을 주입하는 것이 바람직하다.Meanwhile, in the first and second embodiments as described above, instead of forming the NO film, nitrogen ions may be implanted into the silicon wafer. In the case of implanting nitrogen ions, it is preferable to inject 2.0 × 10 14 to 5.0 × 10 15 pieces / cm 2 into the silicon wafer in the region where the thin gate oxide film is to be formed with an energy of 20 to 30 keV.
상술한 바와 같이, 본 발명에서는 실리콘웨이퍼에 NO막을 형성하거나 또는 질소이온을 주입하는 방법에 의해 실리콘웨이퍼에 질소가 존재하도록 하여, 실리콘웨이퍼에 열산화법으로 게이트산화막을 형성할 때 질소의 작용으로 게이트산화막의 성장속도를 저하시키고 공정시간을 지연시키며, 이로 인해 두께가 20Å 이하인 초박막 게이트산화막을 재현성 있게 형성하는 효과가 있다.As described above, in the present invention, nitrogen is present in the silicon wafer by forming a NO film on the silicon wafer or injecting nitrogen ions, so that a gate oxide film is formed on the silicon wafer by a thermal oxidation method. The growth rate of the oxide film is lowered and the process time is delayed. Thus, there is an effect of reproducibly forming an ultra-thin gate oxide film having a thickness of 20 μs or less.
또한, 본 발명에서는 게이트산화막 형성을 위해 장비를 개조할 필요가 없으며 기존의 로를 그대로 이용하여 초박막 게이트산화막을 재현성 있게 형성하기 때문에, 공정비용이 저렴한 효과가 있다.In addition, in the present invention, there is no need to modify equipment to form the gate oxide film, and since the ultra thin gate oxide film is reproducibly formed using the existing furnace as it is, the process cost is low.
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