KR20050002008A - Method for fabricating dual gate oxide using two-step oxidation process - Google Patents

Method for fabricating dual gate oxide using two-step oxidation process Download PDF

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KR20050002008A
KR20050002008A KR1020030043054A KR20030043054A KR20050002008A KR 20050002008 A KR20050002008 A KR 20050002008A KR 1020030043054 A KR1020030043054 A KR 1020030043054A KR 20030043054 A KR20030043054 A KR 20030043054A KR 20050002008 A KR20050002008 A KR 20050002008A
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South Korea
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oxide film
gate oxide
oxidation process
dual gate
annealing
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KR1020030043054A
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Korean (ko)
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조흥재
임관용
장세억
김용수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

PURPOSE: A method for forming a dual gate oxide layer by a two-step oxide process is provided to fabricate a reliable SOC(system on a chip) by performing an annealing process at a predetermined temperature after nitrogen ions are implanted and by performing a two-step process of oxidation and annealing in an oxide process. CONSTITUTION: A sacrificial oxide layer(3) is formed on a silicon substrate. A mask process is performed to expose a predetermined part of the silicon substrate. Nitrogen ions of predetermined energy and dose are implanted into the substrate. An annealing process(6) is performed at a predetermined temperature in an inert atmosphere to gather the nitrogen ions implanted into the substrate around the surface of the substrate. The sacrificial oxide layer is eliminated. A two-step oxide process is performed to simultaneously form gate oxide layers with different thickness.

Description

2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법{Method for fabricating dual gate oxide using two-step oxidation process}Method for fabricating dual gate oxide using two-step oxidation process

본 발명은 한 칩내에 다양한 소자를 갖는 SOC(system on a chip)을 구현하기 위하여 질소 이온주입(nitrogen implant)방법에 의한 다중 게이트산화막 형성시 일정한 N 주입량(Dose)에서 이온주입되지 않는 영역과의 두께 차이를 증가시키기 위한 방법에 관한 것이다.The present invention provides a system on a chip (SOC) having a variety of devices in one chip. The present invention relates to a region in which a plurality of gate oxides are not implanted at a constant N implantation rate when forming a multi-gate oxide film by a nitrogen implant method. A method for increasing the thickness difference.

최근에는 여러가지 목적에 맞는 소자들을 한 칩내에 형성한 SOC(system on a chip)에 대한 연구가 많이 이루어지고 있다. 이러한 SOC에서는 각 소자의 동작전압이 다른데, 이를 위해서 서로 상이한 두께를 갖는 게이트산화막을 형성하는 것이 반드시 필요하다. 즉, 높은 전압이 걸리는 소자에는 신뢰성 향상을 위해 두꺼운 게이트산화막이 필요하고, 소자의 동작속도가 중요한 소자에는 얇은 게이트산화막이 필요하다. 이러한 요구조건에 의해 개발된 것이 듀얼 게이트산화막 또는 다중 게이트산화막 공정으로, 한 칩내에 두꺼운 게이트산화막 영역 및 얇은 게이트산화막 영역을 형성할 수 있는 방법이다. 이러한 듀얼 게이트산화막 또는 다중 게이트산화막을 형성하기 위한 방법중 하나는 질소를 실리콘기판에 이온주입하는 것으로, 질소가 이온주입된 영역의 산화속도가 감소되어 서로 다른 두께를 한 칩에서 구현할 수 있게 된다.Recently, many researches have been conducted on a system on a chip (SOC) in which devices for various purposes are formed in one chip. In such SOC, the operating voltages of the devices are different. For this purpose, it is necessary to form gate oxide films having different thicknesses. That is, a device having a high voltage requires a thick gate oxide film to improve reliability, and a device having a high operation speed requires a thin gate oxide film. Developed by these requirements, a dual gate oxide film or a multi gate oxide film process is a method of forming a thick gate oxide film region and a thin gate oxide film region in one chip. One of the methods for forming the dual gate oxide film or the multi-gate oxide film is ion implantation of nitrogen into a silicon substrate, and the oxidation rate of the region where nitrogen is ion implanted is reduced, so that different thicknesses can be realized in one chip.

그러나 질소 이온주입방법의 단점은 일정한 N의 주입량(Dose)에서 산화속도를 감소시키는데 한계가 있다는 것이다. 종래기술을 도시한 도1을 살펴 보면, N의주입량이 3E14cm-2일때 기존의 1단계 산화방법으로는 약 5Å 정도의 델타(Delta)두께 밖에 벌어지지 않음을 알 수 있다. 이러한 델타 두께를 증가시키기 위해서 N의 주입량을 증가시킬 수도 있지만, N의 주입량이 3E14cm-2이상일때는 게이트산화막의 신뢰성이 급격히 떨어지기 때문에 적용이 불가능하다.However, the disadvantage of the nitrogen ion implantation method is that there is a limit in reducing the oxidation rate at a constant N dose. Looking at Figure 1 showing the prior art, it can be seen that when the injection amount of N is 3E14cm -2, only a delta thickness of about 5 mV occurs by the conventional one-stage oxidation method. In order to increase the delta thickness, the injection amount of N may be increased. However, when the injection amount of N is more than 3E14 cm −2 , the application of the gate oxide film is rapidly deteriorated.

본 발명은 상기 문제점을 해결하기 위한 것으로써, 질소 이온주입방법으로 다중 게이트산화막을 형성할때 일정한 N 주입량에서도 델타 두께를 효과적으로 증가시키기 위하여 질소 이온주입후에 일정 온도에서 어닐링을 진행하고 산화공정시 2단계로 산화와 어닐링을 진행함으로써 신뢰성있는 SOC를 제조하기 위한 2단계 산화공정에 의한 듀얼 게이트산화막 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems, in order to effectively increase the delta thickness even at a constant N implant amount when forming a multi-gate oxide film by nitrogen ion implantation proceeds to annealing at a constant temperature after nitrogen ion implantation and 2 during the oxidation process It is an object of the present invention to provide a dual gate oxide film formation method by a two-step oxidation process for producing reliable SOC by performing oxidation and annealing in steps.

도1은 종래기술의 1단계 게이트산화막 성장방법에 의한 산화막 성장시 N의 주입량에 따른 두께 변화는 나타낸 그래프,1 is a graph showing the change in thickness according to the injection amount of N during the growth of the oxide film by a one-step gate oxide film growth method of the prior art;

도2a 내지 도2e는 본 발명에 의한 2단계 산화공정에 의한 듀얼 게이트산화막 형성방법을 도시한 공정순서도,2A to 2E are process flowcharts illustrating a method of forming a dual gate oxide film by a two-step oxidation process according to the present invention;

도3은 본 발명에 의한 질소 이온주입후의 어닐링 온도에 따른 델타 두께 차이를 도시한 그래프,3 is a graph showing the difference in delta thickness according to the annealing temperature after nitrogen ion implantation according to the present invention;

도4는 종래기술과 본 발명에 의한 델타 두께 차이를 비교하여 나타낸 그래프.Figure 4 is a graph showing a comparison between the delta thickness difference according to the prior art and the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 필드산화막 3 : 희생산화막1: field oxide film 3: sacrificial oxide film

4 : 질소 이온주입 5 : 질소이온주입영역4: nitrogen ion implantation 5: nitrogen ion implantation zone

6 : 어닐링 7 : 얇은 산화막6: annealing 7: thin oxide film

9 : 두꺼운 산화막 11 : 전도층9: thick oxide film 11: conductive layer

상기 목적을 달성하기 위한 본 발명은, 실리콘기판상에 희생산화막을 형성하는 단계와, 상기 실리콘기판의 일정부분을 노출시키기 위한 마스크공정을 진행하는 단계, 일정한 에너지와 주입량으로 기판에 질소를 이온주입하는 단계, 상기 실리콘기판에 이온주입된 질소를 기판 표면쪽으로 모으기 위하여 불활성 분위기의 일정온도에서 어닐링을 행하는 단계, 상기 희생산화막을 제거하는 단계, 및 2단계 산화공정을 진행하여 서로 다른 두께를 갖는 게이트산화막들을 동시에 형성하는 단계를포함하여 구성되는 것을 특징으로 한다.The present invention for achieving the above object, the step of forming a sacrificial oxide film on a silicon substrate, performing a mask process for exposing a portion of the silicon substrate, ion implantation of nitrogen into the substrate at a constant energy and injection amount Performing annealing at a constant temperature in an inert atmosphere, removing the sacrificial oxide film, and performing a two-step oxidation process to collect nitrogen implanted into the silicon substrate toward the substrate surface. And forming oxide films simultaneously.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도2a 내지 도2e를 참조하여 본 발명에 의한 2단계 산화공정에 의한 듀얼 게이트산화막 형성방법을 설명하면 다음과 같다.Referring to Figures 2a to 2e will be described a method of forming a dual gate oxide film by a two-step oxidation process according to the present invention.

먼저, 도2a에 나타낸 바와 같이 필드산화막(1)이 형성된 실리콘기판상에 희생산화막(3)을 형성한 후, 기판의 일정부분을 노출시키기 위한 마스크공정을 통해 기판 소정부분에 선택적으로 포토레지스트패턴을 형성한 다음, 일정한 에너지와 주입량으로 질소이온주입(4)을 실시하여 질소 이온주입영역(5)을 형성한다. 이때, 이온주입 에너지는 3keV~50keV로 하고, 주입량은 5E13~1E15cm-2로 하는 것이 바람직하다.First, as shown in FIG. 2A, after the sacrificial oxide film 3 is formed on the silicon substrate on which the field oxide film 1 is formed, a photoresist pattern is selectively formed on a predetermined portion of the substrate through a mask process for exposing a portion of the substrate. Next, the nitrogen ion implantation region 5 is formed by performing nitrogen ion implantation 4 at a constant energy and implantation amount. At this time, the ion implantation energy is 3keV ~ 50keV, the injection amount is preferably 5E13 ~ 1E15cm -2 .

이어서 도2b에 도시된 바와 같이 상기 포토레지스트패턴을 제거한 후, 실리콘기판에 이온주입된 질소를 기판 상부쪽으로 모으기 위하여 불활성 분위기의 일정온도에서 어닐링(6)을 행한다. 이때, 어닐링 온도는 400~700℃로 하고, 시간은 1분~1시간 정도로 하는 것이 바람직하다.Subsequently, after removing the photoresist pattern as shown in FIG. 2B, annealing 6 is performed at a constant temperature in an inert atmosphere in order to collect nitrogen implanted into the silicon substrate toward the upper portion of the substrate. At this time, it is preferable that annealing temperature shall be 400-700 degreeC, and time shall be about 1 minute-1 hour.

다음에 도2c에 도시된 바와 같이 희생산화막을 제거한다.Next, the sacrificial oxide film is removed as shown in FIG. 2C.

이어서 도2d에 나타낸 바와 같이 2단계 산화공정을 진행하여 서로 다른 두께를 갖는 게이트산화막들(7,9)을 형성한다. 이 2단계 산화공정은 제1산화/어닐링과 제2산화/어닐링으로 이루어진다. 제1산화에서는 O2를 50~5000sccm 주입하고, 제1어닐링은 N2등의 불활성가스 또는 N2/O2분위기에서 진행한다. 제2산화는 O2, H2O, D2O 등의 분위기에서 진행하고, 제2어닐링은 N2분위기에서 일정 시간동안 진행한다. 이러한 2단계 산화 및 어닐링 공정은 600~1000℃ 온도에서 진행하고, 어닐링 시간은 10분~1시간 이내로 진행한다.Subsequently, as shown in FIG. 2D, a two-step oxidation process is performed to form gate oxide films 7 and 9 having different thicknesses. This two-step oxidation process consists of a first oxidation / anneal and a second oxidation / anneal. The first ~ 50 5000sccm injection of O 2 in the oxidation, and the first annealing is conducted in an inert gas or a N 2 / O 2 atmosphere such as N 2. The second oxidation proceeds in an atmosphere such as O 2 , H 2 O, D 2 O, and the second annealing proceeds in a N 2 atmosphere for a predetermined time. This two-stage oxidation and annealing process is carried out at a temperature of 600 ~ 1000 ℃, annealing time is carried out within 10 minutes ~ 1 hour.

이어서 도2e에 나타낸 바와 같이 상기와 같이 형성된 서로 상이한 두께를 갖는 게이트산화막(7,9) 상부에 전도층(11)을 형성한다.Subsequently, as shown in FIG. 2E, the conductive layer 11 is formed on the gate oxide films 7 and 9 having different thicknesses formed as described above.

본 발명에서는 N 이온주입후, 실리콘기판에 있는 N을 표면으로 모으기 위해 어닐링 공정을 진행하는데, 이에 대한 실험결과를 도3에 나타내었다. 도시된 바와 같이 어닐링 공정을 행하지 않은 경우에 비해서 500~600℃로 어닐링한 시료의 델타 두께가 약 1~2Å 정도 증가되는 것을 확인할 수 있다. 그러나 그 이상의 온도에서는 오히려 감소하는 것을 알 수 있는데, 이는 높은 어닐링 온도에서 실리콘기판에 있는 N이 실리콘 표면에 모이는 것 뿐만 아니라 희생산화막내로도 확산해 들어가기 때문이다(이후 희생산화막은 제거된 다음 산화공정이 진행됨).In the present invention, after the implantation of N ions, an annealing process is performed to collect N on the surface of the silicon substrate, the experimental results are shown in FIG. As shown, it can be seen that the delta thickness of the sample annealed at 500 to 600 ° C. is increased by about 1 to 2 mm as compared with the case where the annealing process is not performed. At higher temperatures, however, it is rather reduced, because at high annealing temperatures, N on the silicon substrate not only collects on the silicon surface but also diffuses into the sacrificial oxide film (the sacrificial oxide film is then removed and then oxidized). Proceeded).

도4는 종래기술에 의한 1단계 산화공정에 의해 성장된 산화막과 본 발명의 2단계 산화공정에 의해 성장된 산화막의 델타 두께를 비교하여 나타낸 것이다. 그림에서 확인할 수 있는 바와 같이 본 발명에 의한 델타 두께가 종래 기술에 비해 두배 이상 증가하는 것을 알 수 있다. 이러한 차이는 제1산화에 의해 일정 두께로 성장한 산화막에 제1어닐링 공정으로 실리콘기판에 있는 N을 확산시켜 산화막을 효과적으로 질화시키기 때문이다. 이렇게 질화된 얇은 산화막은 제2산화에서도 산화에 대한 저항력이 높아져 상대적으로 N이 이온주입되지 않은 영역에 비해서 두께의 증가가 현저히 감소하게 된다.Figure 4 shows a comparison of the delta thickness of the oxide film grown by the conventional one-step oxidation process and the oxide film grown by the two-step oxidation process of the present invention. As can be seen in the figure, it can be seen that the delta thickness according to the present invention is more than doubled compared with the prior art. This difference is due to the diffusion of N in the silicon substrate by the first annealing process to the oxide film grown to a certain thickness by the first oxidation to effectively nitride the oxide film. The nitrided thin oxide film has a high resistance to oxidation even in the second oxidation, and the increase in thickness is significantly reduced compared to a region where N is not ion implanted.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명은 질소 이온주입후 적절한 어닐링과 2단계 산화공정을 행함으로써 일정한 N 주입량에서도 N 이온주입이 되지 않은 영역과의 두께 차이(델타 두께)를 크게 할 수 있다. 즉, 낮은 N 주입량으로 두께 차이를 증가시킬 수 있기 때문에 공정 윈도우를 넓힐 수 있게 되어 제품의 신뢰성을 증가시키는 효과가 얻어진다.According to the present invention, by performing an annealing and two-step oxidation process after nitrogen ion implantation, the thickness difference (delta thickness) with a region where N ion implantation is not performed even at a constant N implantation amount can be increased. That is, since the thickness difference can be increased with a low N injection amount, the process window can be widened, thereby increasing the reliability of the product.

Claims (10)

실리콘기판상에 희생산화막을 형성하는 단계와,Forming a sacrificial oxide film on the silicon substrate; 상기 실리콘기판의 일정부분을 노출시키기 위한 마스크공정을 진행하는 단계,Performing a mask process for exposing a portion of the silicon substrate; 일정한 에너지와 주입량으로 기판에 질소를 이온주입하는 단계,Ion implanting nitrogen into the substrate with a constant energy and implantation amount, 상기 실리콘기판에 이온주입된 질소를 기판 표면쪽으로 모으기 위하여 불활성 분위기의 일정온도에서 어닐링을 행하는 단계,Annealing at a constant temperature in an inert atmosphere to collect nitrogen implanted into the silicon substrate toward the substrate surface; 상기 희생산화막을 제거하는 단계, 및Removing the sacrificial oxide film, and 2단계 산화공정을 진행하여 서로 다른 두께를 갖는 게이트산화막들을 동시에 형성하는 단계를 포함하여 구성되는 2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법.A method of forming a dual gate oxide film by a two-step oxidation process comprising: simultaneously performing a two-step oxidation process to form gate oxide films having different thicknesses. 제1항에 있어서,The method of claim 1, 상기 질소 이온주입시 이온주입 에너지는 3keV~50keV로 하는 것을 특징으로 하는 2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법.The ion implantation energy of the nitrogen ion implantation is 3keV ~ 50keV dual gate oxide film forming method by a two-step oxidation process characterized in that. 제1항에 있어서,The method of claim 1, 상기 질소 이온주입시 주입량은 5E13~1E15cm-2로 하는 것을 특징으로 하는 2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법.The method of forming a dual gate oxide film by a two-step oxidation process, characterized in that the injection amount when the nitrogen ion implantation is 5E13 ~ 1E15cm -2 . 제1항에 있어서,The method of claim 1, 상기 실리콘기판에 이온주입된 질소를 기판 표면쪽으로 모으기 위한 어닐링을 400~700℃의 온도에서 행하고, 시간은 1분~1시간 정도로 하는 것을 특징으로 하는 2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법.An annealing for collecting nitrogen ion implanted into the silicon substrate toward the surface of the substrate at a temperature of 400 ~ 700 ℃, the time is about 1 minute to 1 hour, characterized in that the dual gate oxide film forming method by a two-step oxidation process. 제1항에 있어서,The method of claim 1, 상기 2단계 산화공정은 제1산화 및 어닐링과 제2산화 및 어닐링으로 이루어지는 것을 특징으로 하는 2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법.The two-step oxidation process is a dual gate oxide film forming method according to the two-step oxidation process characterized in that the first oxidation and annealing and the second oxidation and annealing. 제5항에 있어서,The method of claim 5, 상기 제1산화에서는 O2를 50~5000sccm 주입하여 산화를 진행하는 것을 특징으로 하는 2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법.In the first oxidation, a method of forming a dual gate oxide film by a two-step oxidation process, characterized in that the oxidation by injecting 50 ~ 5000sccm O 2 . 제5항에 있어서,The method of claim 5, 상기 제1어닐링은 N2등의 불활성가스 또는 N2/O2분위기에서 진행하는 것을 특징으로 하는 2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법.The first anneal is a dual gate oxide film formation method according to the two-step oxidation process, characterized in that proceeding from an inert gas or a N 2 / O 2 atmosphere such as N 2. 제5항에 있어서,The method of claim 5, 상기 제2산화는 O2, H2O, D2O 등의 분위기에서 진행하는 것을 특징으로 하는 2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법.The second oxidation is a method of forming a dual gate oxide film by a two-step oxidation process, characterized in that in the atmosphere of O 2 , H 2 O, D 2 O and the like. 제5항에 있어서,The method of claim 5, 상기 제2어닐링은 N2분위기에서 진행하는 것을 특징으로 하는 2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법.Wherein the second annealing is performed in an N 2 atmosphere. 제1항에 있어서,The method of claim 1, 상기 2단계 산화 및 어닐링 공정은 600~1000℃ 온도에서 진행하는 것을 특징으로 하는 2단계 산화공정에 의한 듀얼 게이트 산화막 형성방법.The two-step oxidation and annealing process is a dual gate oxide film forming method by a two-step oxidation process, characterized in that proceeding at a temperature of 600 ~ 1000 ℃.
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Publication number Priority date Publication date Assignee Title
KR100695004B1 (en) * 2005-11-01 2007-03-13 주식회사 하이닉스반도체 Method of forming an oxide film in a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100695004B1 (en) * 2005-11-01 2007-03-13 주식회사 하이닉스반도체 Method of forming an oxide film in a semiconductor device

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