KR20040009867A - Interconnection structure connecting electrically isolated regions and method of fabricatinging the same - Google Patents

Abstract

PURPOSE: An interconnection structure for connecting isolated regions and a fabricating method thereof are provided to simplify a fabricating process by forming an interconnection structure between active regions, an interconnection structure between conductive lines, and an interconnection structure between a gate electrode and the active region with the same material. CONSTITUTION: An interconnection structure for connecting isolated regions includes the first to the third active regions(116a,116b,116c), the first and the second conductive lines(110a,110b), an interlayer dielectric(127), the first interconnection structure(134), and the second interconnection structure(136). The first to the third active regions(116a,116b,116c) are isolated by a field region of a substrate. The first and the second conductive lines(110a,110b) are formed across the field region adjacent to both sides of the third active region. The interlayer dielectric(127) is laminated on the substrate. The first interconnection structure(134) is formed within the interlayer dielectric to connect the first active region to the second active region. The second interconnection structure(136) is formed within the interlayer dielectric to connect the first conductive line to the second conductive line. The interlayer dielectric is inserted between the first and the second conductive lines.

Description

INTERCONNECTION STRUCTURE CONNECTING ELECTRICALLY ISOLATED REGIONS AND METHOD OF FABRICATINGING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an interconnection structure and a method for manufacturing the interconnection regions electrically connected to each other.

A semiconductor integrated circuit is formed of a contact hole and a wiring structure for forming elements such as transistors electrically isolated on a semiconductor substrate and selectively connecting the elements.

For example, the connection between the active region and the active region (active to active), the connection between the gate electrode and the gate electrode (gate to gate), the connection between the gate electrode and the active region (gate to active) as the contact hole and wiring structure as necessary Are interconnected.

1A is a cross-sectional view showing an interconnect structure according to the prior art. In the drawing, the interconnection region of the active region and the active region (hereinafter 'A' region), the interconnection region of the gate electrode and the gate electrode (hereinafter 'B' region), and the interconnection region of the gate electrode and the active region (hereinafter 'C') 'Area).

Referring to FIG. 1A, a field region 6 defining a first active region 16a and a second active region 16b doped with impurities is disposed in an area 'A'. An interlayer insulating layer 20 is stacked on the substrate, and contact plugs 22 are formed through the interlayer insulating layer 20 to be electrically connected to the active regions 16a and 16b. The contact plugs 22 are electrically connected to each other by interconnection lines 34. Thus, the first active region 16a and the second active region 16b are electrically connected by the contact plugs 22 and the interconnect line 34.

In the 'B' region, an active region 16c in which the impurities are doped between the field regions 6 is defined in the substrate, and the first conductive line 10a and the second conductive line 10b are formed on the field region 6. Is placed. The conductive lines 10a and 10b are formed on the field region 6 in the drawing, but when the conductive lines cross the active region, they become gate electrodes. On the substrate including the conductive lines 10a and 10b. The interlayer insulating layer 20 is stacked, and contact plugs 24 are formed through the interlayer insulating layer 20 and electrically connected to the conductive lines 16a and 16b, respectively. The contact plugs 24 are electrically connected to each other by an interconnect line 36. Thus, the first and second conductive lines 10a and 10b are electrically connected to each other by the contact plugs 24 and the interconnection line 36.

In the 'C' region, a MOS transistor including a source stack and a drain region 18 formed on the gate stack and the substrate on both sides of the gate stack is formed. The gate stack includes a gate insulating film 8, a gate electrode 10c, and a spacer 14 formed on sidewalls of the gate electrode, and the source and drain regions 18 include a low concentration impurity region 12 and a high concentration impurity. It consists of an area 16d. An interlayer insulating layer 20 is stacked on the substrate on which the MOS transistor is formed, and electrically connects the gate electrode 10c of the MOS transistor and the active region 16d doped with impurities through the interlayer insulating layer 20. The contact plug 26 is formed. The contact plug 26 is connected to the interconnect line 38.

As described above, in semiconductor integrated circuits, electrically isolated regions are electrically interconnected using contact plugs 22, 24, 26 and interconnect lines 34, 36, 38. However, in order to form the contact plugs 22, 24, and 26, the interlayer insulating layer 20 is selectively etched to form contact holes. As the integration of semiconductor manufacturing processes proceeds, it becomes difficult to form hole patterns. .

In addition, as integration increases, it becomes difficult to electrically insulate adjacent patterns. For example, a misalignment occurs in the photolithography process of forming contact holes on the conductive lines 10a and 10b in the 'B' region, and thus, between the active region 16c and the conductive lines 10a and 10b doped with impurities. It can be electrically shorted. In order to solve this problem, in the case where the conductive lines 10a and 10b are directly connected in the 'B' region, the conductive line acts as a mask for impurity ion implantation, and thus, between the field regions 6 in the 'B' region. No impurities are injected into the active region. That is, as shown in FIG. 1B, an unwanted MOS transistor is formed while the conductive line 10 crosses the active region, causing device failure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an interconnection structure and a method of manufacturing the interconnection of electrically isolated regions while securing an insulating layer by using a damascene process.

In addition, an object of the present invention is to provide an interconnect structure and a method for manufacturing the interconnect structure that can be formed in a single layer at the same time, while the process is simple.

1a and 1b are cross-sectional views showing an interconnect structure according to the prior art,

2 is a cross-sectional view showing an interconnect structure according to the present invention;

3 to 7 are cross-sectional views showing a method of manufacturing an interconnect structure according to a first embodiment of the present invention;

8 to 10 are cross-sectional views showing a method of manufacturing an interconnect structure according to a second embodiment of the present invention;

11 is a circuit diagram of an SRAM cell,

12-16 are diagrams for implementing two SRAM cells using an interconnect structure in accordance with the present invention.

* Explanation of symbols for the main parts of the drawings

2, 102: substrate 6, 106: field area

10a, 10b, 110a, 110b: conductive lines 10c, 110c: gate electrode

16a, 16b, 16c, 16d, 116a, 116b, 116c, 116d: active region doped with impurities

120, 220: etch stop film 122, 222: lower interlayer insulating film

124, 224: upper interlayer insulating film 127, 227: interlayer insulating film

134, 234: first interconnect structure 136, 236: second interconnect structure

138, 238: third interconnection structure

In order to achieve the above object, the interconnect structure connecting the electrically isolated regions of the present invention to each other includes a first interconnect structure, a first conductive line and a second conductive line connecting the first active region and the second active region. And a third interconnection structure connecting the fourth active region and the gate electrode. Specifically, the first active region, the second active region, the third active region, and the fourth active region are electrically isolated from the substrate by the field region. First and second conductive lines are disposed on the field regions adjacent to both sides of the third active region, and gate electrodes are disposed in the fourth active region through the gate insulating layer. An interlayer insulating layer including an etch stop layer, a lower interlayer insulating layer, and an upper interlayer insulating layer is stacked on the substrate on which the first conductive line, the second conductive line, and the gate electrode are formed. A first interconnect structure electrically connecting the first active region and the second active region, a second interconnect structure electrically connecting the first conductive line and the second conductive line, and the fourth interlayer insulating layer; A third interconnect structure for electrically connecting the active region and the gate electrode is formed by a damascene process. The interlayer insulating layer is interposed between the first conductive line and the second conductive line to electrically insulate the third active region from the second interconnect structure.

In addition, the method of manufacturing an interconnect structure according to the present invention forms a field region defining a first active region, a second active region, a third active region and a fourth active region on a substrate. Subsequently, a first conductive line and a second conductive line are formed on the field regions adjacent to both sides of the third active region, and a gate electrode is formed on the fourth active region via a gate insulating layer. A first opening and a first opening exposing the first active region and the second active region in the interlayer insulating layer after the interlayer insulating layer is stacked on the substrate on which the first conductive line, the second conductive line, and the gate electrode are formed; A second opening exposing the top surface of the line and the second conductive line and a third opening exposing the top surface of the fourth active region and the gate electrode are formed. When the second opening is formed, the interlayer insulating film is left in the gap between the first and second conductive lines. Subsequently, a first interconnect structure connecting the first active region and the second active region, the first conductive line, and the second conductive line are filled by filling the first opening, the second opening, and the third opening with a conductive material. A second interconnect structure, a third interconnect structure connecting the fourth active region and the gate electrode.

The interlayer insulating film must remain in the gap between the first conductive line and the second conductive line on the bottom surface of the second opening while forming the first opening, the second opening, and the third opening in the interlayer insulating film. In addition, it is preferable that the first conductive line, the second conductive line, and the interlayer insulating layer remaining therebetween be aligned horizontally. To this end, two methods may be used.

In the first method, the interlayer insulating layer is selectively etched until the upper surfaces of the first conductive line, the second conductive line, and the gate electrode are exposed to expose the first opening and the first conductive line. And a second opening exposing the second conductive line and the interlayer insulating film remaining in the gap therebetween, and a third opening exposing a portion of the upper surface of the gate electrode. Subsequently, the remaining interlayer insulating layer is selectively etched from the bottom of the first opening and the third opening to expose a first active region and a second active region on the bottom of the first opening, and a third on the bottom of the third opening. Expose the active area.

In the second method, the interlayer insulating film is laminated with a lower interlayer insulating film and an upper interlayer insulating film having different etching selectivity. Subsequently, the upper interlayer insulating film is selectively patterned until the surface of the lower interlayer insulating film is exposed to form a first opening, a second opening, and a third opening. Subsequently, a portion of the lower interlayer insulating film on the bottom of the first opening and the third opening is selectively etched to form a thickness of the lower interlayer insulating film from the substrate to the bottom of the first opening and the third opening, and the first and the second and third openings. The thickness of the lower interlayer insulating film from the top surface of the second conductive line to the bottom surface of the second opening and the third opening is similar. Subsequently, the lower interlayer insulating layer is etched entirely using the patterned upper interlayer insulating layer as an etch mask until the active region of the substrate is exposed. In this way, an interlayer insulating film remains in the gap between the first conductive line and the second conductive line.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawing, the connection region of the active region and the active region (hereinafter 'A' region), the connection region of the gate electrode and the gate electrode (hereinafter 'B' region), and the connection region of the gate electrode and the active region (hereinafter 'C' region) Separated by.

2 is a cross-sectional view illustrating an interconnect structure according to the present invention.

In the region 'A', the first active region 116a and the second active region 116b doped with impurities in the substrate 102 are spaced a predetermined distance apart from each other with the field region 106 interposed therebetween. The interlayer insulating layer 127 including the etch stop layer 120, the lower interlayer insulating layer 122, and the upper interlayer insulating layer 124 is sequentially stacked on the substrate. A first interconnect structure 134 is disposed in the interlayer insulating layer 127 to electrically connect the first active region 116a and the second active region 116b.

In the region 'B', the field regions 106 are spaced apart from the substrate 102 with the third active region 116c doped with impurities therebetween. The first conductive line 110a and the second conductive line 110b are disposed on each of the field regions 106. The first and second conductive lines 110a and 110b cross the field region and the active region on the substrate, and become the gate electrodes of the transistor when crossing the active region. An interlayer insulating layer 127 including an etch stop layer 120, a lower interlayer insulating layer 122, and an upper interlayer insulating layer 124 is stacked on the substrate on which the first and second conductive lines 110a and 110b are formed. A second interconnection structure 136 is disposed in the interlayer insulating layer 127 to electrically connect the first conductive line 110a and the second conductive line 110b. The second interconnect structure includes an insulating layer including a spacer 114, an etch stop layer 120, and a lower interlayer insulating layer 122 in a gap between the first and second conductive lines 110a and 110b. 136 and the third active region 116c are electrically insulated from each other.

In the 'C' region, a MOS transistor including a gate stack formed on a substrate and an active region 118 doped with impurities is disposed on substrates on both sidewalls of the gate stack. The gate stack includes a gate electrode 110c via a gate insulating film 108 and a spacer 114 formed on sidewalls of the gate electrode 110c. The impurity doped active region 118 is a source and drain region, and is composed of a low concentration impurity region 112 and a high concentration impurity region 116d. On the substrate on which the MOS transistor is formed, an interlayer insulating layer 127 including an etch stop layer 120, a lower interlayer insulating layer 122, and an upper interlayer insulating layer 124 is sequentially stacked, and in the interlayer insulating layer 127. A third interconnect structure 138 is disposed to electrically connect the top surface of the gate electrode 110c and the active region 118.

Hereinafter, a manufacturing method for forming the interconnect structure described above will be described.

3 to 7 are cross-sectional views illustrating a method of manufacturing an interconnect structure according to a first embodiment of the present invention.

Referring to FIG. 3, a field region 106 defining a first active region 116a, a second active region 116b, a third active region 116c, and a fourth active region 116d on the substrate 102. ). In other words, the substrate 102 is selectively etched to form the trench 104, and the field region 106 is formed by embedding and chemically polishing the insulator which sufficiently fills the trench 104.

The gate insulating film and the first conductive film are sequentially stacked on the substrate on which the field region 106 is formed, and the first conductive film and the gate insulating film are patterned by a normal photolithography process. That is, in the 'B' region, the first conductive line 110a and the second conductive line 110b are formed on each of the field regions 106 on both sides of the third active region 116c, and the 'C' In the region, the gate electrode 110c is formed through the gate insulating film 108. The first conductive layer may be formed of at least one selected from a polysilicon layer, a silicide layer, and a tungsten layer. Subsequently, the low concentration impurity region 112 is formed using the gate electrode 110c and the field region 106 as an ion implantation mask. The spacer insulating layer may be stacked on the entire surface of the substrate and etched anisotropically to form spacers 114 on sidewalls of the first conductive line 110a, the second conductive line 110b, and the gate electrode 110c. . The spacers 114 are formed on the sidewalls of the gate electrode 110c and the field region 106 as ion implantation masks to form active regions 116a, 116b, 116c, and 116d doped with high concentration impurities. In the 'C' region, the low concentration impurity region 112 and the active region 116d doped with the high concentration impurity become the source and drain regions 118 of the MOS transistor.

Referring to FIG. 4, an interlayer insulating layer 127 including an etch stop layer 120, a lower interlayer insulating layer 122, and an upper interlayer insulating layer 124 is stacked on an entire surface of the substrate on which the first conductive layer is patterned. Reference numeral 122 may be formed of a material having an etching rate different from that of the etch stop layer 120 and the upper interlayer insulating layer 124. The upper interlayer insulating layer 124 may serve as an antireflection film or a hard mask film.

Referring to FIG. 5, the photoresist pattern 125 is formed by a general photo process, and the upper interlayer insulating layer 124 and the lower interlayer insulating layer 122 are formed using the photoresist pattern 125 as an etching mask. The openings 126a, 128b, and 130c are formed by etching until the etch stop layer 120 formed on the first conductive line 110a, the second conductive line 110b, and the gate electrode 110c is exposed. . Part of the lower interlayer insulating film 122 remains on the bottoms of the openings 126a and 130a in regions 'A' and 'C'. The lower interlayer insulating film 122 remains in the gap between the conductive lines 110a and 110b at the bottom of the opening 128a in the region 'B'.

Referring to FIG. 6, a mask pattern 132 is formed to sufficiently cover the opening 128a of the 'B' region through a conventional photographic process. Subsequently, the remaining lower interlayer insulating layer 122 is etched in the 'A' region and the 'C' region by using the mask pattern 132 and the upper interlayer insulating layer 124 as an etching mask. Openings 126b and 130b with the surface of 120 exposed are formed.

Referring to FIG. 7, the mask pattern 132 is removed and the exposed etch stop layer 120 is etched using the upper interlayer insulating layer 124 as an etch mask. Accordingly, the first active region 116a and the second active region 116b and the field region 106 therebetween are exposed in the opening 126c of the 'A' region, and the opening of the 'B' region is exposed. An insulating layer remaining in the gap between the top surfaces of the first and second conductive lines 110a and 110b and the conductive lines 110 and 110b is exposed at 128c, and the gate 130 is formed in the opening 130c of the 'C' region. An upper surface of the electrode 110 and the fourth active region 116d are exposed.

Referring to FIG. 2 again, a second conductive layer is formed to sufficiently fill the openings 126c, 128c, and 130c, and the second conductive layer is planarized until the upper interlayer insulating layer 124 is exposed. The second conductive film is preferably formed of any one selected from tungsten, aluminum, copper, titanium, titanium nitride, and tantalum nitride, and the planarization is preferably chemical mechanical polishing or etch back. When the planarization process is performed, an interconnection structure 134 connecting the first active region 116a and the second active region 116b is formed in region 'A', and the first conductive line is formed in region 'B'. An interconnection structure 136 is formed to connect 110a and the second conductive line 110b, and interconnection between the gate electrode 110c and the fourth active region 116d in the 'C' region. Structure 138 is formed. The first interconnect structure 134, the second interconnect structure 136, and the third interconnect structure 138 are horizontally aligned with each other.

8 to 10 are cross-sectional views illustrating a method of manufacturing an interconnect structure according to a second embodiment of the present invention. The second embodiment is the same until the process of forming the photosensitive film pattern 125 on the interlayer insulating film 127 in the first embodiment.

Referring to FIG. 8, by using the photoresist pattern 125 as an etching mask, the upper interlayer insulating layer 124 is selectively etched until the surface of the lower interlayer insulating layer 122 is exposed, thereby openings 126d and 128d. 130d).

Referring to FIG. 9, the photoresist layer pattern 135 is removed, and a mask pattern 140 is formed to sufficiently cover the opening 128d in the 'B' region by a normal photographic process. Subsequently, the exposed lower interlayer insulating layer 122 is selectively etched in the 'A' and 'C' regions using the mask pattern 140 and the upper interlayer insulating layer 124 as an etching mask. As a result, the thickness of the lower interlayer insulating film formed on the conductive lines 110a and 110b at the bottom of the opening 128d in the 'B' region (indicated by 'b' in the drawing), and the 'A' region and the 'C' The thicknesses of the lower interlayer insulating films formed on the substrate at the bottoms of the openings 126e and 130e in the regions (angles shown by 'a' and 'c' in the drawings) are similar.

Referring to FIG. 10, the photoresist layer pattern 140 is removed, and the lower interlayer insulating layer 122 is etched using the upper interlayer insulating layer 124 as an etch mask to expose a surface of the etch stop layer 122. Openings 126b, 128a, and 130b are formed. Since the thickness of the lower interlayer insulating layer to be etched is the same, the spacer 114, the etch stop layer 120 and the lower interlayer insulating layer 122 remain in the gap between the conductive lines 110a and 110b in the 'B' region. do.

Referring back to FIG. 2, the etch stop layer 120 exposed on the bottom of the openings 126b, 128a, and 130b is removed, and the interconnect structures 134, 136, and 138 are filled by filling the openings with a conductive film. Form.

The interconnect structure of the first and second embodiments described above has the advantage of simultaneously forming the connection between the active region and the active region, the connection of the conductive line and the conductive line, and the connection of the gate electrode and the active region to a single material using a damascene process. There is this. The embodiment illustrates a process of simultaneously forming interconnect structures of region 'A', 'B', and 'C'. However, the present invention is not limited thereto, and only the interconnect structures in the 'A' region and the 'B' region are simultaneously formed, or only the interconnect structures in the 'B' region and the 'C' region are simultaneously formed, or ' Only the interconnection structure in the A 'region and the' C 'region can be formed at the same time.

Such interconnect structures can be used in a variety of semiconductor manufacturing processes. Hereinafter, an embodiment in which the method of manufacturing the interconnect structure described above is actually applied to a static random access memory (SRAM) will be described with reference to the drawings of FIGS. 11 to 16. An embodiment actually applied in SRAM is a manufacturing method for simultaneously forming interconnect structures in the 'A' region and the 'B' region described above.

11 is a circuit diagram of an SRAM cell, and FIGS. 12-16 are diagrams for implementing two SRAM cells using the interconnect structure of the present invention.

Referring to FIG. 11, an SRAM cell is composed of two access transistors AT1 and AT2, two pull-up transistors PT1 and PT2, and two driver transistors DT1 and DT2. Transistors PT1 and DT1 constitute a first inverter, and transistors PT2 and DT2 constitute a second inverter. The first and second inverters are cross connected at two nodes N1 and N2. The source regions of the transistors DT1 and DT2 are connected to the ground line Vss, and the source regions of the transistors PT1 and PT2 are connected to the power supply line VDD. The drain of the transistor AT1 is connected to the bit line BL1, and the drain of the transistor AT2 is connected to the bit line BL2. The source of transistor AT1 and the source of transistor AT2 are connected to node N1 and node N2, respectively. Gate electrodes of the transistors AT1 and AT2 are connected to the common word line WL.

12 and 13 are plan views showing two SRAM cells facing each other in a mirror image with respect to the line h-h '.

Referring to FIG. 12, field regions 206 defining active regions 216a and 216b are defined. The active region is composed of a first active region 216a in which an n-type transistor is formed and a second active region 216b in which a p-type transistor is formed.

First active layers 210a, 210b, and 211 cross the active regions 216a and 216b and the field region 206. The first conductive film constitutes first gate electrodes 210a and 210b and second gate electrode 211. Two first gate electrodes and two second gate electrodes are disposed in one cell.

The two first gate electrodes 210a and 210b respectively form a gate for the transistor AT1 and the transistor AT2 across the first active region 216a.

One of the second gate electrodes 211 is disposed to be perpendicular to the first gate electrodes 210a and 210b, and forms gate electrodes of the transistors DT1 and PT1 across the active regions 216a and 216b. And connect these gate electrodes. Another second gate electrode 211 forms a gate electrode for transistor DT2 and transistor PT2 and connects these gate electrodes.

Impurities are ion implanted into the active regions 216a and 216b between the first conductive layers 21a, 210b and 211. The first active region 216a is formed with an n-type highly doped ion implanted active region (indicated by N + in the drawing). In the second active region 216b, a highly doped ion implanted p-type implanted active region (indicated by P + in the drawing) is formed.

FIG. 13 is a plan view illustrating second conductive layers 234 and 236 on the drawing of FIG. 12.

Referring to FIG. 13, the second conductive layer includes a word line 236 connecting the first gate electrodes 210a and 210b to each other, an active region 216a doped with n-type impurities, and an active region doped with p-type impurities. It consists of an interconnect structure 234 connecting the regions 216b to each other.

FIG. 14 is a cross-sectional view taken along line II ′ of FIG. 13, and an interconnection structure 234 connecting an n-type doped active region 216a and a p-type doped active region 216b in region 'A'. ) Is a word line 236 connecting the gate electrode 210a and the gate electrode 210b in the 'B' region.

13 and 14, in the 'A' region, an n-type doped active region 216a and a p-type active region 216b are disposed between the substrate 202 and the field region 206 therebetween. It is arranged. An interlayer insulating film 227 including an etch stop film 220, a lower interlayer insulating film 222, and an upper interlayer insulating film 224 is sequentially stacked on the substrate. An interconnect structure 234 formed by a damascene process is disposed in the interlayer insulating layer to electrically connect the n-type doped active region and the p-type doped active region 216b to each other.

In the 'B' region, an active region is defined on the substrate by the field region 106. The gate electrodes 210a and 210b crossing the active region and the field region are spaced apart from each other by a predetermined distance. An insulating layer composed of a spacer 214, an etch stop layer 220, and a lower interlayer insulating layer 222 is interposed in the gap between the gate electrodes 210a and 210b. The gate electrodes 210a and 210b and the insulating layer interposed therebetween are horizontally aligned. A word line 236 is disposed on upper surfaces of the gate electrodes 210a and 210b to electrically connect the gate electrodes to each other. An n-type doped active region 216a intersecting the word line 236 perpendicular to the word line 236 is disposed on the lower substrate of the word line 236 with the lower interlayer insulating layer 222 and the etch stop layer 220 therebetween. do. The n-type doped active region 216a and the word line 236 intersect with each other in plane and have the effect of acting as conductive lines.

The interconnect structure 234 in the 'A' region and the word line 236 in the 'B' region are formed of a series of etch stop layers 222, a lower interlayer dielectric layer 222, and an upper interlayer dielectric layer 224. The insulating films 227 are manufactured by the damascene process, and the detailed manufacturing method is the same as the first and second embodiments described above.

An advantage of forming the SRAM cell in the structure shown in Figs. 13 and 14 is that the density of the cell can be increased and the process can be simplified. For example, since the n-doped n-type doped active region 216a and the word line 236 become conductive lines, the common ground line 244 may be formed in two cells as shown in FIG. 15.

FIG. 15 is a plan view illustrating the third conductive layer in the plan view of FIG. 13.

Referring to FIG. 15, the third conductive layers 240, 242, and 244 include a local wiring 240, a power supply line 242, and a common ground line 244, and are electrically isolated from each other through contacts. Connect the

FIG. 16 is a plan view illustrating a fourth conductive film in the plan view of FIG. 15.

Referring to FIG. 16, the fourth conductive layer 250 becomes a bit line and is connected to an n-type doped active region through a contact.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention made as described above, the interconnection structure of the active region and the active region, the interconnection structure of the conductive line and the conductive line, and the interconnection structure of the gate electrode and the active region can be simultaneously formed of the same material, thereby simplifying the process. It can work.

In addition, in the present invention, even if word lines cross on the doped active region, an insulating film is interposed between the active region and the word lines so that each can be used as a conductive line.

Claims (42)

A first active region, a second active region, and a third active region electrically isolated from the substrate by field fields; First and second conductive lines formed across the field regions adjacent to both sides of the third active region; An interlayer insulating layer stacked on the substrate on which the first and second conductive lines are formed; A first interconnect structure electrically connecting the first active region and the second active region in the interlayer insulating film; And And a second interconnection structure electrically connecting the first conductive line and the second conductive line to the interlayer insulating layer, wherein the gap between the first conductive line and the second conductive line is interposed with the interlayer insulating layer. Interconnection structure of a semiconductor device. The method of claim 1, And the third active region and the second interconnect structure cross each other with an interlayer insulating film interposed between the first conductive line and the second conductive line. The method of claim 1, And the upper surfaces of the first and second conductive lines and the upper surfaces of the interlayer insulating layers interposed therebetween are aligned with each other. The method of claim 1, A top surface of the interlayer insulating film, a top surface of the first interconnect structure, and a top surface of the second interconnect structure are aligned with each other. The method of claim 1, Wherein the interlayer insulating film is formed of a lower interlayer insulating film and an upper interlayer insulating film having different etching rates. The method of claim 1, And an etch stop film under the interlayer insulating film. The method of claim 1, At least one of the first active region and the second active region is doped with n-type impurities. The method of claim 1, At least one of the first active region and the second active region is doped with a p-type impurity. The method of claim 1, Wherein the first interconnect structure and the second interconnect structure are of the same material formed simultaneously. The method of claim 9, Wherein said first interconnect structure and said second interconnect structure are any one selected from tungsten, aluminum, copper, titanium, titanium nitride, and tantalum nitride. The method of claim 1, And wherein the first conductive line and the second conductive line extend to cross the first active region. The method of claim 11, Wherein said first and second conductive lines across said first active region are gate electrodes of pass transistors in SRAM and said second interconnect structure is a word line. The method of claim 1, A fourth active region electrically separated by the field region; A MOS transistor formed in the fourth active region; And And a third interconnection structure electrically connecting the gate electrode and the fourth active region of the MOS transistor to the interlayer insulating layer. The method of claim 13, Wherein the first conductive line, the second conductive line, and the gate electrode are formed at the same time, and are at least one selected from a polysilicon film, a silicide film, and a tungsten film. Forming a field region defining a first active region, a second active region, and a third active region on the substrate; Forming first and second conductive lines crossing the field regions adjacent to both sides of the third active region; Forming an interlayer insulating film on the substrate on which the first and second conductive lines are formed; A first opening exposing the first active region and the second active region and a second opening exposing the top surfaces of the first conductive line and the second conductive line are formed in the interlayer insulating layer, wherein the first and second openings are formed. Leaving the interlayer insulating film in a gap between conductive lines; Filling the first opening with a conductive material to form a first interconnect structure connecting the first active region and the second active region; And Filling the second opening with a conductive material to form a second interconnect structure connecting the first conductive line and the second conductive line. The method of claim 15, Wherein the third active region and the second interconnect structure cross each other with an interlayer insulating film interposed therebetween in a gap between the first and second interconnect structures, each of which becomes a conductive line. Method of manufacturing interconnect structure. The method of claim 15, And the top surfaces of the first and second conductive lines and the top surfaces of the interlayer insulating layers interposed therebetween are horizontally aligned with each other. The method of claim 15, A top surface of the interlayer insulating film, a top surface of the first interconnect structure, and a top surface of the second interconnect structure are horizontally aligned with each other. The method of claim 15, And the interlayer insulating film is formed of a lower interlayer insulating film and an upper interlayer insulating film having different etching rates. The method of claim 15, Forming the first opening and the second opening, The interlayer insulating layer is selectively etched until the top surfaces of the first conductive line and the second conductive line are exposed, so that a gap between the first opening, the first conductive line, and the second conductive line in which the interlayer insulating layer remains on the bottom surface. Forming a second opening in which the interlayer insulating film remains; And Selectively etching the remaining interlayer insulating film on the bottom of the first opening to expose a first active region and a second active region on the bottom of the first opening. Way. The method of claim 19, Forming the first opening and the second opening, Selectively etching the upper interlayer insulating film until the surface of the lower interlayer insulating film is exposed to form a first opening and a second opening; A portion of the exposed lower interlayer insulating film may be selectively etched from the bottom of the first opening to form a thickness of the lower interlayer insulating film from the substrate to the bottom of the first opening and from the top surfaces of the first and second conductive lines. Making the thickness of the lower interlayer insulating film to the bottom of the second opening similar; And Selectively etching the lower interlayer insulating film remaining on the bottom of the first opening and the second opening using the upper interlayer insulating film as an etching mask to expose the first active region and the second active region on the bottom of the first opening; Exposing a first conductive line and a second conductive line at a bottom of the second opening, and leaving a lower interlayer insulating film therebetween. The method of claim 15, And forming an etch stop film before forming the interlayer insulating film, wherein the etch stop film is removed before forming the first opening, the second opening, and the third opening. The method of claim 15, And at least one of said first active region and said second active region further comprises doping with an n-type impurity. The method of claim 15, At least one of the first active region and the second active region further comprises doping with a p-type impurity. The method of claim 15, And wherein said first interconnect structure and said second interconnect structure are formed of the same material at the same time. The method of claim 25, Wherein said first interconnect structure and said second interconnect structure are formed from any one selected from tungsten, aluminum, copper, titanium, titanium nitride, and tantalum nitride. The method of claim 15, And wherein the first conductive line and the second conductive line extend to cross the first active region. The method of claim 27, Wherein said first and second conductive lines across said first active region are gate electrodes of a pass transistor of SRAM and said second interconnect structure is a word line. . The method of claim 15, Forming a fourth active region electrically separated by the field region; Forming a MOS transistor in the fourth active region; And And forming a third interconnect structure in the interlayer insulating film to electrically connect the gate electrode of the MOS transistor and the fourth active region. The method of claim 29, And wherein the first conductive line, the second conductive line, and the gate electrode are simultaneously formed with at least one selected from a polysilicon film, a silicide film, and a tungsten film. Forming a field region defining a first active region, a second active region, a third active region, and a fourth active region on the substrate; Stacking a gate insulating film and a first conductive film on the entire surface of the substrate; Patterning the first conductive layer and the gate insulating layer to form first conductive lines and second conductive lines on the field regions on both sides adjacent to the third active region, and interposing a gate insulating layer on the fourth active region. Forming a gate electrode; Forming a high concentration impurity region in the first active region, the second active region, the third active region and the fourth active region by using the field region and the gate electrode as a mask for ion implantation; Forming an interlayer insulating film on an entire surface of the substrate including the first conductive line, the second conductive line, and the gate electrode; Selectively etching the interlayer insulating layer to expose a first active region and a second active region, a second opening to expose top surfaces of the first conductive line and the second conductive line, and an upper surface of the gate electrode and the Forming a third opening exposing a fourth active region, wherein the interlayer insulating film remains in a gap between the first and second conductive lines; Filling the first opening, the second opening, and the third opening with a second conductive layer to connect a first interconnection structure connecting the first active region and the second active region, and connecting the first conductive line and the second conductive line. Forming a second interconnect structure and a third interconnect structure connecting said gate electrode and said fourth active region. The method of claim 31, wherein And the interlayer insulating film is formed of a lower interlayer insulating film and an upper interlayer insulating film having different etching rates. The method of claim 31, wherein Forming the first opening, the second opening, and the third opening, The interlayer insulating layer may be selectively etched until the upper surfaces of the first conductive line, the second conductive line, and the gate electrode are exposed to expose the first opening, the first conductive line, and the second conductive layer. Forming a second opening in which an interlayer insulating film remains in a gap between lines, and a third opening in which a portion of an upper surface of the gate electrode is exposed; And The remaining interlayer insulating layer is selectively etched on the first opening and the bottom of the third opening to expose the first active region and the second active region on the bottom of the first opening, and the third active region on the bottom of the third opening. A method of manufacturing an interconnect structure for a semiconductor device, comprising exposing the semiconductor device. The method of claim 32, Forming the first opening, the second opening, and the third opening, Selectively etching the upper interlayer insulating film until the surface of the lower interlayer insulating film is exposed to form a first opening, a second opening, and a third opening; A portion of the exposed lower interlayer insulating film may be selectively etched from the bottoms of the first and third openings so that the thickness of the lower interlayer insulating film from the substrate to the bottom of the first opening and the third openings and the first conductive film. Making the thickness of the lower interlayer insulating film from the pattern to the bottom of the second opening and the third opening similar; And The lower interlayer insulating film remaining on the bottom of the first opening, the second opening, and the third opening is selectively etched using the upper interlayer insulating film as an etching mask, and the first active region and the second opening are formed on the bottom of the first opening. Exposing an active region, exposing a first conductive line and a second conductive line at the bottom of the second opening, and exposing a fourth active region at the bottom of the third opening. Manufacturing method. The method of claim 31, wherein Wherein the first interconnect structure, the second interconnect structure and the third interconnect structure are simultaneously formed of the same material. 36. The method of claim 35 wherein Wherein the first interconnect structure, the second interconnect structure, and the third interconnect structure are formed of any one material selected from tungsten, aluminum, copper, titanium, titanium nitride, and tantalum nitride. Method of manufacturing the connection structure. The method of claim 31, wherein Wherein the first and second conductive lines are pass transistors of SRAM, and the second interconnect structure is a word line connecting the pass transistors. The method of claim 31, wherein At least one of the first active region and the second active region is doped n-type. The method of claim 31, wherein At least one of the first active region and the second active region is doped to a p-type. The method of claim 31, wherein Wherein the third active region and the second interconnect structure cross each other with an interlayer insulating film interposed therebetween in a gap between the first and second interconnect structures, each of which becomes a conductive line. Method of manufacturing interconnect structure. The method of claim 31, wherein And the top surfaces of the first and second conductive lines and the top surfaces of the interlayer insulating films interposed therebetween are horizontally aligned with each other. The method of claim 31, wherein A top surface of the interlayer insulating film, a top surface of the first interconnect structure, a second interconnect structure, and a top surface of the third interconnect structure are horizontally aligned with each other.