KR20010086499A - Method of forming semiconductor device with soi substrate - Google Patents

Abstract

PURPOSE: A method for forming a semiconductor device using a SOI substrate is provided to prevent the malfunction of circuits due to noise by forming an active region for wiring on a semiconductor substrate of SOI(Silicon On Insulator) structure. CONSTITUTION: An interlayer insulating film(218) is formed on the whole surface of the structure on which silicide is formed. A plurality of contact holes is formed to expose impurity regions(205n, 205p, 207a) and a gate conductive layer(210) by patterning the interlayer insulating film(218). The first contact hole(220) and the second contact hole(222) expose the first and second source/drain region(205n, 205p), and the third contact hole(224) and the fourth contact hole(226) exposes both ends of an active region(207a) for wiring.

Description

Method of forming a semiconductor device using a saw substrate {METHOD OF FORMING SEMICONDUCTOR DEVICE WITH SOI SUBSTRATE}

TECHNICAL FIELD This invention relates to the manufacturing method of a semiconductor device. Specifically, It is related with the formation method of the semiconductor device using an SOI substrate.

In order to drive unit devices such as transistors, capacitors or resistors in a semiconductor device, these devices must be electrically connected. For this purpose, metal wirings are formed. As semiconductors are highly integrated, the device area decreases and the number of required metal wirings increases. As a result, fine metal wirings are formed by stacking a plurality of layers. Up to six layers have recently been introduced and continue to increase. However, when the metal wiring layer is increased in this way, problems such as a decrease in reliability of the product, an increase in defective rate, and an increase in manufacturing cost are generated. Therefore, it is required to minimize the number of layers of the metal wiring.

On the other hand, when there is no extra metal wiring when additional unit devices need to be connected, it may be necessary to form a new metal wiring layer or modify the circuit itself to add metal wiring. In order to solve this problem, a method of connecting through an active region formed in a semiconductor substrate when a distance between unit devices is short has been proposed. However, when an active region for wiring is formed on a semiconductor substrate doped with a low concentration of N-type or P-type to form inter-element wiring, a parasitic diode is formed between the semiconductor substrate and the active region, and the circuit malfunctions due to such parasitic diodes. A problem arises. Therefore, when using a conventional semiconductor substrate, it was not possible to connect the unit devices using the active region.

FIG. 1A is a cross-sectional view showing a problem of the prior art, and FIG. 1B is an equivalent circuit diagram of Morse elements electrically connected by an active area for wiring in FIG. 1A.

Referring to FIG. 1A, an N-type well 102 is formed in a predetermined region of a lightly doped P-type semiconductor substrate 100. An isolation layer 104 is formed in a predetermined region of the semiconductor substrate 100 on which the well 102 is formed to define an active region. The active region includes an active region for a transistor and an active region for wiring. A first gate pattern 106a and a second gate pattern 106b are formed in the active region for the transistor, and spacers 107 are formed on sidewalls of the first and second gate patterns 106a and 106b, respectively. A first source / drain region 108 and a second source / drain region 110 are formed in active regions on both sides of the first and second gate patterns 106a and 106b. The first source / drain region 108 forms an N-type impurity region and the first gate pattern 106a and an NMOS transistor (Tn of FIG. 1B), and the first source / drain region 108 is formed in the N-type well 102. The two source / drain regions 110 are P-type impurity regions to form the second gate pattern 114 and the PMOS transistor (Tp of FIG. 1B). When forming the first source / drain region 108, an N-type impurity region is formed in the active region 112 for wiring at the same time. Silicides 114 are formed in the first and second gate patterns 106a and 106b, the first and second source / drain regions 108 and 110, and the wiring active region 112. The interlayer insulating layer 116 is formed on the entire surface of the resultant formed silicide 114, and the metal contact plug 118 and the metal wiring 120 are formed.

When the NMOS transistor and the PMOS transistor are electrically connected through the wiring active region 112, as shown in the equivalent circuit of FIG. 1B, the P-type semiconductor substrate 100 and the N-type wiring are used. Parasitic diodes D are formed between the active regions 112. Accordingly, when the signal containing noise passes, electrons or holes are excessively injected by the parasitic diode, causing a circuit malfunction.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method of forming a semiconductor device capable of preventing malfunction of a circuit due to noise by forming an active region for wiring on a semiconductor substrate having an SOI structure. have.

1A is a cross-sectional view of a semiconductor device according to the prior art.

1B is an equivalent circuit diagram of a semiconductor device according to the prior art.

2A to 2C are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

2D is an equivalent circuit diagram of a semiconductor device formed in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

200: buried oxide layer 100, 201: semiconductor substrate

104, 203: isolation layer 106, 211: gate pattern

107, 212: spacer 108, 110, 205: source / drain

112, 207a: Impurity regions for wiring 114, 216: silicide

116, 218: interlayer insulating film 220, 222, 224, 226: contact hole

118, 230, 232, 234, 236: metal contact plug

120, 240, 242: metal wiring

(Configuration)

According to the present invention for achieving the above object, a method of forming a semiconductor device using an SOI substrate comprises the steps of: forming a device isolation film defining a plurality of active regions electrically isolated from a semiconductor layer of the SOI substrate; Forming a first device and a second device in a first active area and a second active area of the plurality of active areas, respectively; Forming an interconnection impurity region of a first conductivity type or a second conductivity type in a third active region of the plurality of active regions; Forming an interlayer insulating film on an entire surface of the resultant product in which the first device, the second device, and the wiring impurity region are formed; Patterning the interlayer insulating layer to form first and second contact holes for exposing the first and second elements, respectively, and forming third and fourth contact holes for exposing both ends of the wiring active region, respectively. Doing; And a first metal wiring electrically connecting the first element and the wiring active region through the first and third contact holes, and the second element and the wiring active region through the second and fourth contact holes. Forming a second metal wire to be electrically connected.

Preferably, the first and second devices are NMOS transistors and PMOS transistors, and the first and second contact holes expose the drain region of the NMOS transistor and the drain region of the PMOS transistor, respectively.

It is preferable that one of the first conductivity type and the second conductivity type is N type and the other is P type.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2D.

2A to 2C are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

2D is an equivalent circuit diagram of a semiconductor device formed in accordance with an embodiment of the present invention.

Referring to FIG. 2A, an isolation layer 203 is formed to define a plurality of active regions electrically isolated from a semiconductor layer 201 of a silicon on insulator (SOI) substrate having a buried oxide layer 200. . The plurality of active regions includes an active region 205 for a device and an active region 207 for a wiring. The isolation layer 203 is formed by a conventional method such as shallow trench isolation (STI).

Referring to FIG. 2B, a gate insulating layer 209 and a gate electrode 210 are sequentially deposited on the entire surface of the semiconductor substrate, and then patterned to form a first gate pattern 211n and a second gate on the active region 205 for the device. The pattern 211p is formed. An insulating layer is formed on the entire surface of the resultant material on which the first and second gate patterns 211n and 211p are formed, and then anisotropically etched to form spacers 212 on sidewalls of the first and second gate patterns 211n and 211p, respectively. .

Impurity ions of a first conductivity type are implanted into active regions on both sides of the first gate pattern 211n to form a first source / drain region 205n and second active regions on both sides of the second gate pattern 212p. The second source / drain region 205p is formed by injecting biconductive impurities. For example, N-type impurity ions are implanted on both sides of the first gate pattern 212n to form an N-type impurity region, and P-type impurity ions are implanted on both sides of the second gate pattern p. To form a P-type impurity region. The first gate pattern and the first source / drain region form a first device, eg, an NMOS transistor (T1 in FIG. 2D), and the second gate pattern and the second source / drain region are a second device, eg For example, a PMOS transistor (T2 in FIG. 2D) is formed.

When the first or second source / drain regions 205n and 205p are formed, an interconnection impurity region 207a is formed at the same time. That is, when an impurity is injected into the first source / drain region 205n, the wiring active region 207 is opened to form a first conductivity type impurity region. Alternatively, when an impurity is injected into the second source / drain region 205p, the wiring active region 207 is opened to form a second conductivity type impurity region. Therefore, the impurity concentration of the wiring impurity region 207a is formed to be the same as the impurity concentration of the first or second source / drain regions 205n and 205p. For example, the wiring impurity region 207a is formed by implanting N-type or P-type impurity ions with a high dose of about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ atoms / cm ² .

Silicide 216 is selectively formed on the impurity regions 205n, 205p, and 207a and the gate conductive layer 210. The silicide 216 is formed by a salicide process. That is, a metal such as cobalt, titanium, nickel, and the like is deposited on the entire surface of the semiconductor substrate including the impurity regions 205n, 205p, and 207a and the gate conductive layer 210, and then heat-treated. Then, silicide is selectively formed in a portion where silicon is exposed, that is, the impurity regions 205n, 205p, and 207a and the gate conductive layer 210. In this way, the silicide may be lowered to improve electrical characteristics.

Referring to FIG. 2C, an interlayer insulating layer 218 is formed on the entire surface of the resultant formed silicide 216. The interlayer insulating layer 218 is patterned to form a plurality of contact holes exposing the impurity regions 205n, 205p, and 207a and the gate conductive layer 210. The plurality of contact holes include a first contact hole 220 and a second contact hole 222 exposing the first and second source / drain regions 205n and 205p, and the wiring active region 207a. And a third contact hole 224 and a fourth contact hole 226 exposing both ends of the third contact hole 224. For example, the first contact hole 220 and the second contact hole 222 may expose the drain region of the NMOS transistor and the drain region of the PMOS transistor, respectively.

Filling the plurality of contact holes with a conductive material to form a plurality of contact plugs including a first contact plug 230, a second contact plug 232, a third contact plug 234, and a fourth contact plug 236. do. A metal wiring layer is formed on the interlayer insulating film 218 including the plurality of contact plugs. The metal wiring layer is patterned to form a plurality of metal wirings. The plurality of metal wires may include a first metal wire 240 electrically connecting the first element and the wiring active region 207a through the first contact plug 230 and the third contact plug 234. The second metal wire 242 electrically connects the second element and the wiring active region 207a through the second contact plug 232 and the fourth contact plug 236.

According to the present invention, since the wiring active region 207a is surrounded by the buried oxide layer 200 and the device isolation layer 203, as shown in the equivalent circuit diagram of FIG. 2D, the wiring active region 207a. The parasitic diode is not formed when the adjacent devices are electrically connected through. Therefore, wiring between unit elements is possible through the active region formed on the semiconductor substrate.

The present invention has the effect of enabling interconnection between devices without forming an additional metallization layer by electrically connecting the unit devices through the active area for wiring formed on the semiconductor substrate of the SOI structure.

Claims (3)

Forming a device isolation film defining a plurality of active regions electrically isolated from the semiconductor layer of the SOI substrate; Forming a first device and a second device in a first active area and a second active area of the plurality of active areas, respectively; Forming an interconnection impurity region of a first conductivity type or a second conductivity type in a third active region of the plurality of active regions; Forming an interlayer insulating film on an entire surface of the resultant product in which the first device, the second device, and the wiring impurity region are formed; Patterning the interlayer insulating layer to form first and second contact holes for exposing the first and second elements, respectively, and forming third and fourth contact holes for exposing both ends of the wiring active region, respectively. Doing; And First metal wires electrically connecting the first element and the wiring active region through the first and third contact holes, and electrically connecting the second element and the wiring active region through the second and fourth contact holes. Forming a second metal wiring to be connected to each other. The method of claim 1, Wherein the first and second elements are NMOS transistors and PMOS transistors, respectively, and the first and second contact holes expose a drain region of the NMOS transistor and a drain region of the PMOS transistor, respectively. Way. The method of claim 1, Wherein one of said first conductivity type and said second conductivity type is N type and the other is P type.