KR20010054509A - Method of fabricating semiconductor devices - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to control a latch-up phenomenon, by forming an inversion channel so that a voltage between a base and an emitter of an npn-type parasitic bipolar transistor increases. CONSTITUTION: A gate insulation layer is formed on a semiconductor substrate(20) of the first conductivity type. A gate(22) is formed on the gate insulation layer. An insulation material as a passivation layer is formed on an exposed surface of the gate. An electrode(24) for forming a channel is formed on the gate insulation layer and the passivation layer located on a source formation region of the gate, and a side surface of the gate adjacent to a drain region is exposed. Low density impurity ions of the second conductivity type are doped into only the drain region of the gate. A gate sidewall spacer(26) is formed on a side surface of the exposed gate. High density impurity ions of the second conductivity type are doped into the source region and the drain region of the semiconductor substrate. An insulation layer is formed on the entire surface of the semiconductor substrate.

Description

Method of fabricating semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a transistor used as a source of an NMOS device is formed by forming an inversion channel by applying a predetermined voltage to an active region of a substrate corresponding to a source region. Thus, the semiconductor device is designed to improve the latch-up phenomenon by preventing the turn-on of parasitic bipolar transistors formed on the substrate including neighboring wells by decreasing the junction depth of the source, thereby increasing the junction depth of the well. It relates to a transistor manufacturing method.

As the semiconductor device is highly integrated, each cell becomes finer and the internal electric field strength is increased. This increase in electric field strength causes a hot-carrier effect in which the carrier of the channel region is accelerated and injected into the gate oxide layer in the depletion layer near the drain during operation of the device. The carrier injected into the gate oxide film creates a level at the interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage (V _TH ) or decreasing the mutual conductance, thereby degrading device characteristics. Therefore, in order to reduce the deterioration of device characteristics due to the hot-carrier effect, a structure in which the drain structure is changed such as a lightly doped drain (LDD) or the like should be used.

1A to 1C are cross-sectional views of a transistor manufacturing process of a lightly doped drain (LDD) structure of a semiconductor device according to the prior art.

Referring to FIG. 1A, a field oxide film (not shown) is formed on a predetermined portion of the surface of a P-type silicon substrate 10, which is a semiconductor substrate, by a conventional selective oxidation method such as local oxide of silicon (LOCOS), shallow trench isolation (STI), or the like. ) To define the active and field regions of the device.

Then, the surface of the semiconductor substrate 10 is thermally oxidized to form an oxide film for a gate insulating film.

The polysilicon layer doped on the oxide film for gate insulating film is deposited by chemical vapor deposition (hereinafter, referred to as CVD).

The polysilicon layer and the oxide film are then patterned by photolithography to define the gate 12 and the gate oxide film 11. At this time, the gate size is the same as the gate pattern mask pattern size.

A low concentration impurity ion buried layer 13 for forming an LDD structure is formed by implanting N-type impurities at low concentration into the exposed portion of the semiconductor substrate 10 using the gate 12 as an ion implantation mask. .

Referring to FIG. 1B, sidewall spacers 14 are formed as insulating layers on side surfaces of the gate 12 and the gate oxide layer 11. At this time, the sidewall spacers 14 are formed by depositing silicon oxide on the substrate by chemical vapor deposition and then etching back so that the gate 12 and the semiconductor substrate 10 are exposed.

In addition, by using the gate 12 and the sidewall spacers 14 as ion implantation masks, N-type impurities are implanted at a high concentration into the exposed active regions of the semiconductor substrate 10 to thereby be used as source and drain regions. An ion buried layer 15 is formed. At this time, the high concentration impurity ion buried layer 15 and the low concentration impurity ion buried layer 13 are formed to overlap each other.

Referring to FIG. 1C, the substrate 10 including the high concentration impurity ion buried layer 15 and the low concentration impurity ion buried layer 13 is subjected to a thermal process such as annealing to plate the impurity ion buried layers 13 and 15. The traces are sufficiently diffused to form a source / drain pittus composed of the low concentration impurity diffusion region 130 and the high concentration impurity diffusion region 150. Thus, an NMOS transistor is manufactured.

Then, the interlayer dielectric layer 14 is formed of an interlayer dielectric (ILD) layer such as an oxide film on the substrate including the transistor, and then a predetermined portion of the interlayer dielectric layer is removed by photolithography to form a high concentration impurity diffusion region 150. A pair of contact holes are formed to expose the gap.

Next, a conductive layer is formed to fill the contact hole with a conductive material such as tungsten and aluminum, and then patterned to form a drain electrode 17 and a source electrode 18.

As described above, the MOS transistor manufactured according to the prior art has a parasitic bipolar transistor (BJT) having an npn structure having a high concentration impurity diffusion region for an NMOS source, an n-type well formed with a p-type substrate, and a PMOS in a CMOS structure in which NMOS and PMOS are simultaneously formed. ) Will inevitably form.

Therefore, as the semiconductor device is highly integrated and the size of the transistor is reduced, the length of the gate is shortened and the length of the channel is decreased, thereby increasing the substrate current into the p-type substrate bulk due to the injection of hot-carriers. The increased substrate current vaporizes the voltage potential of the p-type substrate, turning on the npn-type bipolar transistor.

Subsequently, the turned-on bipolar transistor lowers the voltage potential of the n-type well, which in turn turns on the pnp-type bipolar transistor composed of a high concentration impurity diffusion filtration N-type well and a p-type substrate of the PMOS. Since the potential of the substrate is increased to cause a latch, and the amount of current is sharply increased, the device is eventually destroyed.

Accordingly, the semiconductor device manufacturing method according to the related art has a problem in that the critical dimension of the gate is reduced as the device is highly integrated, thereby causing a latch-up phenomenon, thereby lowering the reliability of the semiconductor device manufactured.

Accordingly, an object of the present invention is to form an inversion channel by applying a predetermined voltage to an active region of a substrate corresponding to a source region, thereby manufacturing a transistor used as a source of an NMOS device, thereby reducing the junction depth of the source. It provides a method of manufacturing a transistor of a semiconductor device to improve the latch-up phenomenon by preventing the turn-on of the parasitic bipolar transistor formed on the substrate including the neighboring well by reducing the relatively increase the depth of the well of the well. have.

A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of forming a gate insulating film on the first conductive semiconductor substrate, forming a gate on the gate insulating film, and an insulator on the exposed surface of the gate Forming a passivation layer, forming a channel forming electrode on the gate insulating layer and the passivation layer on the source forming region of the gate, and exposing side surfaces of the gate adjacent to the drain region; Low concentration doping with impurity ions, forming gate sidewall spacers on the side of the exposed gate, high concentration doping of the source and drain regions of the semiconductor substrate with the second conductivity type impurity ions, and It comprises a step of forming an insulating layer on the front surface.

1A to 1C are cross-sectional views of a transistor manufacturing process of a semiconductor device according to the prior art.

2A to 2D are cross-sectional views of a transistor manufacturing process of a semiconductor device according to the present invention.

According to the present invention, in the fabrication of a MOS device having an LDD or DDD structure, as the structure of these devices is further refined, the latch-up phenomenon due to an increase in leakage current in the transistor makes the operation of the parasitic bipolar transistor of the npn structure difficult. Prevent destruction and improve reliability.

In the present invention, instead of forming a low concentration impurity diffusion region for a source of an NMOS transistor, a Vcc voltage applied to a PMOS source is applied to a corresponding portion to form an inversion layer by applying a voltage, thereby increasing the channel length of the device, thereby latching up. To prevent. That is, the operation of the bipolar transistor is suppressed by increasing the band width of the base of the bipolar transistor of the vertical npn structure.

In other words, by omitting n-type impurity ion implantation in the source region of the NMOS transistor and forming an inversion layer with an upper Vcc voltage, the width of the n + layer is reduced, so that the bandwidth of the base of the p-type substrate, i.e., the npn bipolar transistor, is relatively high. As a result, the operation of the npn bipolar transistor becomes difficult, and latch-up occurrence is suppressed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views of the transistor manufacturing process of the semiconductor device according to the present invention as viewed in the channel length direction.

Referring to FIG. 2A, a field oxide film (not shown) is formed on a predetermined portion of the surface of a P-type silicon substrate 20, which is a semiconductor substrate, by a conventional selective oxidation method such as LOCOS (Local Oxidation of Silicon) or STI (shallow trench isolation). ) To define the active and field regions of the device.

Next, the surface of the semiconductor substrate 20 is thermally oxidized to form an oxide film 21 for a gate insulating film.

The doped polysilicon layer on the oxide insulating film 21 for gate insulating film is deposited by chemical vapor deposition (hereinafter, referred to as CVD).

The polysilicon layer is then patterned by photolithography to define a gate 22 made of the remaining polycrystalline silicon layer 22.

The exposed surface of the gate 22 is oxidized to form a protective film 23 having a predetermined thickness. In this case, an oxide film 21 for forming a gate is formed on the surface of the active region of the substrate 21, and the passivation layer 23 is formed to have a sufficient thickness for sufficient insulation with a conductive layer for forming an auxiliary channel to be formed later.

Referring to FIG. 2B, the conductive layer is formed by chemical vapor deposition using polysilicon doped on the oxide film 21 including the surface of the protective film 23 formed on the surface of the gate 22.

A photoresist is applied on the conductive layer, followed by exposure and development, to form a photoresist pattern (not shown) that simultaneously exposes a portion over the gate 22 and the top of the source formation region.

Then, between the conductive layer of the portion not protected by the photoresist pattern, the protective film, and the oxide film on the substrate are sequentially removed by anisotropic etching between the channel forming electrode 24 made of the remaining conductive layer and the gate 22 below. The interposing protective film 230 and the gate insulating film 210 are formed. In this case, the gate insulating film 210 remains over the gate 22 and the channel forming electrode 24.

Therefore, the surface of the gate 22 that does not overlap the channel forming electrode 24 is exposed, and the remaining active region of the substrate 20 is exposed.

In order to form a lightly doped region in the drain formation region of the substrate 20, an ion implantation mask is formed on the substrate to expose only the lightly doped region formation region, and then ion implantation using the n-type impurities such as As and P is performed. By using ions at a low concentration on the exposed portion of the substrate to form a low concentration ion buried layer 25, the ion implantation mask is removed. Therefore, unlike the prior art in which the LDD region is formed in both the source and drain formation regions, the low concentration ion buried layer 25 is formed only in the drain region in the embodiment of the present invention. This is to increase the bandwidth of the base of the npn type parasitic bipolar transistor to make it difficult to turn on.

Referring to FIG. 2C, sidewall spacers 26 are formed as insulating layers on side surfaces of the gate 22 and the gate insulating layer 210. In this case, the sidewall spacers 26 are formed to secure a lightly doped LDD region, and after the silicon oxide is deposited on the substrate by chemical vapor deposition, the upper surface of the gate 22 and the semiconductor substrate 20 are exposed. It is formed by etchback.

Subsequently, a high concentration of n-type impurity ions such as As and P are implanted in the entire surface of the exposed substrate 20 without an ion implantation mask to form a high concentration of impurity ion buried layer 27 in the source / drain formation region of the substrate. do. At this time, since the low concentration impurity ion buried layer 25 is formed in the drain formation region, it partially overlaps with the high concentration impurity ion buried layer 25.

Referring to FIG. 2D, a thermal process such as annealing is performed on the substrate 20 including the high concentration impurity ion buried layer 27 and the low concentration impurity ion buried layer 25 to plate the impurity ion buried layers 25 and 27. The traces are sufficiently diffused to form a source / drain section including the low concentration impurity diffusion region 250 and the high concentration impurity diffusion regions 270 and 271. In this case, the drain includes the low concentration impurity diffusion region 250 and the high concentration impurity diffusion region 270, but the source includes only the high concentration impurity diffusion region 271.

However, in the embodiment of the present invention, the channel forming electrode 24 is formed on the source side, and a predetermined voltage is applied to the electrode 24 to form an inversion layer in the active region below the overall transistor. Extend the channel length.

Thus, an NMOS transistor is manufactured.

Then, the interlayer dielectric layer 28 is formed of an interlayer dielectric (ILD) layer such as an oxide film on the substrate including the transistor, and then a predetermined portion of the interlayer dielectric layer is removed by photolithography to form high concentration impurity diffusion regions 270 and 271. A pair of contact holes for exposing the via and via holes for exposing a portion of the surface of the channel forming electrode 24 are simultaneously formed.

Next, a conductive layer is formed to fill the contact hole and the via hole with a conductive material such as tungsten and then patterned to form the drain plug 30, the source plug 31, and the channel forming electrode plug 29.

Then, a conductive layer is formed of a metal such as aluminum on the interlayer insulating layer 28 so as to cover the surfaces of the plugs 29, 30, and 31, and then patterned to form a wiring connected to a predetermined voltage source. In this case, the wiring connected to the channel forming electrode plug 29 may be connected to the Vcc voltage of the PMOS device in the CMOS.

Therefore, during device operation, the drain of the transistor is similar to the structure of the prior art, and the source portion forms an inversion layer by a predetermined voltage applied to the channel forming electrode 24 by using the operation principle of the gate. By forming a channel, a sudden increase in substrate current is prevented.

Accordingly, the present invention can improve the reliability of the device by suppressing the latch-up phenomenon by increasing the voltage between the base and the emitter of the npn type parasitic bipolar transistor by forming an inversion layer for the source of the NMOS transistor. There is an advantage.

Claims (5)

Forming a gate insulating film on the first conductive semiconductor substrate; Forming a gate on the gate insulating film; Forming a protective film on an exposed surface of the gate with an insulator; Forming a channel forming electrode on the gate insulating layer and the passivation layer on the source forming region of the gate and exposing side surfaces of the gate adjacent to the drain region; Low concentration doping with a second conductivity type impurity ion only in the drain region of the gate; Forming a gate sidewall spacer on the exposed side of the gate; Heavily doping the source and drain regions of the semiconductor substrate with the second conductivity type impurity ions; Forming an insulating layer on the entire surface of the semiconductor substrate. The method of claim 1, wherein the channel forming electrode is formed to partially overlap the gate. The method of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type. The method of claim 1, further comprising: removing a predetermined portion of the insulating layer to form a pair of contact holes exposing the highly doped semiconductor substrate and an opening exposing a surface of the channel forming electrode; Forming a plug filling the contact hole and the opening with a conductive material; And forming wirings on the insulating layer so as to contact the plug formed in the opening and the plug formed in the contact hole, respectively. The method of claim 4, wherein the wiring contacting the plug formed in the opening is formed to be connected to a voltage capable of forming an inversion layer in the source region of the semiconductor substrate located under the channel forming electrode. Method of manufacturing a semiconductor device.