KR19980013925A - Semiconductor device and manufacturing method - Google Patents

Abstract

A semiconductor device disclosed to reduce a collector resistance and to provide a high-performance bipolar transistor includes: a semiconductor layer formed on a substrate of a first conductivity type; A well region of a second conductivity type formed at a predetermined position on a surface of the semiconductor layer and having an impurity concentration lowered vertically downward from the surface; A buried region of a second conductivity type formed adjacent to the well region and the substrate and having an impurity concentration higher than that of the adjacent portion of the well region; An opening formed in the semiconductor layer to expose a predetermined portion of the buried region; A conductive pad formed in the opening to be in contact with the exposed region of the embedded region and extending to a predetermined portion of the opening peripheral portion including the opening, the conductive pad having a uniform thickness; And a metal electrode which is in contact with an extension of the conductive pad.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a bipolar transistor and a manufacturing method thereof.

In recent years, BiCMOS technology, which combines CMOS technology with advantages of high integration and low power consumption and Bifora technology which has advantages of high-speed operation, is actively studied. BiCMOS technology is based on CMOS technology, and how to achieve the best high-performance bipolar technology at the same time with minimal additional process is a major problem.

On the other hand, in a BiCMOS gate circuit that drives a high-capacity load, the collector resistance of the bipolar transistor greatly affects the gate delay. Therefore, in order to realize a high-performance BiCMOS circuit, the collector resistance must be minimized. In order to reduce the collector resistance, a deep N + collector contact technique has been disclosed in the prior art as shown in Fig. However, the deep N + collector contact technique must maintain a relatively large collector base spacing in order to prevent degradation of the collector-base breakdown voltage due to lateral diffusion of impurities during deep N + region formation. Such a spacing constraint limits the reduction in the design dimensions of the bipolar transistor, thereby hindering high integration. In order to solve such a problem, a deep N + polysilicon plug contact technique shown in FIG. 2 has been proposed. This is described in Diegest of Technical Papers, 1988 International Electron Devices Meeting. pp. 756-759. December 1988. and IEDM 90. pp. 493-496. This deep N + polysilicon plug contact technique has the advantage of suppressing the lateral diffusion of N + impurities by the sidewall dielectric film and reducing the design dimensions of the transistor. However, deeper N + polysilicon plug contact technologies have become complicated due to the addition of a collector trench etch process, side wall spacer formation for lateral diffusion prevention, and polysilicon trench buried process for collector contact of a bipolar transistor, regardless of CMOS process . In addition, voids may be formed when the trench is buried in polysilicon. This void generation increases the collector resistance.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of reducing a collector resistance and capable of providing a high-performance bipolar transistor, and a method of manufacturing the same.

Another object of the present invention is to provide a high-performance BiCMOS SRAM semiconductor device and a method of manufacturing the same by adding a minimum number of processes to an SRAM semiconductor device based on a CMOS process and a manufacturing process thereof.

In order to achieve the object of the present invention, a semiconductor device of the present invention includes: a semiconductor layer of a predetermined conduction type formed on a semiconductor substrate of a first conductivity type; A well region of a second conductivity type formed at a predetermined position on a surface of the semiconductor layer and having an impurity concentration lowered vertically downward from the surface; A buried region of a second conductivity type formed adjacent to the well region and the semiconductor substrate and having an impurity concentration higher than that of the adjacent portion of the well region; An opening formed in the semiconductor layer to expose a predetermined portion of the buried region; A conductive pad formed in the opening to be in contact with the exposed region of the embedded region and extending to a predetermined portion of the opening peripheral portion including the opening, the conductive pad having a uniform thickness; And a metal electrode which is in contact with an extension of the conductive pad.

A manufacturing method of a BiCMOS semiconductor device having a CMOS transistor and a bipolar transistor on the same wafer includes the steps of forming a first embedding layer of a first conductivity type and a second embedding layer of a first conductivity type on a surface of a semiconductor substrate of a first conductivity type, Forming a second embedding layer of a second type; Growing an epitaxial layer on a surface of a second well of the second conductivity type on the first and second buried layers; Forming a first well of the first conduction type and a second well of the second conduction type in the epitaxial layer; A PMOS transistor or a bipolar transistor is formed in the vicinity of the surface of the second well of the second conduction type on the second buried layer of the second conduction type and the PMOS transistor or the bipolar transistor is formed in the vicinity of the surface of the second conduction type of the first conduction type Forming an NMOS transistor in the vicinity of the surface of one well; Forming an opening for a second buried layer contact in a second well where the bipolar transistor is formed after forming the transistor; A conductive material is deposited on the entire surface after the opening is formed and the deposited conductive material is patterned to simultaneously provide an interconnect and a conductive pad.

1 is a vertical cross-sectional view of a deep impurity contact-type NPN bipolar transistor with a conventional impurity doped buried layer.

2 is a vertical cross-sectional view of a conventional polysilicon plug contact-type NPN bipolar transistor having an impurity doped buried layer.

3 is a vertical cross-sectional view of a conductive pad contact bipolar transistor having an impurity doped buried layer in accordance with an embodiment of the present invention.

FIGS. 4 to 19 are views showing a manufacturing process sequence of the semiconductor device of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

3 illustrates a cross-sectional structure of a bipolar transistor using the conductive pad contact contact technique according to the present invention. In FIG. 3, reference numeral 10 denotes a P-type semiconductor substrate, 12 denotes an N + buried layer, 16 denotes an N well, 18 denotes a P well, 22 denotes a P base or an internal base, 24 denotes a P + base or an external base, Emitter electrode, numeral 34 is a collector electrode, numeral 36 is an opening, numeral 44 is polysilicon doped with N ++, numeral 46 is a metal silicide, numeral 48 is an extension electrode, , And 50 is a conductive pad. As shown in FIG. 3, in the present invention, by forming a contact with the conductive pad 50 between the N + buried layer 12 of the bipolar transistor and the collector electrode 34, the conventional N + doped polysilicon plug contact technology It is possible to reduce the collector contact resistance by a simple process. Particularly, the conductive pad 50 is formed of a polycide structure that is a laminated structure of the N + doped polysilicon 44 and the low-resistance metal silicide 46, for example, W, Ti, Ta, It is possible to further reduce the resistance as compared with the plug contact technology in which there is a possibility of occurrence of the problem. In addition, the conductive pad contact technology of the present invention does not require the spacer diffusion barrier film for lateral diffusion used in the conventional plug contact technology to be formed on the inner wall of the opening 36. This is because, in the conventional method, since the plug is formed before forming the base, the impurity is diffused sideways from the N + doped polysilicon plug by the subsequent heat treatment process to prevent narrowing the interval between the base collectors, . However, in the present invention, after forming the base, the conductive pad 50 is formed together with the polysilicon 52 for the emitters and the metal silicide 54 for emitters, thereby eliminating the influence of the subsequent trench definition and simplifying the process have. The emitter polysilicon 52 and the emitter metal silicide 54 are used for interconnection interconnection and SRAM cell formation for electrical connection between elements in the fabrication of an SRAM semiconductor device, The present invention can simplify the BiCMOS process because the conductive pad can be formed without any additional process in the manufacturing process of the SRAM semiconductor device.

The details of the present invention will be described in detail with reference to FIGS. 4 to 19.

4, a pad oxide film 1a and a nitride film 1b are sequentially formed on a low-concentration P-type substrate 100, and a laminate of a pad oxide film 1a and a nitride film 1b is formed for a normal photo- After the P embedding area is opened by patterning the structure, a P-type impurity such as boron is implanted.

Referring to FIG. 5, when the thermal oxidation process is performed after the P-type impurity is implanted, a thick oxide film 3 is formed only on the surface of the P-buried region without the nitride film 1b, and the P- Type impurity layers 102, 102a, and 102b are formed. Subsequently, the nitride film 3 is removed, and the oxide film 3 is used as a mask to ion-implant N-type impurities such as acenic at a high concentration. 6, the P-type impurity layers 102, 102a, 102b and the N + -type impurity layers 104, 104a, 104b are removed as shown in FIG. 6 .

Referring to FIG. 7, on the substrate surface on which the impurity layers are formed, 1.51 m < / RTI > epitaxial layer 5 (hereinafter referred to as an epi layer) is grown. The P type impurity layers 102, 102a and 102b and the N + type impurity layers 104, 104a and 104b between the substrate 100 and the epi layer 5 become the P type buried layer and the N + buried layer, respectively.

FIG. 8 shows the formation of the N-type impurity layers 106, 106a and 106b and the P-type impurity layers 108, 108a and 108b using a normal LOCOS process. The N-type impurity layers 106, 106a and 106b are formed on the N + buried layers 104 and 104a and the P-type impurity layers 108a and 108b are formed on the P-type buried layers 102 and 102a And 102b. The N-type impurity layer is an N-well region in which the PMOS transistor 106a region and the bipolar transistor 106 region are to be formed. The P-type impurity layer is formed in the NMOS transistor 108a region as a P- And the sRAM memory element 108b are to be formed.

9 is a cross-sectional view of a field oxide film 110 for electrical insulation between elements in a part of the epi layer where the N wells 106, 106a and 106b and the P wells 108, 108a and 108b are formed, (See FIG.

Referring to FIG. 10, polysilicon 114, 118, and 122 are coated on the resultant, and then metal silicide 116, 120, and 124 are applied on the entire surface. Next, the polysilicon 114, 118, 122 and the metal silicide 116, 120, 124 are patterned in a specific shape using a normal photolithography process. Here, some polysilicon and metal silicides 114 and 116 (hereinafter referred to as 'polycide') are used as a gate for the MOS structure of the MOS transistor together with the gate oxide film 112, Is used as a conductive layer for electrical connection between elements, and another part of the polycides 118 and 120 is used as a protective film for protecting the active region of the bipolar transistor.

Referring to FIG. 11, Phosphorus ions are ion-implanted at an dose of 3.0E13 # / cm 2 and an ion implantation energy of 40 KeV to form an N-type LDD without using a photolithography process on the entire surface of the resultant structure. At this time, the protective layers 118 and 120 of the bipolar transistor serve as a mask for preventing the phosphorus ions from being injected into the active region of the bipolar transistor. Then, all regions except the active region of the PMOS transistor are coated with a photoresist film by using a normal photolithography process, and then BF 2 ions are ion-implanted at a dose of 4.4E13 # / cm 2 and an ion implantation energy of 40 KeV, for example, Thereby forming the LDD 126. Since the dose amount of BF2 ions for forming the P-type LDD 126 is larger than the dose amount of the phosphorus ions for forming the N-type LDD 128, the N-type LDD 128 is formed in the NMOS transistor, A P-type LDD 126 is formed.

12, a spacer is formed on the sidewalls of the polycide films 114, 116, 118, 120, 122, and 124 by applying an oxide film to a thickness of about 3000 Å and then performing an anisotropic dry etching process. This is for forming the LDD structure of the MOS transistor. At this time, the polycide protection films 118 and 120 of the bipolar transistor prevent the active region of the bipolar transistor from being damaged during the anisotropic dry etching process.

Referring to FIG. 13, a photoresist film (not shown) is formed using a conventional photolithography process so that the first side connection window 132a for connecting the collector side power supply of the bipolar transistor to the polycide side protection films 118 and 120 of FIG. The polycide films 118 and 120 are removed and the single crystal silicon in the region of the first collector power supply connection window 132a is etched as well. It is one of the processes.

Referring to FIG. 14, boron ions are implanted at a dosage of 2.0E13 # / cm 2 and an ion implantation energy of 50 KeV to remove the P-type internal base immediately after the etching process, Type impurity layer 134 is formed. At this time, the P-type impurity layer 134 may be formed in the region of the first collector power connection window 132a of the bipolar transistor. This is because the P-type impurity layer in the region of the first collector power supply connection window 132a is removed as well as the N-type impurity is implanted at a high concentration as the subsequent process proceeds.

15, after removing the photoresist film 7 from the resultant product, a photoresist film is formed on the resultant using a conventional photolithography process so that the NMOS transistor region is exposed. Then, E15 # 15 / cm2 and an ion implantation energy of 40 KeV to form the source and drain 136 of the NMOS transistor and the source and drain 138 of the NMOS transistor for the SRAM memory element. After removing the photoresist film, a photoresist film is formed using a normal photolithography process so that the region of the first collector power supply connection window 132a of the bipolar transistor is exposed. Then, phosphorus ions are implanted at a dose of 5.0E15 / And an implantation energy of 80 KeV is injected to form a deep N + type impurity layer 140a. This deep N + type impurity layer 140a is vertically adjacent to the N + buried layer 104b and affects the collector resistance of the bipolar transistor. The deep N + type impurity layer 140a is also formed in an ESD (Electro Static Discharge) preventing NMOS transistor (not shown). After removing the photoresist film, a photoresist film is formed using a normal photolithography process so that the PMOS transistor region and a part 144 of the base region of the bipolar transistor are exposed. Then, BF2 ions are implanted at a dose of 5.0E15 # / cm2 Ions are implanted at an ion implantation energy of 30 KeV to form the source and drain regions of the PMOS transistor and the external base region 144 of the bipolar transistor.

Referring to FIG. 16, an oxide film 146 is formed on the entire surface of the resultant structure to a thickness of about 1000 Å, and then a normal photolithography process is performed to form a first collector power connection window 132b region of the bipolar transistor The oxide film of the exposed region where the photoresist film is formed is removed so as to expose the region of the connection window 148a and the poly-rod resistor for the resistance type ESRAM memory element. At this time, the connection window 148a simultaneously exposes the polycides 122 and 124 used as a conductive layer for electrical connection between elements and the drain region of the NMOS transistor for the SRAM memory device, and the first collector power supply connection The oxide film 146 in the window 132b region is removed to expose the single crystal silicon.

17, a polycrystalline silicon 150 is applied to a thickness of about 500 Å and a photoresist film is formed in a specific shape using a conventional photolithography process to form the polycrystalline silicon 150 into a predetermined shape. The single crystal silicon in the region of the polycrystalline silicon and the first collector power supply contact hole 2 (FIG. 16B) is also etched at the same time to form a first collector power connection window 132c ), Which is one of the core processes of the present invention. The polycrystalline silicon 150 is used as a resistor used in a load resistance of a poly resistance type SRAM memory device, a power supply wiring, and a circuit. The polysilicon 150 is formed so as to expose a connection window 148b, a power supply wiring, A photoresist film is formed and Phosphorus ions are implanted, for example, at a dose amount of 4.0E15 # / cm2 and an ion implantation energy of 30 KeV to enable connection of the connection window 148b, and power supply wiring and resistance are formed. On the other hand, the polycrystalline polysilicon 150 in the region where the ion implantation is not performed becomes the load resistance of the Slammemory memory element.

18 shows a step of forming a conductive pad for power connection between an electric ground power terminal of the resistive SRAM memory element and the ground wiring and the emitter and collector of the bipolar transistor. The oxide film 146b for interlayer insulation is formed to have a thickness of about 2000 Å And then the region 152a where the emitter of the bipolar transistor is to be formed, the region of the first collector power connection window 132d of the bipolar transistor, and the ground power source region 154a of the Slammemory device are exposed, After the oxide film 146, 146a, 146b of the exposed region is formed, a polysilicon film 156, 160, 164 is deposited on the entire surface of the resultant to a thickness of 1000 angstroms. # / cm < 2 > and an ion implantation energy of 100 KeV, and a metal silicide such as tungsten silicide 158, 162, or 166 is applied to the entire surface of the resultant to a thickness of 1500 A, And by shaping the polysilicon (156, 160, 164) and metal silicide (158, 162, 166) of said laminated structure in a predetermined shape.

As ions implanted into the polysilicon 156, 160, and 164 are diffused into silicon while thermal processing proceeds in a subsequent process to form an emitter of the bipolar transistor. The concentration of the deep N + type impurity layer 140c in FIG. Which helps to reduce the collector resistance of the bipolar transistor. Thus, some polysilicon and metal silicides 156 and 158 (hereinafter referred to as " polycides ") form the polyimide structure of the bar transistor and the other portions of the polycides 160 and 162 are connected to the collector of the bipolar transistor And another part of the polycides 164 and 166 are used as the electric ground power terminal and the ground wiring of the resistive SRAM memory element.

FIG. 19 shows a process of forming the respective electrodes of the MOS transistor and the bipolar transistor. The HTO (Hot Temperature Oxide) layer is laminated on the resultant, and the BPSG (Boro-Phosphorus Silicate Glass) Next, the HTO and BPSG films on the regions 172, 174, 176, 178, 180, and 181 where the respective electrodes are to be formed are removed using a normal photolithography process to form a connection window, The conductive materials 182, 184, 186, 188, 190, and 192 are deposited and then patterned to complete the electrodes.

The present invention is not limited to the above-described embodiments but can be easily modified by those skilled in the art within the scope and spirit of the present invention described in the claims below.

As described above, the collector contact of the N + buried layer 104b of the bipolar transistor can be reduced by using the contact pad structure without using a deep N + doped layer structure or a polysilicon plug structure, and the collector resistance can be reduced and the process can be simplified There is an effect that can be.

Claims (6)

A semiconductor layer of a predetermined conduction type formed on a semiconductor substrate of a first conductivity type; A well region of a second conductivity type formed at a predetermined position on a surface of the semiconductor layer and having an impurity concentration lowered vertically downward from the surface; A buried region of a second conductivity type formed adjacent to the well region and the semiconductor substrate and having an impurity concentration higher than that of the adjacent portion of the well region; An opening formed in the semiconductor layer to expose a predetermined portion of the buried region; A conductive pad formed in the opening to be in contact with the exposed region of the embedded region and extending to a predetermined portion of the opening peripheral portion including the opening, the conductive pad having a uniform thickness; And a metal electrode which is in contact with an extension of the conductive pad. The semiconductor device according to claim 1, wherein the buried region is a high-concentration collector of a bipolar transistor. The semiconductor device according to claim 1, wherein the conductive pad is any one of impurity doped polycrystalline silicon, impurity doped amorphous silicon, or a stacked structure of the impurity doped polycrystalline silicon and the impurity doped buried region. The semiconductor device according to claim 1, wherein the conductive pad has a stacked structure of impurity-doped polycrystalline silicon and a metal silicide. A method of manufacturing a BiCMOS semiconductor device having a CMOS transistor and a bipolar transistor on the same wafer, the method comprising: forming a first buried layer of a first conductivity type and a second buried layer of a second conductivity type on a surface of a semiconductor substrate of a first conductivity type; ; Growing an epitaxial layer on a surface of the semiconductor substrate on which the first and second buried layers are formed; Forming a first well of the first conduction type and a second well of the second conduction type in the epitaxial layer; The first conductive material is deposited on the surface of the first well of the first conductivity type and in the vicinity of the surface of the second well of the second conductivity type to pattern the deposited first conductive material to form a first embedding layer An NMOS transistor or a load resistance SRAM memory element NMOS transistor is formed in the vicinity of the surface of the first well of the first conductivity type and a surface of the second well of the second conductivity type in the vicinity of the surface of the second well of the second conductivity type A step of forming a protective film in a region where the gate of the PMOS transistor and the base of the NPN bipolar transistor are to be formed; Forming a photoresist film for preventing etching and preventing ion implantation so as to expose an entire region where the bipolar transistor is to be formed, removing the protection film and forming an opening for a second buried layer contact together, And removing the photoresist layer by ion implantation; After the opening is formed, polycrystalline silicon is deposited on the entire surface and the deposited polycrystalline silicon is patterned to form the load resistance of the load resistive SRAM memory element, the power supply wiring of the load resistive SRAM memory element, and the resistance, Etching the silicon together to deeper the opening; After forming the openings, a second conductive material is deposited on the front surface and the deposited second conductive material is patterned to form the ground power supply wiring of the load resistive SRAM storage element, the interconnections, and the challenge for the second embedded layer contact And simultaneously forming the pads. 6. The method of claim 5, wherein the first and second conductive materials are polycides of impurity doped polysilicon and metal silicide.