KR20040009749A - Method of Manufacturing Semiconductor Device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to simplify a fabricating process by forming a MIM capacitor and a multi-layer metal line, simultaneously. CONSTITUTION: The first metal layer is deposited on a semiconductor substrate(21). A bottom metal line(22) and a capacitor bottom electrode(23) are formed by patterning the first metal layer. An interlayer dielectric(25) is deposited on the bottom metal line(22) and the capacitor bottom electrode(23). The first and the second contact holes are formed by etching the interlayer dielectric(25). A dielectric layer(29) is deposited on the interlayer dielectric. A photoresist layer pattern is formed on the interlayer dielectric. The dielectric layer(29) is etched by using the photoresist layer pattern. The photoresist layer pattern is removed. The second metal layer is deposited thereon. A top metal line(33b) and a capacitor top electrode(33a) are formed by patterning the second metal layer.

Description

Method of manufacturing semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can improve productivity through a simplified process.

An analog capacitor generally uses a metal-insulator-metal film (MIM) structure instead of a polysilicon film-insulation film-polysilicon film structure. This is because capacitors used in analog circuits in the RF band are required to have high quality factor values because there is almost no depletion and low resistance metal electrodes are essential to realize this. .

On the other hand, in manufacturing a semiconductor device having such a MIM capacitor, conventionally, the metal wiring is formed after the formation of the MIM capacitor, the manufacturing method is as follows.

1A to 1E are cross-sectional views illustrating processes for manufacturing a semiconductor device according to the related art.

First, as shown in FIG. 1A, a lower metal wiring 2 is formed on a semiconductor substrate 1 having a predetermined base layer according to a known process, and then the lower metal wiring 2 is covered. A first interlayer insulating film 3 is formed on the semiconductor substrate 1. Then, the first metal film 4, the dielectric film 5, and the second metal film 6 are sequentially formed on the first interlayer insulating film 3.

Subsequently, as shown in FIG. 1B, the second metal film 6 and the dielectric film 5 are patterned through a known photolithography process, thereby forming the upper electrode 6a of the MIM capacitor.

Subsequently, as shown in 1c, the first metal film 4 is etched to form the lower electrode 4a of the MIM capacitor, and as a result, the lower electrode 4a, the dielectric film 5 and the upper electrode. A MIM capacitor 10 composed of a stack of 6a is formed.

Next, as shown in FIG. 1D, a second interlayer insulating film 11 is deposited on the resultant, and the local portions of the second interlayer insulating film 11 and the first interlayer insulating film 3 are etched to form a lower metal. Contact holes 12 are formed to expose the wiring 2, the lower electrode 4a, and the upper electrode 6a, respectively.

Next, as shown in FIG. 1E, a metal film is deposited on the second interlayer insulating film 11 so that the contact holes 12 are filled, and then the metal film is patterned to form the lower metal wiring 2. The upper metal wiring 13a in contact with each other is formed to form a multi-layered metal wiring structure, and the lower electrode wiring 14a and the upper electrode wiring 14b in contact with the lower electrode 4a and the upper electrode 6a, respectively. ).

However, as described above, the conventional method of manufacturing a semiconductor device forms a multi-layered metal wiring after the formation of the MIM capacitor, so that the entire process is complicated, and therefore, undesirable in terms of productivity.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve productivity through process simplification.

1A to 1E are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to the prior art.

2A to 2D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to the present invention.

Explanation of symbols on main parts of drawing

21 semiconductor substrate 22 lower metal wiring

23 capacitor lower electrode 25 interlayer insulating film

27: first photosensitive film pattern 29: dielectric film

31: second photosensitive film pattern 33: second metal film

33a: capacitor upper electrode 33b: upper metal wiring

37: MIM capacitor

In order to achieve the above object, the present invention, the step of depositing a first metal film on a semiconductor substrate having a predetermined base layer; Patterning the first metal layer to form a lower metal interconnection and a capacitor lower electrode; Depositing an interlayer insulating film on the lower metal interconnection and the lower electrode; Etching the interlayer insulating layer to form first and second contact holes exposing the lower metal interconnection and the lower electrode, respectively; depositing a dielectric layer on the interlayer insulating layer including surfaces of the first and second contact holes ; Forming a photoresist pattern covering the upper region of the capacitor lower electrode on the insulating layer; Etching the exposed portion of the dielectric layer using the photoresist pattern as an etch barrier: removing the photoresist pattern; Depositing a second metal film on the substrate resultant; and patterning the second metal film to form an upper metal wiring contacting the lower metal wiring through the first contact hole, and at the same time, a capacitor upper electrode on the insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor device comprising forming a.

According to the present invention, since the MIM capacitor and the multilayer metal wiring are formed at the same time, the process can be simplified, thereby improving productivity.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views illustrating processes of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a first metal film is deposited on a semiconductor substrate 21 having a predetermined underlayer, and then the first metal film is patterned to form the lower metal wiring 22 and the capacitor lower electrode 23. Form. Next, an interlayer insulating film 25 is deposited on the lower metal wiring 22 and the capacitor lower electrode 23, and an upper region of the lower metal wiring and the capacitor lower electrode is exposed on the interlayer insulating film 25. 1 Photosensitive film pattern 27 is formed.

Referring to FIG. 2B, the interlayer insulating layer 25 is etched using the first photoresist layer pattern, and as a result, a first contact hole exposing the lower metal wiring 22 and the capacitor lower electrode 23, respectively. 26a and the second contact hole 26b are formed. Next, after removing the first photoresist layer pattern, a dielectric layer 29 is deposited on the interlayer insulating layer 25 including the surfaces of the first contact hole 26a and the second contact hole 26b. A second photoresist pattern 31 covering the upper region of the capacitor lower electrode 23 is formed on the dielectric layer 29.

Referring to FIG. 2C, the exposed portion of the dielectric layer 29 is etched using the second photoresist layer pattern as an etch barrier. Then, the dielectric layer 29 is left only on the capacitor lower electrode 23. Subsequently, in the state where the second photoresist layer pattern is removed, a second metal layer 33 is deposited on the substrate resultant, and an upper metal wiring forming region and a capacitor forming region are defined on the second metal layer 33. The third photosensitive film pattern 35 is formed.

Referring to FIG. 2D, the second metal film 33 is etched using the third photoresist pattern as an etch barrier, and as a result, the lower metal wire 22 through the first contact hole 26a. The upper metal wiring 33b in contact with the film is formed to form a multilayer metal wiring structure, and at the same time, the capacitor upper electrode 33a is formed on the dielectric film 29, whereby the lower electrode 23 and the dielectric film 29 are formed. ) And an MIM capacitor 39 formed of a laminated film structure of the upper electrode 33a. Then, the third photoresist pattern is removed, and as a result, the formation of the MIM capacitor and the multilayer metal wiring according to the present invention are completed.

Meanwhile, as another embodiment of the present invention, the MIM capacitor and the multi-layered metal wiring may be formed using a damascene process.

That is, after etching the dielectric layer 29 in FIG. 2B, the second metal is formed to have a thickness to completely fill the first and second contact holes 26a and 26b on the substrate resultant with the second photoresist layer pattern 31 removed. After the film 33 is deposited, the second metal film 33 is chemically mechanical polished (CMP) until the interlayer insulating film 25 is exposed to form the upper electrode 33a of the MIM capacitor. After forming the plug in the multi-layer metal wiring, the upper metal wiring is formed on the interlayer insulating film 25 to form a multi-layer metal wiring structure.

As described above, since the present invention simultaneously forms the MIM capacitor and the multi-layered metal wiring, the overall process can be simplified as compared with the conventional techniques for implementing the MIM capacitor and the multi-layered metal wiring, respectively, thereby simplifying the process. This can improve productivity.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (1)

Depositing a first metal film on a semiconductor substrate having a predetermined underlayer; Patterning the first metal layer to form a lower metal interconnection and a capacitor lower electrode; Depositing an interlayer insulating film on the lower metal interconnection and the lower electrode; Etching the interlayer insulating layer to form first and second contact holes exposing the lower metal wiring and the lower electrode, respectively: Depositing a dielectric film on the interlayer insulating film including surfaces of the first and second contact holes; Forming a photoresist pattern covering the upper region of the capacitor lower electrode on the insulating layer; Etching the exposed dielectric layer portion using the photoresist pattern as an etch barrier: Removing the photoresist pattern; Depositing a second metal film on the substrate product; and Patterning the second metal layer to form an upper metal interconnection contacting the lower metal interconnection through the first contact hole, and simultaneously forming a capacitor upper electrode on the dielectric layer. Manufacturing method.