KR20030042232A - Method of forming mim capacitor having cylinder structure - Google Patents

Abstract

PURPOSE: A method for fabricating a metal insulator metal(MIM) capacitor is provided to increase capacitance, reduce the size of an electrode and eliminate a step caused by an upper electrode by making the MIM capacitor composed of a cylinder structure. CONSTITUTION: A semiconductor substrate(21) on which an underlying layer(22) is formed is prepared. The first metal layer for a lower electrode(23a) is formed on the underlying layer. A groove of a predetermined depth is formed in a predetermined position of the first metal layer. A dielectric layer(26) is deposited on the first metal layer including the groove. The second metal layer for the upper electrode(27a) is formed on the dielectric layer to completely fill the groove. The second metal layer and the dielectric layer are polished until the first metal layer is exposed so that the upper electrode is formed in the groove by interposing the dielectric layer. The first metal layer is patterned to form the lower electrode.

Description

METHOD OF FORMING MIM CAPACITOR HAVING CYLINDER STRUCTURE}

The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a MIM capacitor of a cylinder structure.

The analog capacitor is typically formed of a metal-insulator-metal (MIM) structure instead of a poly-insulator-poly (PIP) structure. This is because a capacitor used in an analog circuit in an RF band requires a high Q (Quality Factor) value, because it requires little depletion and low resistance metal electrode as an electrode material.

1A to 1E are cross-sectional views illustrating processes for forming a conventional MIM capacitor, which will be described below.

Referring to FIG. 1A, in a state in which a predetermined base layer 10 is formed on a semiconductor substrate 1, a first metal film 11 and a dielectric film 12 for lower electrodes on the base layer 10 are formed. And the second metal film 13 for the upper electrode is formed in this order. Then, the first photoresist layer pattern 14 defining the capacitor upper electrode formation region is formed on the second metal layer 13 through a known photolithography process.

Here, the base layer 10 may be understood to include an interlayer insulating film having a surface planarized with a transistor. In addition, the first and second metal films 11 and 13 for the lower and upper electrodes may be understood to be formed of a laminated film of Ti / TiN / Al / Ti / TiN, wherein the Al film has a low resistance. Therefore, the Ti film and the TiN film under the Al film function as an adhesive layer and a diffusion barrier layer, and the Ti and TiN films on the Al film function as an adhesive layer and an antireflection layer, respectively. In addition, the dielectric film 12 includes an oxide film having a high dielectric constant, for example, a silicon oxynitride (SiOxNy) film, a silicon nitride (Si3N4) film, or an oxide film formed by PECVD. In addition, although not shown, a contact plug exists in the base layer 10, and the contact plug may be understood to be in contact with the first metal film for the lower electrode.

Referring to FIG. 1B, the second metal film 13 and the dielectric film 12 are etched using the first photoresist film pattern 14 as an etching mask to obtain a capacitor upper electrode 13a. In this case, the etching is performed by dry etching using an activated plasma composed of a mixed gas of Cl2, BCl3 and N2 gas. In addition, the process for forming the capacitor upper electrode 13a may be performed in the order of etching the second metal film 13, removing the first photoresist film pattern 14, or etching the dielectric film 12. The etching of the second metal film 13, the etching of the dielectric film 12, and the removal of the first photoresist film pattern 14 are performed in this order. In addition, the etching of the dielectric film 12 is performed by a plasma activated using a gas containing "C" and "F" as a main component, for example, a CxFy gas such as CF4, C2F6, C4F8, C5F8, and the like.

Subsequently, after the photoresist is coated on the resultant, the photoresist is exposed and developed to form a second photoresist pattern 15 for forming a capacitor lower electrode.

Referring to FIG. 1C, the exposed first metal film portion, which is not covered by the second photoresist film pattern, is etched with an activated plasma made of a mixed gas of Cl 2, BCl 3, and N 2, and then the second photoresist pattern used as an etching mask is etched. To form the capacitor lower electrode 11a, and as a result, the MIM capacitor 20 having the laminated structure of the lower electrode 11a, the dielectric film 12, and the upper electrode 13a is completed. . In Fig. 1C, reference numeral 11b, which has not been described, indicates circuit wiring.

Referring to FIG. 1D, an interlayer insulating film 16 is formed on the resultant, and the surface thereof is planarized through a chemical mechanical polishing (CMP) process. Here, even if the CMP process is applied after the deposition, the interlayer insulating layer 16 may not be completely planarized due to the surface topology of the lower layer when a single layer of an oxide material is applied.

Thus, as shown, the interlayer insulating film 16 is a single film of an insulating film, such as a BPSG film, or a double film of a planarizing film 16a, such as SOG and FOX, and a PE-TEOS 16b, for complete planarization, or Or more laminated films.

Referring to FIG. 1E, predetermined portions of the interlayer insulating layer 16 are selectively etched to form contact holes for exposing the capacitor lower and upper electrodes 11a and 13a and the circuit wiring 11b, respectively. A conductive film such as a tungsten film is embedded in the holes to form contact plugs 17 contacting the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a, respectively. Then, by depositing and patterning a metal film on the interlayer insulating layer 16, the contact line 17 is electrically contacted with the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a. Metal electrodes 18 are formed. Here, the metal electrodes 18 are formed in a stacked structure of Ti / TiN / Al / Ti / TiN similarly to the capacitor lower and upper electrodes 11a and 13a.

However, the above-described conventional method for forming MIM capacitors has the following problems.

First, as described above, the dielectric film is etched after the second metal film for the upper electrode is etched. In this process, a horizontal etch occurs, and as shown in FIG. 2, the dielectric film 12 is etched. The side portion of) may be excessively etched, and as a result, a short between the upper electrode and the lower electrode may occur.

Second, since the lower electrode is formed through patterning of the photoresist layer and etching of the first metal layer again after patterning of the upper electrode, its formation is not easy, and in particular, it is difficult to form a fine pattern.

Third, the capacitor capacity is proportional to the area of the dielectric film, that is, the electrode surface area. In the conventional case, since the capacitor is formed by simply stacking the structure, it is difficult to increase the capacity. As a result, conventional capacitor structures are undesirable in terms of high integration.

Fourth, since the interlayer insulating film must be formed in a two-layer structure for planarization, it is cumbersome, especially when SOG or FOX is applied for complete planarization, in relation to the deposition of SOG or FOX in different thicknesses for each region. In the CMP process of the surface, the recess problem is intensified.

Fifth, when the plug is formed, the interlayer dielectric layer is etched by using a plasma activated with CxFy gas, and in particular, the etching of the interlayer dielectric layer is performed by over etching to prevent under etching. When the lower electrode is aligned with an etching target, as shown in FIG. 3, the upper electrode 13a is damaged as well as in severe cases. There is a risk that the upper electrode 13a is pierced. On the contrary, when the upper electrode is aligned with an etching target, an open defect may occur due to underetching on the lower electrode side. In addition, the material such as SOG or FOX is difficult to control the amount of etching as well as difficult to control the contact size because the etching rate is relatively faster than the silicon oxide film (SiO2).

Accordingly, the present invention has been made to solve the above problems, and to solve the problem in the process while solving a problem caused by the step between the lower electrode and the upper electrode of the cylinder structure MIM (MIM) capacitor forming method The purpose is to provide.

In addition, the present invention has a further object to provide a method for forming a MIM capacitor of the cylinder structure to adopt a cylinder structure to obtain a high capacity, through which the high-capacity device can be advantageously applied. .

1A to 1E are cross-sectional views illustrating processes for forming a conventional MIM capacitor.

2 and 3 are views for explaining the problems of the prior art.

Figures 4a to 4e is a cross-sectional view for each process for explaining a method of forming the MIM capacitor of the cylinder structure according to an embodiment of the present invention.

5A and 5B are diagrams for explaining a photoresist pattern obtained as a result of diffraction and interference of light.

Explanation of symbols on the main parts of the drawings

21 semiconductor substrate 22 base layer

23: first metal film 23a: capacitor lower electrode

23b: circuit wiring 24: first photosensitive film pattern

25 groove 26 dielectric film

27: second metal film 27a: capacitor upper electrode

28: second photosensitive film pattern 30: MIM capacitor

31 interlayer insulating film 32 contact plug

33: metal electrode 50: exposure mask

52: photosensitive film pattern

MEM capacitor forming method of the cylinder structure of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate having a base layer formed on the upper surface; Forming a first metal film for a lower electrode on the underlayer; Forming a groove having a predetermined depth in place of the first metal film; Depositing a dielectric film on the first metal film including the groove; Forming a second metal film for an upper electrode on the dielectric film to completely fill the groove; Polishing the second metal film and the dielectric film until the first metal film is exposed to form an upper electrode in which the dielectric film is interposed in the groove; And patterning the first metal layer to form a lower electrode.

The method may further include forming an interlayer insulating film on the resultant after forming the capacitor lower electrode; Forming contact plugs in the interlayer insulating layer, the contact plugs being in contact with the lower electrode and the upper electrode, respectively; And forming metal electrodes on the interlayer insulating layer, the metal electrodes contacting the contact plugs, respectively.

Here, in the method of the present invention, the first metal film is formed into a stacked structure of Ti / TiN / Al, and the second metal film is formed into a stacked film of Ti / TiN / W using a CVD method, or After deposition of the copper seed (Cu seed) to form a copper film using an electrolysis method.

According to the present invention, since the MIM capacitor is formed in a cylindrical structure, the problem caused by the step difference between the lower electrode and the upper electrode can be solved, and in particular, a high capacity can be obtained, which is very advantageously applied to the manufacture of a highly integrated device. can do.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4E are cross-sectional views of processes for describing a method of forming an MIM capacitor having a cylinder structure according to an embodiment of the present invention.

Referring to FIG. 4A, a predetermined base layer 22 including a transistor and a contact plug is formed on a semiconductor substrate 21, and a laminated film of Ti / TiN / Al / Ti / TiN is formed on the base layer 22. The first metal film 23 for the capacitor lower electrode is formed. Thereafter, a first photoresist layer pattern 24 is formed on the first metal layer 23 through a known photolithography process to expose a portion of the first metal layer 23. A circular groove is formed on the surface of the first metal film 23 by etching the predetermined thickness of the exposed first metal film portion with an activated plasma composed of a mixed gas of Cl 2, BCl 3 and N 2 using 24 as an etching mask. To form 25.

Here, the first photoresist layer pattern 24 is formed by sequentially applying a photoresist layer, exposing the photoresist layer using an exposure mask, and developing the exposed photoresist layer in sequence, and the exposure process is illustrated in FIG. 5A. As described above, the exposure mask 50 has a rectangular opening area.

In this case, the exposure is performed using an exposure mask 50 having a rectangular opening area, but as shown in FIG. 5B, the first photosensitive film obtained through the exposure using the exposure mask 50 and a subsequent development process. The pattern 52 has a circular hole therein. This is due to the diffraction and interference of the light. In more detail, the exposure energy passing through the center portion A of the opening region is subjected to much interference, but the exposure energy passing through the corner portion B of the opening region is determined by Since it is not subjected to much interference, the photoresist portion corresponding to the center portion A is subjected to sufficient exposure energy to the surface portion of the lower layer and is sufficiently removed in the subsequent development process, while the photoresist portion corresponding to the corner portion B is sufficient. This is due to the fact that the exposure energy could not be transferred and therefore not developed at right angles in the subsequent development process. As a result, when the photoresist film is exposed using the exposure mask 50 having the rectangular opening region, the pattern implemented on the first photoresist pattern 24 becomes circular, thus etching the first photoresist pattern 24. By etching the first metal film 23 using the mask, the grooves 25 formed in the first metal film 23 become circular.

Referring to FIG. 4B, a chemical vapor deposition (CVD) method or an electrolysis method may be performed on the surface of the groove 25 and the surface of the first metal film 23 in a state where the first photoresist layer pattern used as an etching mask is removed. A linear dielectric film 26 is deposited using this method, and a second metal film 27 for upper electrode is deposited on the dielectric film 26 so that the groove 25 is completely embedded. Here, the second metal film 27 is formed in a stacked structure of Ti / TiN / W using a CVD method, or a copper film using an electrolysis method. In this case, when using the electrolysis method, a copper film is deposited by using an electrolysis reaction in a state of depositing a copper seed.

Referring to FIG. 4C, the second metal film and the dielectric film are polished through the CMP process until the first metal film 23 is exposed, and the capacitor is disposed in the groove 25 with the dielectric film 26 interposed therebetween. The upper electrode 27a is formed. Then, the second photoresist layer pattern 28 is formed on the capacitor upper electrode 27a and the first metal layer 23 through a known photolithography process.

Referring to FIG. 4D, the first metal film is etched using the second photoresist film pattern as an etching mask so that the capacitor lower electrode 23a is formed, and as a result, the MIM capacitor 30 having the cylinder structure is formed. To complete. Reference numeral 23b denotes a circuit wiring.

Referring to FIG. 4E, an interlayer insulating layer 31 is deposited on the resultant to cover the MIM capacitor of the cylinder structure, and the surface thereof is planarized through a CMP process. Then, predetermined portions of the interlayer insulating film 31 are selectively plasma-etched to form contact holes exposing the capacitor upper electrode 27a, the lower electrode 23a, and the circuit wiring 23b, respectively, and then tungsten or copper. The contact plugs 32 are formed in each contact hole by sequentially performing the deposition and the CMP process, and then the metal electrodes 32 electrically contacting the contact plugs 32 on the interlayer insulating layer 31 are formed. Form. In this case, the metal electrodes 32 are formed in a stacked structure of Ti / TiN / Al.

The MIM capacitor according to the present invention formed through the process as described above has the following advantages.

First, since the MIM capacitor forming method of the present invention performs the etching of the dielectric film by the CMP process, the phenomenon that the side of the dielectric film is excessively etched does not occur as compared with the conventional method, and therefore, the short problem between the upper electrode and the lower electrode is fundamental. Is solved.

Second, the MIM capacitor forming method of the present invention forms an upper electrode through deposition of a dielectric film and a second metal film and polishing the films, and then forms a lower electrode through a photolithography process, thereby performing two photolithography processes. Compared with the conventional method of forming the upper electrode and the lower electrode, the process proceeds more easily, and in particular, the formation of the lower electrode is easier than that of the conventional one, and the micronization is easy.

Thirdly, the MIM capacitor of the present invention has a cylindrical structure, which has an increased capacitor capacity than that of the conventional one, and in particular, a high capacitor capacity can be obtained even if the size thereof is reduced.

In detail, the capacitor capacity is proportional to the area of the dielectric film as shown in Equation 1 below, and inversely proportional to the thickness of the dielectric film.

(C: capacitor capacity, ε: dielectric constant, A: area of dielectric film, t: thickness of dielectric film)

However, the MIM capacitor of the present invention has a cylinder structure, and the area of the dielectric film in this structure is the sum of the areas of the portions disposed on the bottom surface and the wall surface of the groove as shown in Equation 2 below.

(A: dielectric film area, h: height of groove)

Thus, the MIM capacitor of the present invention has an increased capacity than that of the conventional one, so that the desired capacity can be maintained even if the size is reduced.

Fourth, since the MIM capacitor of the present invention does not have a step between the lower electrode and the upper electrode, application of SOG or FOX is not necessary for complete surface planarization in forming the interlayer insulating film, and thus, troublesome processing can be solved.

Fifth, since the MIM capacitor of the present invention has no step between the lower electrode and the upper electrode, it is easy to adjust the depth during the etching of the interlayer insulating film for forming the contact plug, and in particular, to prevent the problem of damaging the upper electrode due to the excessive etching. Can be.

As described above, according to the present invention, the MIM capacitor is formed in a cylinder structure, and thus, the capacity can be increased, and the size of the electrode can be reduced, and thus the present invention can be very advantageously applied to the manufacture of highly integrated devices. In addition, according to the present invention, by forming the MIM capacitor in a cylindrical structure, the step caused by the upper electrode can be eliminated, and thus, the advantages in the process can be obtained.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

Providing a semiconductor substrate having an underlayer formed on an upper surface thereof; Forming a first metal film for a lower electrode on the underlayer; Forming a groove having a predetermined depth in place of the first metal film; Depositing a dielectric film on the first metal film including the groove; Forming a second metal film for an upper electrode on the dielectric film to completely fill the groove; Polishing the second metal film and the dielectric film until the first metal film is exposed to form an upper electrode in which the dielectric film is interposed in the groove; And And forming a lower electrode by patterning the first metal layer. The method of claim 1, wherein the first metal film has a stacked structure of Ti / TiN / Al. The method of claim 1, wherein the second metal film is a laminated film of Ti / TiN / W or a copper film. 4. The method of claim 3, wherein the laminated film of Ti / TiN / W is formed by a CVD method. The method of claim 4, wherein the copper film is formed by electrolysis after deposition of a copper seed (Cu seed). The method of claim 1, wherein after forming the capacitor lower electrode, Forming an interlayer insulating film on the resultant product; Forming contact plugs in the interlayer insulating layer, the contact plugs being in contact with the lower electrode and the upper electrode, respectively; And And forming metal electrodes in contact with the contact plugs on the interlayer insulating layer.