KR20040008485A - Forming method for test patterns of a semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a test pattern of a semiconductor device is provided to enhance the reliability of a test process by forming the test pattern for measuring only SAC(Self Aligned Contact) failure. CONSTITUTION: An N-well(33) is formed on a test pattern region of a semiconductor substrate. A gate insulating layer is formed on the semiconductor substrate. A conductive layer for a gate electrode is formed on the gate insulating layer. A gate electrode and a gate insulating layer pattern(35) are formed by etching the conductive layer for the gate electrode and the gate insulating layer. A p+ source/drain region(43) is formed by implanting p+ ions into the semiconductor substrate of both sides of the gate electrode. An insulating layer spacer(41) is formed on the gate electrode and a sidewall of the gate insulating layer pattern(35). An interlayer dielectric(45) is formed on the entire surface of the semiconductor substrate. The interlayer dielectric(45) is etched by performing a photo-etch process. A landing plug(47) is formed by forming a conductive layer thereon and etching the conductive layer.

Description

Forming method for test patterns of a semiconductor device

The present invention relates to a method of forming a test pattern of a semiconductor device, and more particularly, to a method of forming a test pattern of a semiconductor device capable of more reliably testing the characteristics of a device by forming a test pattern capable of measuring only a SAC fail. .

In DRAM, test patterns can be used to measure the electrical properties of the device, which can be a great help in device simulation.

As semiconductor devices are becoming highly integrated, most contact holes are formed using the SAC method.

In particular, in the recent technology trend, when the contact hole is formed by the SAC method, a material used as an etch barrier is used as a hard mask for the conductive wiring, and the thickness of the remaining hard mask is a large variable in the generation of SAC fail. Acts as.

In this case, the thickness of the hard mask used as an etch barrier cannot be used above a certain level due to the high integration of the device.

In order to improve the SAC fail, the thickness of the hard mask existing on the upper portion of the conductive line is continuously increased when the conductive line is formed.

However, when increasing the thickness of the hard mask, there is a problem that the formation process of the conductive wiring itself becomes difficult.

Hereinafter, a test pattern forming method of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A is a schematic diagram showing a leakage current measuring mechanism using a test pattern of a semiconductor device according to a first embodiment of the prior art, in which a test pattern for measuring SAC fail is formed in a test pattern formation region of a semiconductor substrate. Illustrated.

First, the pwell 13 is formed by ion implanting an impurity in a test pattern region of a semiconductor substrate (not shown).

Next, a device isolation insulating film 11 defining an active region is formed on the semiconductor substrate.

Next, a gate insulating film and a conductive layer for a gate electrode are formed on the semiconductor substrate. In this case, the gate electrode conductive layer is formed of a polycrystalline silicon layer into which n + impurities are ion-implanted, a stacked structure of a WN film and a W film.

Next, the stack structure is etched by a photolithography process using a gate electrode mask to form a gate insulating film pattern 15, a polysilicon layer pattern 17, a WN film pattern 18, and a W film pattern 19. To form.

Next, a low concentration of n-type impurities are implanted into the semiconductor substrates on both sides of the gate electrode to form an n− source / drain region 23.

Next, an insulating film spacer 21 is formed on sidewalls of the gate electrode and the gate insulating film pattern 15. At this time, the insulating film spacer 21 is formed of a nitride film.

Next, an interlayer insulating film 25 is formed over the entire surface. The interlayer insulating film 25 is formed of a BPSG film.

Next, the interlayer insulating layer 25 is etched by a photolithography process using a contact mask exposing portions intended as bit line contacts and storage electrode contacts. At this time, the etching process is performed by the SAC method.

Then, a conductive layer (not shown) is formed over the entire surface, and then planarized to form a landing plug 27. In this case, a polysilicon layer in which n + impurities are ion-implanted is used.

Thereafter, a test process is performed to confirm the fail by the SAC method.

To this end, a Vcc terminal is connected to the landing plug 27, and a Vss terminal is connected to the gate electrode 17 to measure whether there is a leakage current between the landing plug 27 and the gate electrode 17. In this case, when the landing plug 27 and the gate electrode 17 are shorted, the landing plug 27 and the gate electrode 17 flow in the direction of the landing plug 27 and the gate electrode 17. (See Figure 1A)

FIG. 2A is a schematic diagram showing a leakage current measuring mechanism using a test pattern of a semiconductor device according to a second exemplary embodiment of the prior art, and illustrates a case in which an enwell 29 is used instead of the pewell 13 of FIG. 1A. At this time, in order to test the leakage current between the landing plug 27 and the gate electrode, a Vcc terminal is connected to the gate electrode, and a Vss terminal is connected to the enwell 29.

In the above structure, when the landing plug 27 and the gate electrode 17 are shorted, the leakage current is n-well 29 -n- source / drain region 23-landing plug 27-polysilicon layer pattern 17 , That is, it moves in the direction (④).

However, as described above, in the method of forming a test pattern of the semiconductor device according to the related art, the leakage current measured when the failure of the gate insulating layer in addition to the SAC failure is measured when the leakage current is measured between the landing plug 27 and the gate electrode. It becomes bigger. In this case, the landing plug 27-the polysilicon layer pattern 17 and the n-source / drain region 23-the polysilicon layer pattern 17 in Fig. 1b, i.e., directions (2) and (3), and Fig. 2b. Leakage current paths are formed in the enwells 29, n-source / drain regions 23, landing plugs 27, polysilicon layer patterns 17, enwells 29, i.e. There is a problem in that the leakage current due to the SAC fail cannot be measured purely.

In order to solve the above problems of the prior art, a gate is formed by using an polycrystalline silicon layer in which an n well is formed on a semiconductor substrate, and p + impurities are implanted to form a p + source / drain region, followed by ion implantation of n + impurities. Forming an electrode and a landing plug prevents the formation of a leakage current path between the gate electrode and the p + source / drain region when measuring the leakage current between the gate electrode and the landing plug, thereby obtaining reliable measurement values. The purpose is to provide.

1A is a schematic diagram showing a leakage current measuring mechanism using a test pattern of a semiconductor device according to a first embodiment of the prior art;

FIG. 1B is a schematic diagram illustrating a problem in measuring SAC fail using a test pattern of the semiconductor device of FIG. 1A; FIG.

2A is a schematic diagram showing a leakage current measuring mechanism using a test pattern of a semiconductor device according to a second embodiment of the prior art;

FIG. 2B is a schematic diagram illustrating a problem in measuring SAC fail using a test pattern of the semiconductor device of FIG. 2A; FIG.

3A to 3C are cross-sectional views illustrating a method for forming a test pattern of a semiconductor device according to the present invention.

4 is a schematic diagram showing a leakage current measuring mechanism using a test pattern of a semiconductor device according to the present invention.

<Description of Symbols for Major Parts of Drawings>

11, 31: device isolation insulating film 13: Pwell

15, 35: gate insulating film pattern 17, 37: polysilicon layer pattern

18, 38: WN layer pattern 19, 39: W layer pattern

21, 41: insulating film spacer 23: n- source / drain region

25, 45: interlayer insulating film 27, 47: landing plug

33 33: Enwell 43: p + source / drain region

In order to achieve the above object, the test pattern of the semiconductor device according to the present invention,

Forming an enwell in the test pattern region of the semiconductor substrate;

Forming a gate insulating film on the semiconductor substrate;

Forming a conductive layer for a gate electrode on the gate insulating film;

Forming a gate electrode and a gate insulating layer pattern by etching the gate electrode conductive layer and the gate insulating layer by a photolithography process using a mask for a gate electrode;

Forming p + source / drain regions by implanting p + impurities into the semiconductor substrates on both sides of the gate electrode;

Forming an insulating film spacer on sidewalls of the gate electrode and the gate insulating film pattern;

Forming an interlayer insulating film over the entire surface;

A process of self-aligning the interlayer insulating film by a photolithography process using a contact mask exposing portions intended as bit line contacts and storage electrode contacts;

Forming a landing plug by forming a conductive layer in which n + impurities are injected over the entire surface and then planarizing etching;

The p + impurity is boron,

A reverse bias is formed between the gate electrode and the p + source / drain region.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3C are cross-sectional views illustrating a method of forming a test pattern of a semiconductor device according to the present invention, and FIG. 4 is a schematic diagram illustrating a leakage current measuring mechanism using a test pattern of a semiconductor device according to the present invention. do.

First, the N well 33 is formed by ion implanting N-type impurities into a test pattern region of a semiconductor substrate (not shown).

Next, a device isolation insulating film 31 defining an active region is formed on the semiconductor substrate. (See Figure 3A)

Next, a gate insulating film and a conductive layer for a gate electrode are formed on the semiconductor substrate. In this case, the gate electrode conductive layer is formed of a polycrystalline silicon layer into which n + impurities are ion-implanted, a stacked structure of a WN film and a W film.

Next, the stack structure is etched by a photolithography process using a gate electrode mask to form a gate insulating film pattern 35, a polysilicon layer pattern 37, a WN film pattern 38, and a W film pattern 39. To form.

Next, a high concentration of p + impurities are implanted into the semiconductor substrates on both sides of the gate electrode to form a p + source / drain region 43.

Next, an insulating film spacer 41 is formed on sidewalls of the gate electrode and the gate insulating film pattern 35. The insulating film spacer 41 is formed of a nitride film. (See Figure 3b)

Next, an interlayer insulating film 45 is formed over the entire surface. The interlayer insulating film 45 is formed of a BPSG film.

Next, the interlayer insulating layer 45 is etched by a photolithography process using a contact mask exposing portions intended as bit line contacts and storage electrode contacts. At this time, the etching process is performed by the SAC method.

Then, a conductive layer (not shown) is formed over the entire surface, and then planarized to form a landing plug 47. In this case, a polysilicon layer in which n + impurities are ion-implanted is used. (See Figure 3c)

Thereafter, a test process is performed to confirm the fail by the SAC method.

To this end, a Vcc terminal is connected to the landing plug 47, and a Vss terminal is connected to the gate electrode to measure a leakage current between the landing plug 47 and the gate electrode. At this time, when the landing plug 47 and the gate electrode are shorted, the leakage current flows in the landing plug 47-polycrystalline silicon layer pattern 37, i.e., direction (⑥), which is measured by a resistance curve.

In addition, when the gate insulating film pattern 35 is deteriorated and a leakage current flows in the polysilicon layer pattern 37 -p + source / drain region 43-landing plug 47, that is, in the direction (⑦), the n + impurities Since a reverse bias is formed between the injected polysilicon layer pattern 37 and the p + source / drain region 43, it is very small compared to the leakage current value flowing in the (6) direction (6> 7). (See Figure 4)

As described above, in the method of forming a test pattern of a semiconductor device according to the present invention, the gate electrode and the source / drain are deteriorated due to the deterioration of the gate insulating film when the test pattern is formed to measure the insulating properties between the landing plug and the gate electrode formed by the SAC method. By preventing leakage current paths from being formed between regions, only pure SAC fail can be measured to improve electrical characteristics and reliability of semiconductor devices.

Claims (3)

Forming an enwell in the test pattern region of the semiconductor substrate; Forming a gate insulating film on the semiconductor substrate; Forming a conductive layer for a gate electrode on the gate insulating film; Forming a gate electrode and a gate insulating layer pattern by etching the gate electrode conductive layer and the gate insulating layer by a photolithography process using a mask for a gate electrode; Forming p + source / drain regions by implanting p + impurities into the semiconductor substrates on both sides of the gate electrode; Forming an insulating film spacer on sidewalls of the gate electrode and the gate insulating film pattern; Forming an interlayer insulating film over the entire surface; A process of self-aligning the interlayer insulating film by a photolithography process using a contact mask exposing portions intended as bit line contacts and storage electrode contacts; A method of forming a test pattern of a semiconductor device, the method comprising: forming a landing plug by forming a conductive layer in which an n + impurity is implanted on an entire surface and then planarizing etching. The method of claim 1, And the p + impurity is boron. The method of claim 1, And a reverse bias is formed between the gate electrode and the p + source / drain region.