KR20000043191A - Manufacturing method of monitoring apparatus of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a monitoring apparatus of a semiconductor device is to measure a characteristics of pure leakage current of impurity region so as to improve productivity and yield of semiconductor device. CONSTITUTION: A manufacturing method of a monitoring apparatus comprises the steps of: forming a gate insulation layer(16) on a semiconductor substrate(12); forming a gate electrode(18) on the gate insulation layer; ion implanting an impurity into the substrate on opposite side of the gate electrodes to form an impurity region; forming a flattening layer on the entire layer; forming a photoresist layer pattern on the flattening layer; removing the flattening layer using the photoresist layer pattern as an etching mask to form a contact hole, and removing the photoresist layer pattern; forming a contact plug filling the contact hole; forming a conductive layer on the flattening layer; and etching the conductive layer to form a pad connected to the contact plug.

Description

Manufacturing method of inspection device of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a test device for a semiconductor device. In particular, an MOS field effect transistor is formed over an active region, and an impurity region for forming an impurity region for inspection and a contact for connecting to an external pad are separately formed. The present invention relates to an inspection apparatus for measuring junction leakage current characteristics excluding leakage current due to damage due to contact etching in an impurity region to be inspected.

As the semiconductor devices become more integrated, the gate electrodes of the MOS FETs also decrease in width, but when the width of the gate electrodes decreases by N times, the electrical resistance of the gate electrodes increases by N times, which reduces the operating speed of the semiconductor devices. Therefore, in order to reduce the resistance of the gate electrode, polyside, which is a laminated structure of the polysilicon layer and the silicide, is used as the low resistance gate by using the property of the polysilicon layer / oxide layer interface showing the most stable MOSFET characteristics.

In general, a pn junction formed of a p or n type semiconductor substrate with n or p type impurities is implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region. Therefore, in a semiconductor device having a reduced channel width, the junction depth should be shallow to prevent short channel effects due to side diffusion from the diffusion region, and to prevent junction breakage due to electric field concentration to the drain. For this purpose, there are methods such as forming a source / drain region into an LDD structure.

Hereinafter, a method for manufacturing an inspection apparatus for a semiconductor device according to the related art will be described with reference to the accompanying drawings.

1 is a cross-sectional view of an inspection apparatus of a semiconductor device according to the prior art.

First, an element isolation insulating film 13 is formed in a portion of the p-type semiconductor substrate 11 that is intended as an element isolation region.

Next, an impurity region 15 is formed by ion implanting n + impurities into the semiconductor substrate 11 using an n + implant mask (not shown).

Next, the planarization layer 17 is formed on the entire surface, and a contact hole is formed by an etching process using a contact mask that exposes a portion of the impurity region 15 to be a contact.

In addition, when the conductive layer (not shown) is formed on the planarization layer 17, and then the planarization layer 17 is exposed by an entire surface etching process or a chemical mechanical polishing process. Until then, the conductive layer is removed to form a contact plug 19 filling the contact hole.

Thereafter, a conductive wiring 21 connected to the contact plug 19 is formed on the planarization film 17. (See Fig. 1)

However, the method of manufacturing a semiconductor device inspection apparatus according to the related art as described above is a method of measuring a leakage current characteristic of a junction by directly forming a contact in an implant region of a portion to be inspected. Since damages and damages generated during contact formation are monitored, there is a problem that it is difficult to distinguish whether the change in the characteristics of the monitored junction and the unstable phenomenon are due to the change of the junction or the damages generated during contact formation.

The present invention provides a method for manufacturing a device for inspecting a semiconductor device which prevents deterioration of yield and reliability of a device by measuring pure leakage current characteristics of a junction region using a MOS transistor in order to solve the problems of the prior art. The purpose is.

1 is a cross-sectional view showing an inspection apparatus of a semiconductor device according to the prior art.

2A is a plan view showing an inspection apparatus of a semiconductor device according to the present invention.

FIG. 2B is a sectional view along line A-A 'of FIG. 2A;

<Description of Signs of Major Parts of Drawings>

11, 12: semiconductor substrate 13, 14: device isolation insulating film

15 junction region 16 gate insulating film

17 planarization film 18 gate electrode

19, 30, 32: contact plug 20: LDD area

21: conductive wiring 22: insulating film spacer

24a: first impurity region 24b: second impurity region

26: first flattening film 28: second flattening film

34: external pad 36: voltage input pad

In order to achieve the above object, a method for manufacturing an inspection device for a semiconductor device according to the present invention

forming a gate insulating film on the semiconductor substrate including n-well and p-well;

Forming a gate electrode on the gate insulating film;

Forming an impurity region by implanting impurities into both semiconductor substrates of the gate electrode;

Forming a planarization film over the entire surface;

Forming a photoresist pattern on the planarization layer exposing a portion of the impurity region on one side of the gate electrode to an external pad contact and a portion of the gate contact to apply a voltage to the gate electrode;

Removing the planarization layer by using the photoresist pattern as an etching mask to form a contact hole, and then removing the photoresist pattern;

Forming a contact plug to fill the contact hole;

Forming a conductive layer on the planarization film;

And etching the conductive layer using the conductive wiring mask as an etch mask to form a pad connected to the contact plug.

Hereinafter, with reference to the accompanying drawings will be described in detail according to the present invention.

FIG. 2A is a plan view showing an inspection apparatus of a semiconductor device according to the present invention, and FIG. 2B is a cross-sectional view taken along the line A-A 'of FIG.

First, n wells (not shown) are formed on an p-type or n-type semiconductor substrate 12 by an n-well mask (not shown), and p-wells (not shown) are used in an implant process using a p-well mask (not shown). Not shown).

Next, an element isolation insulating film 14 is formed on a portion of the semiconductor substrate 12 that is intended to be an element isolation region.

Next, a gate insulating layer 16 is formed on the semiconductor substrate 12, and a first conductive layer (not shown) is formed. In this case, the first conductive layer may use a polysilicon layer, a tungsten silicide layer, a polyside layer, or a metal layer.

Next, the gate electrode 18 is formed by etching the first conductive layer with an etch mask using a gate electrode mask that protects a portion of the first conductive layer that is intended as the gate electrode. The gate electrode 18 may be formed of a polysilicon layer, a polyside, or a metal layer.

An n-type low concentration impurity is ion-implanted into both semiconductor substrates 12 of the gate electrode 18 to form a lightly doped drain (LDD) region 20.

Next, an insulating film (not shown) is formed on the entire surface, and then the entire surface is etched to form an insulating film spacer 22 on the sidewall of the gate electrode 18.

Thereafter, high concentration impurities are implanted into both semiconductor substrates 12 of the insulating film spacer 22 to form the first impurity region 24a and the second impurity region 24b. At this time, a high concentration of p-type impurity is implanted into the n well formed in the peripheral circuit of the semiconductor substrate 12, and a high concentration of n-type impurity is implanted into the p well, and the concentration impurity is n-type or p-type impurity. Ion implantation. In addition, the first impurity region 24a on one side of the gate electrode 18 is a junction region for electrically connecting with the outside, and the second impurity region 24b on the other side of the gate electrode 18 is the It is a junction area for inspecting leakage current caused by damage by ion implantation process. Here, the second impurity region 24b may be a junction region formed by all kinds of ion implantation processes.

Next, an interlayer insulating film 26 is formed over the entire surface, and a planarization film 28 is formed over the interlayer insulating film 26.

Subsequently, a photoresist pattern (not shown) is formed on the planarization film 28 to expose portions of conductive wiring contacts on the first impurity region 24a and the gate electrode 18.

The planarization layer 28 and the interlayer insulating layer 26 are etched using the photoresist pattern as an etch mask to form a conductive wiring contact hole (not shown), and the photoresist pattern is removed.

Next, a second conductive layer (not shown) is formed on the planarization layer 28 to fill the conductive wiring contact hole.

Next, the second conductive layer is etched or CMP to form contact plugs 30 and 32 connected to the first impurity region 24a and the second impurity region 24b.

Thereafter, a third conductive layer (not shown) is formed on the entire surface to be connected to the contact plugs 30 and 32.

Next, the third conductive layer is etched by using a conductive wiring mask as an etch mask to form an external pad 34 and a voltage input pad 36 connected to the contact plugs 30 and 32.

Meanwhile, a second conductive layer (not shown) filling the conductive wiring contact hole is formed on the planarization layer 28, and then etched using a conductive wiring mask to etch the external pad 34 and the voltage input pad 36. ) Can be formed. (See Figure 2b)

The characteristics of the junction region differ depending on the voltage state applied to the NMOS transistor formed by the above process.

First, when the semiconductor substrate 12 is connected to the ground, and the NMOS transistor is "turned off" by applying 0 V to the gate electrode 18, the semiconductor substrate 12 is "turned off" according to the "turn-off" of the NMOS transistor. The first impurity region 24a and the second impurity region 24b are electrically shorted to monitor only the bonding characteristics of the first impurity region 24a connected to the external pad 34.

On the other hand, when the semiconductor substrate 12 is connected to the ground and the source voltage (Vs) + 3V is applied to the gate electrode 18 to turn the NMOS transistor into a "turn-on" state, the " The first impurity region 24a and the second impurity region 24b are electrically connected to each other according to the turn-on ", so that the junction characteristics of the first impurity region 24a and the junction characteristics of the second impurity region 24b are This is monitored together.

Therefore, in order to measure the pure junction property of the second impurity region 24b, the monitored junction property when the NMOS transistor is "turn-off" is subtracted from the monitored junction property when the NMOS transistor is "turn-on". .

In the method of manufacturing a semiconductor device inspection device according to the present invention, a contact device is not directly formed in an impurity region to be inspected during a manufacturing process of an inspection apparatus for measuring a junction leakage current of an impurity region after an ion implantation process in a semiconductor device manufacturing process. Using the morph transistor, the impurity region is electrically connected to the impurity region connected to the external pad to measure the electrical characteristics, and the pure leakage current characteristic of the impurity region is measured by comparing the prescribed value with the measured value. There is an advantage in improving yield and productivity by improving properties and reliability.

Claims (3)

forming a gate insulating film on the semiconductor substrate including n-well and p-well; Forming a gate electrode on the gate insulating film; Forming an impurity region by implanting impurities into both semiconductor substrates of the gate electrode; Forming a planarization film over the entire surface; Forming a photoresist pattern on the planarization layer exposing a portion of the impurity region on one side of the gate electrode to an external pad contact and a portion of the gate contact to apply a voltage to the gate electrode; Removing the planarization layer by using the photoresist pattern as an etching mask to form a contact hole, and then removing the photoresist pattern; Forming a contact plug to fill the contact hole; Forming a conductive layer on the planarization film; And etching the conductive layer by using a conductive wiring mask as an etch mask to form pads connected to the contact plugs. The method of claim 1, And the gate electrode is formed of a polysilicon layer, a polyside, or a metal layer. The method of claim 1, Forming a contact layer after the contact hole is formed, and forming a pad by etching the conductive layer using an conductive mask as an etching mask.