KR100414678B1 - A method of manufacturing test structure for testing junction leakage current - Google Patents
A method of manufacturing test structure for testing junction leakage current Download PDFInfo
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- KR100414678B1 KR100414678B1 KR10-2001-0088241A KR20010088241A KR100414678B1 KR 100414678 B1 KR100414678 B1 KR 100414678B1 KR 20010088241 A KR20010088241 A KR 20010088241A KR 100414678 B1 KR100414678 B1 KR 100414678B1
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- leakage current
- junction leakage
- salicide
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000012360 testing method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
본 발명은 살리사이드 공정 진행시 정션 누설전류 특성을 분석하고 불량 분석에 적용할 수 있는 반도체 장치의 정션 누설전류 측정용 테스트 구조 제조방법에 관하 것으로, 활성영역과 필드영역을 갖는 반도체 기판에 있어서, 상기 필드영역에 소자격리막을 형성하는 단계와, 상기 활성영역에 소오스/드레인 영역을 형성하는 단계와, 상기 소오스/드레인 영역에 선택적으로 살리사이드을 형성하는 단계와, 상기 살리사이드가 노출되도록 복수개의 콘택홀을 갖는 층간 절연막을 형성하는 단계와, 상기 콘택홀을 매립시키는 플러그를 형성하는 단계와, 상기 플러그와 연결되는 도전층을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method for manufacturing a test structure for measuring the junction leakage current of a semiconductor device that can be applied to the analysis of the junction leakage current during the salicide process and to the failure analysis. The present invention relates to a semiconductor substrate having an active region and a field region. Forming a device isolation layer in the field region, forming a source / drain region in the active region, selectively forming a salicide in the source / drain region, and a plurality of contacts to expose the salicide Forming an interlayer insulating film having holes, forming a plug filling the contact hole, and forming a conductive layer connected to the plug.
Description
본 발명은 반도체 장치의 정션 누설전류 측정용 테스트 구조 제조방법에 관한 것으로, 특히 살리사이드(salliide) 공정 진행시 정션 누설전류 특성을 분석하고 불량 분석에 적용할 수 있는 반도체 장치의 정션 누설전류 측정용 테스트 구조 제조방법에 관하 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a test structure for measuring junction leakage current of semiconductor devices. In particular, the present invention relates to a method for manufacturing junction leakage current of semiconductor devices that can be applied to failure analysis and analysis of junction leakage current characteristics during the salicide process. The test structure manufacturing method will be described.
일반적으로 반도체 소자의 고집적화에 따라 MOS 트랜지스터의 크기가 작아지고, MOS 트랜지스터의 소오스/드레인 영역의 접합깊이도 점점 얕아지게 되었다. 이렇게 소오스/드레인 영역의 접합깊이가 점점 얕아지면, 접합의 면저항은 접합깊이에 반비례하기 때문에 면저항이 증가되므로 소자의 기생저항(parasitic resistance)이 증가하는 문제가 발생한다.In general, the higher the integration of semiconductor devices, the smaller the size of the MOS transistor and the shallower the junction depth of the source / drain regions of the MOS transistor. As the junction depth of the source / drain regions becomes shallower in this manner, the sheet resistance of the junction is inversely proportional to the junction depth, resulting in an increase in the parasitic resistance of the device.
결국, 반도체 소자의 크기를 줄이기 위해서는 접합의 깊이도 얕아져야 하는 반면, 면저항도 줄여야 하므로 비저항을 줄여야 한다.As a result, in order to reduce the size of the semiconductor device, the depth of the junction must be shallow, while the sheet resistance must be reduced, so the specific resistance must be reduced.
따라서 실리사이드막을 얇은 접합의 소오스/드레인 영역에 형성하므로써 접합의 면저항을 감소시킬 수 있다.Therefore, the sheet resistance of the junction can be reduced by forming the silicide film in the source / drain regions of the thin junction.
상기와 같은 실리사이드막은 크게 고융점 금속과 폴리 실리콘과의 반응에 의해 형성되는 폴리사이드(polycide)와 고융점 금속과 실리콘과의 반응에 의해 형성되는 살리사이드(SALICIDE:self-aligned silicide)로 나뉘어지며, 이러한 실리사이드막으로는 티타늄 실리사이드막(TiSi2)이 널리 알려져 있다.The silicide layer is largely divided into a polycide formed by the reaction between the high melting point metal and the polysilicon and a salicide (SALICIDE: self-aligned silicide) formed by the reaction between the high melting point metal and the silicon. As such a silicide film, a titanium silicide film (TiSi 2 ) is widely known.
한편, 소오스/드레인 영역에 실리사이드막을 형성하게 되면 실리사이드막의 형성 두께에 대응하는 깊이 만큼 실리콘으로 된 소오스/드레인 영역부분의 소모를 수반하게 된다. 즉, 실리사이드막의 형성 두께에 따라 정션 누설전류 특성의 변화 및 공정 변수에 따른 정션 누설전류 특성의 변화가 크다.On the other hand, when the silicide film is formed in the source / drain region, the source / drain region portion of silicon is consumed by a depth corresponding to the formation thickness of the silicide film. That is, the change in junction leakage current characteristics according to the formation thickness of the silicide film and the change in junction leakage current characteristic according to process variables are large.
한편, 정션 누설전류는 반도체장치의 스탠-바이-전류(Stand by Current) 특성에 큰 영향을 주기 때문에 정션 누설전류 특성을 측정하는 것이 매우 중요하다.On the other hand, it is very important to measure the junction leakage current characteristics because the junction leakage current has a great influence on the stand-by-current characteristics of the semiconductor device.
이하, 첨부된 도면을 참조하여 종래의 반도체 장치의 정션 누설전류 측정용 테스트 구조 제조방법에 대하여 설명하기로 한다.Hereinafter, a method of manufacturing a test structure for measuring junction leakage current of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래의 반도체 장치의 정션 누설전류 측정용 테스트 구조의 제조방법을 나타낸 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of manufacturing a test structure for measuring junction leakage current of a conventional semiconductor device.
도 1a에 도시한 바와 같이 반도체 기판(10)에 활성영역 및 필드영역을 정의한 후, 상기 필드영역을 선택적으로 식각하여 트랜치를 형성하고, 상기 트랜치에 산화막을 매립하여 소자격리막(11)을 형성한다.After defining active and field regions in the semiconductor substrate 10 as shown in FIG. 1A, trenches are formed by selectively etching the field regions, and an isolation layer 11 is formed by filling an oxide layer in the trenches. .
그리고 상기 활성영역에 게이트 전극(도면에 도시하지 않았음)을 형성하고, 불순물 이온주입 공정을 통해 상기 게이트 전극 측면의 반도체 기판(10)에 소오스/드레인 영역(12)을 형성한 후, 상기 소오스/드레인 영역(12)에 살리사이드층(13)를 형성한다.A gate electrode (not shown) is formed in the active region, and a source / drain region 12 is formed in the semiconductor substrate 10 on the side of the gate electrode through an impurity ion implantation process. The salicide layer 13 is formed in the / drain region 12.
도 1b에 도시한 바와 같이 상기 결과물 상부에 층간 절연막(14)을 형성하고, 상기 소오스/드레인 영역(12) 즉, 실시사이드층(13) 선택적으로 노출되도록 복수개의 콘택홀(15)을 형성한다.As shown in FIG. 1B, an interlayer insulating layer 14 is formed on the resultant, and a plurality of contact holes 15 are formed to selectively expose the source / drain region 12, that is, the execution side layer 13. .
상기 콘택홀(15)을 포함한 층간 절연막(14)상에 제 1 도전층을 증착하고, CMP 공정 및 전면식각 공정을 통해 상기 콘택홀(15)에 매립되는 플러그(16)를 형성한다.A first conductive layer is deposited on the interlayer insulating layer 14 including the contact hole 15, and a plug 16 embedded in the contact hole 15 is formed through a CMP process and an entire surface etching process.
도 1c에 도시한 바와 같이 상기 결과물 상부에 제 2 도전층(17)을 증착하여반도체 장치의 정션 누설전류를 측정한다.As illustrated in FIG. 1C, a second conductive layer 17 is deposited on the resultant to measure junction leakage current of the semiconductor device.
그러나 상기와 같은 종래의 반도체 장치의 정션 누설전류 측정용 테스트 구조 제조방법에 있어서는 다음과 같은 문제점이 있었다.However, the above-described conventional method for manufacturing a test structure for measuring junction leakage current of a semiconductor device has the following problems.
살리사이드 공정이 진행되는 경우 모든 활성영역에 살리사이드가 형성되므로 살리사이드에 의한 정션 누설전류 특성을 따라 분석하고 불량분석을 하기가 어렵다.When the salicide process is performed, salicide is formed in all active regions, so it is difficult to analyze according to the junction leakage current characteristic by the salicide and to perform a defect analysis.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 살리사이드에 의한 누설전류 특성을 비교할 수 있도록 하여 반도체 장치의 스탠-바이-전류의 분석을 용이하게 할 수 있는 반도체 장치의 정션 누설전류 측정용 테스트 구조 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is possible to compare the leakage current characteristics by salicide so that the analysis of the junction leakage current of a semiconductor device can facilitate the analysis of the stand-by-current of the semiconductor device. Its purpose is to provide a test structure manufacturing method.
도 1a 내지 도 1c는 종래의 반도체 장치의 정션 누설전류 측정용 테스트 구조의 제조방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method of manufacturing a test structure for measuring junction leakage current of a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명의 일실시예에 따른 반도체 장치의 정션 누설전류 측정용 테스트 구조의 제조방법을 나타낸 공정 단면도2A to 2C are cross-sectional views illustrating a method of manufacturing a test structure for measuring junction leakage current of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
100 : 반도체 기판 101 : 소자격리막100 semiconductor substrate 101 device isolation film
102 : 소오스/드레인 영역 103 : 포토레지스트102 source / drain region 103 photoresist
104 : 실리사이드층 105 : 층간 절연막104: silicide layer 105: interlayer insulating film
106 : 콘택홀 107 : 플러그106: contact hole 107: plug
108 : 제 2 도전층108: second conductive layer
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 장치의 정션 누설전류 측정용 테스트 구조 제조방법은 활성영역과 필드영역을 갖는 반도체 기판에 있어서, 상기 필드영역에 소자격리막을 형성하는 단계와, 상기 활성영역에 소오스/드레인 영역을 형성하는 단계와, 상기 소오스/드레인 영역에 선택적으로 살리사이드을 형성하는 단계와, 상기 살리사이드가 노출되도록 복수개의 콘택홀을 갖는 층간 절연막을 형성하는 단계와, 상기 콘택홀을 매립시키는 플러그를 형성하는 단계와, 상기 플러그와 연결되는 도전층을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a test structure for measuring a junction leakage current of a semiconductor device according to the present invention includes forming a device isolation film in the field region in a semiconductor substrate having an active region and a field region; Forming a source / drain region in the region, selectively forming a salicide in the source / drain region, forming an interlayer insulating film having a plurality of contact holes to expose the salicide, and forming the contact hole; Forming a plug for embedding the, and forming a conductive layer connected to the plug.
또한, 상기 살리사이드는 소오스/드레인 영역상의 콘택이 형성되는 일부분만형성시키는 것이 바람직하다.In addition, the salicide preferably forms only a portion of the contact on the source / drain region.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 장치의 정션 누설전류 측정용 테스트 구조 제조방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a test structure for measuring junction leakage current of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 일실시예에 따른 반도체 장치의 정션 누설전류 측정용 테스트 구조 제조방법을 나타낸 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a test structure for measuring junction leakage current of a semiconductor device according to an embodiment of the present invention.
도 2a에 도시한 바와 같이 반도체 기판(100)에 활성영역 및 필드영역을 정의한 후, 상기 필드영역을 선택적으로 식각하여 트랜치를 형성하고, 상기 트랜치에 산화막을 매립하여 소자격리막(101)을 형성한다.As shown in FIG. 2A, an active region and a field region are defined in the semiconductor substrate 100, and then, the field region is selectively etched to form a trench, and an oxide film is embedded in the trench to form an isolation layer 101. .
그리고 상기 활성영역에 게이트 전극(도면에 도시하지 않았음)을 형성하고, 불순물 이온주입 공정을 통해 상기 게이트 전극 측면의 반도체 기판(100)에 소오스/드레인 영역(102)을 형성한다.A gate electrode (not shown) is formed in the active region, and a source / drain region 102 is formed in the semiconductor substrate 100 on the side of the gate electrode through an impurity ion implantation process.
이어, 상기 소오스/드레인 영역(102)상에 포토레지스트(103)를 증착하고, 노광 및 현상공정을 이용하여 패터닝한 후, 상기 패터닝된 포토레지스트(103)를 마스크로 이용하여 상기 노출된 소오스/드레인 영역(102)에 살리사이드층(104)을 선택적으로 형성한다.Subsequently, the photoresist 103 is deposited on the source / drain region 102 and patterned using an exposure and development process, and then the exposed source / drain is formed using the patterned photoresist 103 as a mask. The salicide layer 104 is selectively formed in the drain region 102.
도 2b에 도시한 바와 같이 상기 패터닝된 포토레지스트(103)를 제거한 후, 상기 결과물 상부에 층간 절연막(105)을 형성하고, 상기 살리사이드층(104)이 노출되도록 상기 층간 절연막(105)을 선택적으로 식각하여 복수개의 콘택홀(106)을 형성한다.After removing the patterned photoresist 103 as shown in FIG. 2B, an interlayer insulating layer 105 is formed on the resultant, and the interlayer insulating layer 105 is selectively selected so that the salicide layer 104 is exposed. Etching to form a plurality of contact holes (106).
이어, 상기 콘택홀(106)을 포함한 층간 절연막(105)상에 제 1 도전층을 증착하고, CMP 공정 및 전면식각 공정을 통해 상기 콘택홀(106)에 매립되는 플러그(107)를 형성한다.Subsequently, a first conductive layer is deposited on the interlayer insulating layer 105 including the contact hole 106, and a plug 107 embedded in the contact hole 106 is formed through a CMP process and an entire surface etching process.
도 2c에 도시한 바와 같이 상기 결과물 상부에 제 2 도전층(108)을 증착하여 반도체 장치의 정션 누설전류를 측정함으로써 반도체 장치의 스탠-바이-전류 분석이 용이하다.As illustrated in FIG. 2C, the second conductive layer 108 is deposited on the resultant to measure junction leakage current of the semiconductor device, thereby facilitating stand-by-current analysis of the semiconductor device.
이상에서 설명한 바와 같이 본 발명의 반도체 장치의 정션 누설전류 측정용 테스트 구조 제조방법에 의하면, 살리사이드에 의한 누설전류 특성을 비교하여 반도체 장치의 스탠-바이-전류의 분석을 용이하다.As described above, according to the test structure manufacturing method for measuring the junction leakage current of the semiconductor device of the present invention, it is easy to analyze the stand-by-current of the semiconductor device by comparing the leakage current characteristics by salicide.
따라서, 반도체 장치의 불량분석이 용이하고 정션 특성에 의한 불량분석 결과를 신속히 피드-백(Feed Back)할 수 있어 신속한 공정의 실험을 통해 반도체 장치의 수율을 향상시킬 수 있는 효과가 있다.Therefore, it is easy to analyze the defect of the semiconductor device and can quickly feed back the defect analysis result due to the junction characteristic, thereby improving the yield of the semiconductor device through a rapid process experiment.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5759871A (en) * | 1996-07-26 | 1998-06-02 | Advanced Micro Devices, Inc. | Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques |
| US5931106A (en) * | 1997-05-30 | 1999-08-03 | Durkopp Adler Aktiengesellschaft | Buttonhole sewing machine, with a needle-thread clamp and cutter |
| KR20000043191A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Manufacturing method of monitoring apparatus of semiconductor device |
| US6165807A (en) * | 1999-01-25 | 2000-12-26 | Taiwan Smiconductor Manufacturing Company | Method for forming junction leakage monitor for mosfets with silicide contacts |
| US6249138B1 (en) * | 1999-11-23 | 2001-06-19 | United Microelectronics Corp. | Method for testing leakage current caused self-aligned silicide |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5759871A (en) * | 1996-07-26 | 1998-06-02 | Advanced Micro Devices, Inc. | Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques |
| US6037607A (en) * | 1996-07-26 | 2000-03-14 | Advanced Micro Devices, Inc. | Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques |
| US5931106A (en) * | 1997-05-30 | 1999-08-03 | Durkopp Adler Aktiengesellschaft | Buttonhole sewing machine, with a needle-thread clamp and cutter |
| KR20000043191A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Manufacturing method of monitoring apparatus of semiconductor device |
| US6165807A (en) * | 1999-01-25 | 2000-12-26 | Taiwan Smiconductor Manufacturing Company | Method for forming junction leakage monitor for mosfets with silicide contacts |
| US6249138B1 (en) * | 1999-11-23 | 2001-06-19 | United Microelectronics Corp. | Method for testing leakage current caused self-aligned silicide |
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