TW472357B - Bypass circuits for reducing plasma damage - Google Patents

Abstract

The present invention provides a method for reducing plasma damage to a gate oxide of a metal-oxide semiconductor (MOS) transistor positioned on a substrate of a MOS semiconductor wafer. The method begins with the formation of a dielectric layer covering the MOS transistor on the substrate. An etching process is then performed to form a first contact hole through the dielectric layer to a gate on the surface of the MOS transistor, as well as to form a second contact hole through the dielectric layer to an n-well in the substrate. A bypass circuit, positioned on the dielectric layer and the first and second contact holes, and a fusion area are then formed. The fusion area, electrically connecting with the bypass circuit, also electrically connects with the MOS transistor and the n-well thereafter. Ions produced during the process are thus transferred to the n-well via the conductive wire so as to reduce plasma damage to the gate oxide. The fusion area is finally disconnected after the formation of the MOS transistor.

Description

mm V. Description of the invention (1) Field of the invention The present invention provides a conducting circuit for a metal oxide semiconductor (MOS) transistor to reduce the electric current suffered by the gate oxide of the MOS transistor. Plasma damage ° Background Description Metal-oxide semiconductor (MOS) transistors are one of the most commonly used electronic components in integrated circuits. The M0S transistor is a four-contact element composed of three different electrodes: gate, source, and dr ain. It mainly uses the gate of the M0S transistor to switch between different gates. The channel effect formed under the extreme voltage is used as a digita 1 zed solid-state switch between the source and the non-electrode to match other components used in various logic and memory integrated circuit products. on. Please refer to FIGS. 1 to 4, which are schematic diagrams of a conventional method for manufacturing a MOS transistor. As shown in FIG. 1, the conventional M0S transistor is fabricated on a semiconductor wafer 10. The semiconductor wafer i 〇 includes a silicon substrate (si 1 icon substrate 12) and a gate 16 provided on the silicon substrate 1. A gate oxide layer 14 ′ is further provided between the gate electrode 16 and the silicon substrate 12 and is disposed on the surface of the substrate 12.

V. Description of the invention (2) Next, as shown in FIG. 2, a first ion implantation (ion imp 1 antati ο η) process 1 8 ′ is performed on the silicon substrate 12 on both sides of the gate electrode 16 to form a second doped layer. The miscellaneous region is used as the lightly doped drain (LDD) 22 of the M 0 S transistor, which is also referred to as the source-drain extension (SDE). An insulator is used to form a spacer 2 4 around the vertical sidewall of the gate electrode 16. Then, as shown in FIG. 4, a second ion implantation process 26 is performed, and the silicon substrate 12 on the outer edge of the side wall 24 is raised; j is a doped region, and is used as the source of the μ MOS transistor ( s 〇urce) 2 7 and drain 28 'to complete the process of M0S transistor, as shown in Figure 4. Please refer to FIG. 5. FIG. 5 is a schematic diagram of a conventional method for performing a self-alignment silicide (Salicide) process on a MOS transistor. After the M0S transistor process is completed, most of the current semiconductor processes will add a self-aligned silicide process, or in the previous process, they will be at the gate 16, source 27, and drain 2 8 respectively. A layer of polycrystalline metal silicide (pOlycide) is flooded on the silicon surface to reduce the contact resistance of each Shi Xiwu surface. Therefore, after completing the self-aligned lithography to produce jade, a metal silicide layer 32 'is formed on the surface of the gate 1 β, the source 27 and the end 28 of the M 0 S transistor to reduce each silicon. Contact resistance on rough surfaces.

Page 7mm V. Description of the invention (3) However, during the process of making MOS transistors, it was performed during plasma etching, ion bombardment, and development (ph 〇t 〇pr 〇cess). Steps such as ultraviolet radiation (UV radiation) may cause a large number of electrons to accumulate in the gate, and then the phenomenon of current penetrating from the gate into the silicon substrate, which is commonly known as "antenna effect" (ante antenna effect). This antenna effect will cause the degradation of the gate oxide layer (d e g r a d a t i ο η), which is also known as "plasma induced damage" (PPID), and then seriously affects the function of the MOS transistor. Therefore, how to avoid the accumulation of electrons in the gate of the MOS transistor and cause the gate oxide layer to be damaged by the plasma is an important issue that cannot be delayed. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for reducing plasma process induced damage (PPID) of a gate oxide layer of a metal oxide semiconductor (MOS) transistor, so as to solve the problems of the conventional manufacturing method. . In a preferred embodiment of the present invention, the MOS transistor system is provided on a substrate of a semi-conductor wafer. First, a dielectric layer is formed on the substrate to cover the MOS transistor, and a first contact hole is etched into the dielectric layer to reach the top of the MOS transistor, and a second contact hole is passed to the substrate. One of the n-wells. Then on the dielectric layer, the first connection

Page 8 mmi 5. Description of the invention (4) A conductive circuit (bypass) composed of a metal layer is formed in the contact hole and the second contact hole, and an electrical connection is formed in the conductive circuit by an extremely thin width. The metal wire 'or the power-off region made of polycrystalline silicon electrically connects the M 0 S transistor to the N-type well. Finally, after the manufacturing process of the MOS transistor is completed, a part of the wires in the power-off area is melted in a high temperature manner, or a laser beam is irradiated to the power-off area to cut off the electrical connection of the power-off area. Since the manufacturing method of the present invention electrically connects the MOS transistor to the N-type well through a diversion circuit, the gate electrode is caused by plasma etching (ρ 1 asma etching) and ion bombardment. And the ultraviolet radiation (UV radiati ο η >) performed during the photo process can be guided to the N-type well by the flow guide circuit to form electrical properties with the ions in the N-type well Neutralization. Therefore, the manufacturing method of the present invention can prevent the occurrence of antenna effect, thereby reducing the plasma process induced damage (P ID) of the gate oxide layer, and effectively ensure the M 0 S power Normal operation of the crystal.

Figures oe, t M ca to < O show r Ming Liu body p s ^ b said the map guide a six u ms detailed examination of the half s figure detailed parameters U such as on p C please oxygen ◦ i-Huiming is harmful One concern] _ 1 Gold damage C11, Figures 6 to 11 show the method of reducing plasma ss induced damage (PPID) suffered by a gate oxide layer of a transistor according to the present invention, which shows a semiconductor wafer 40 includes a silicon substrate e) 4 2 and a gate 4 6 located at Shi Xiji.

V. Description of the invention (5) On the bottom 42, a gate oxide layer 44 is provided between the intermediate electrode 46 and the silicon substrate 42 and is provided on the surface of the silicon substrate 42. In addition, an N-well 50 is located in the silicon substrate 42 within a distance of 46-segment from the gate electrode, and the N-well 50 is at least separated from the MOS transistor by a shallow distance. Trench Isolation (STI) 70. Next, as shown in FIG. 7, a first ion implantation (i 〇η im ρ 1 antati ο η) process 4 8 ′ is performed to form a two-doped region on the silicon substrate 4 2 surface layer on both sides of the gate 4 6. Let's use it as lightly doped drain (LDD) 52 'of M0S transistor. It is also called Source-Drain Extension (SDE). As shown in Figure 8, then an insulating material is used to A spacer 5 4 is formed around the vertical sidewall of the gate electrode 46. Then, as shown in FIG. 9, a second ion implantation process 5 6 ′ is performed to form a two-doped region on the stone substrate 4 2 on the outer edge of the side wall 5 4 as the source of the MOS transistor 57 And the pole 58 (drain). 'Next, as shown in FIG. 10, a dielectric layer 60 is formed on the silicon substrate 42 to cover the MOS transistor, and a first ^ contact hole 62 is etched in the dielectric layer 60 to reach the MOS electrode. The top of the crystal and a second contact hole 64 lead to the N-type well 50 on the silicon substrate 42. Then, as shown in FIG.]-, A conductive plug (Plug) composed of a crane metal layer or other conductive material is formed on the dielectric layer 60, inside the first contact hole 62 and the second contact hole 64. And is a known bypass circuit (6) for metal interconnection, and then uses deposition and yellow light

Page 10 V. Description of the invention (6) cum surname-process (PEP), forming the required metal interconnects on the dielectric layer 60, and at the same time defining the pattern of the conductive circuit 66 Subsequently, the polycrystalline silicon deposition and the yellow light and etching process (PEP) are used to form a power-off region 68 in the diversion circuit 66 on the dielectric layer 60, so that the MOS transistor and the N-type well 50 are formed. Electrical connection so that the ions accumulated in the process steps of plasma etching, ion bombardment, photo process, and UV radiation in subsequent processes can be passed through the flow guide circuit 6 6 is guided into the N-type well 50, or the ions in the gate 46 can be guided to the n-type well 5 0 through the current-conducting circuit 6 6 to form electricity with the ions in the N-type well 50. Neutralize to reduce the gate oxide layer 4 to suffer from plasma damage. Among them, in the power failure region of the circuit 66, the gate of the polycrystalline silicon (PEP) system is completed, which can lead to electrical conduction. After completion of the process of the present invention, the dielectric layer 60 can also be formed. The current-conducting and power-off region 6 8 ′ then forms a metal interconnect layer that electrically connects the Mos transistor, 68, and N-type well 50. In addition, the power-off region 68 formed by the use can also be formed in the private crystal of the reduced crystal 'that is, the yellow light and etching process using the meaning electrode 46' are used to simultaneously form the patterns of the gate electrodes 46 and the current guiding circuit 66 . After the most damaging processes such as plasma etching, ion bombardment, development, and ultraviolet radiation, the power-off area line is melted in a high-temperature manner. "-Laser light irradiates _ electricity area 68 to block electricity into the M0S electricity. Crystal manufacturing process. Compared to 知 知 技 # ί, the manufacturing method of the present invention

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V. Description of the invention (7) 2 The MOS transistor is electrically connected to the n-type well, so the gate electrode is developed by a photo process due to plasma etching and ion bombardment (r). The ions accumulated during the ultraviolet radiation (uv 1 a11 on) and other steps can be coughed into the N-type well through the flow guide circuit, and electrically neutralize with the ions in the N-type well, so it can prevent ions. It accumulates in the gate 'and then generates a current penetrating from the gate to $ =', which is commonly known as the "antenna effect" (ante η naeffect) phenomenon. = The manufacturing method of the present invention can reduce the electrical equipment Z = (plasma process induced damage, PPID), slow down the degradation of the bucket and the formation, and ensure the normal operation of the MOS transistor. Often, the above are only the preferred embodiments of the present invention, and any equivalent changes and modifications made according to the scope of the present invention shall belong to the patent claims of the present invention. <Han Xiang

Page 12 ㈣357 Brief description of the diagrams Brief description of the diagrams Figures 1 to 4 are schematic diagrams of conventional methods for making MOS transistors. Figure 5 is a schematic diagram of a method for performing a self-aligned silicide process by a conventional MOS transistor. Figures 6 to 11 illustrate a method for reducing plasma damage to a gate oxide layer of a metal oxide semiconductor (MOS) transistor according to the present invention. schematic diagram. Explanation of symbols in the diagram 10 Semiconductor wafer 1 2 Xi substrate 14 Gate oxide layer 16 Intermediate electrode 18 First ion implantation process 2 2 Lightly doped electrode 24 Side wall 27 Source 32 Metal silicide layer 42 Silicon substrate 46 Question pole 50 N-type well 54 Side wall 57 Source electrode 60 Dielectric layer 64 Second contact hole 68 Power off area 26 Second ion implantation process 28 Drain 40 Semiconductor wafer 4 4 Idle oxide layer 48 First ion cloth Implantation process 5 2 Lightly doped poles 56 Second ion implantation process 5 8 poles 62 First contact holes 66 Diversion circuits 70 Shallow trench isolation

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Claims (1)

47 move? 6. Scope of Patent Application 1. A flow-conducting circuit for reducing the gate oxide layer (gate 〇xlde) between a metal oxide semiconductor (ffletal-0Xlde semicoru ^ ctor, MOS) transistor and plasma damage The diversion circuit is disposed on a semiconductor wafer, the semiconductor wafer includes a substrate, the MOS transistor is disposed on the substrate, a dielectric layer covers the MOS transistor, and the diversion circuit A bypass circuit is disposed on the dielectric layer, and the current guiding circuit includes: a wire including at least a first contact end and a second contact end, and the first contact end is electrically connected to the MOS A gate conductive layer on top of the transistor, and the second contact terminal is electrically connected to a doped region on the substrate, and a power-off region is provided in the wire to cut off the wire from the The electrical connection of the M 0S transistor; wherein the ions in the gate oxide layer are guided to the doped region through the wire to reduce the gate oxide layer from being damaged by the plasma. 1 'The current-conducting circuit according to item 1 of the scope of patent application, wherein the wire is composed of a plurality of contact plugs (contact piUg) and a metal layer. 3. For example, the current-conducting circuit of the scope of patent application, wherein the wire is part of a metal interconnect. 4. The current-conducting circuit according to item 1 of the patent application range, wherein the power-off area is made of polycrystalline silicon. Page 14 ㈣357 6. Scope of Patent Application 5. For example, the current-conducting circuit of the scope of patent application No. 1 in which the doped region is an N-well. 6. The current-conducting circuit according to item 1 of the patent application, wherein the ions in the gate oxide layer are electrically neutralized with the ions in the doped region through the wire to reduce the gate oxide layer from being subjected to electricity. Pulp damage. 7. A method for reducing the plasma damage of a gate oxide layer of a metal oxide semiconductor (MOS) transistor. The MOS transistor system is provided on a substrate of a semiconductor wafer. The method includes the following steps: A dielectric layer is formed on the substrate to cover the MOS transistor; a first contact hole is etched into the dielectric layer to reach the top of the MOS transistor, and a second contact hole is passed to one of the substrates. A miscellaneous region; a bypass circuit is formed on the dielectric layer, in the first contact hole and the second contact hole, and a power-off region is electrically connected in the current guide circuit, so that the M 0 S The transistor forms an electrical connection with the doping region, and cuts off the electrical connection in the power-off region after the MOS transistor is completed; wherein the ions in the gate oxide layer are guided to the transistor through the current-conducting circuit. Doped region to reduce plasma damage to the gate oxide layer. 8. The method according to item 7 of the patent application, wherein the current guiding circuit is composed of a metal layer. Page 15 6. Scope of patent application 9. For the method of scope 7 of the patent application, the current-conducting circuit is part of a metal interconnect. 10. The method according to item 7 of the scope of patent application, wherein the power-off region is made of polycrystalline silicon. Π. The method according to item 7 of the application, wherein the doped region is an N-well. 1 2 _ If the method in the scope of patent application No. 7, wherein the method of cutting off the power-off area is to melt a part of the wires in the power-off area in a high temperature manner to block the electrical connection. 1 3. The method according to item 7 of the scope of patent application, wherein the method of cutting off the power-off area is irradiating the power-off area with a laser light. 14. The method according to item 7 of the scope of patent application, wherein the ions in the gate oxide layer are electrically neutralized with the ions in the doped region through the current guiding circuit to reduce the gate oxide layer ’s exposure Plasma damage. 15. —A bypass circuit for reducing the plasma damage of the gate oxide layer of a metal oxide semiconductor (MOS) transistor, the bypass circuit is provided on a semiconductor wafer, and the semiconductor wafer Contains a base on it, Page 16 ㈣357 6. Patent application scope At least one MOS transistor is provided on the substrate. The current guiding circuit includes: a wire including at least a first contact end and a second contact end, and the first contact end is Electrically connected to a gate conductive layer of the MOS transistor, and the second contact terminal is electrically connected to a doped region on the substrate; and a power-off region is provided in the wire for cutting off The wire is electrically connected to the MOS transistor; wherein the ions in the gate oxide layer are guided to the doped region through the wire to reduce the gate oxide layer from being damaged by the plasma. 16. The current-conducting circuit according to item 15 of the scope of patent application, wherein the wire is composed of a plurality of contact plugs (c ο n t a c t ρ 1 u g) and a metal layer. 17. The current-conducting circuit according to item 15 of the scope of patent application, wherein the wire is a part of a metal interconnect. 1 8. The current-conducting circuit according to item 15 of the scope of patent application, wherein the power-off area is composed of polycrystalline stone. 19. The current-conducting circuit according to item 15 of the application, wherein the doped region is an N-type well (η-w e 1 1). 20. The current-conducting circuit according to item 15 of the scope of patent application, wherein the ions in the gate oxide layer are electrically formed with the ions in the doped region through the wire. Page 17 ㈣357 Page 18