KR20010003048A - Method for forming contact in semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a contact of a semiconductor device is provided to easily control a gap between a plug and a bit line, by forming a plug for electrically connecting a storage electrode and the first plug poly before the bit line and an interlayer dielectric are formed. CONSTITUTION: A semiconductor substrate(20) is prepared which includes a gate electrode having a spacer(24) and a hard mask layer(23) and source/drain regions(25A,25B) on both sides of the gate electrode. The first plug poly(26A,26B) contacting the source/drain regions is formed in a space of both sides of the gate electrode. The second plug poly(27) having a predetermined height is formed on the first plug poly contacting the source region. A bit line(28A) is formed on the first plug poly contacting the drain region. An interlayer planarized layer(30) having the same height as the second plug poly is formed on the resultant structure. A storage electrode(31) contacting the second plug poly is formed.

Description

Method for forming contact in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to forming a contact of a semiconductor device capable of preventing a short circuit between adjacent conductors due to misalignment in a highly integrated semiconductor device. It is about a method.

In recent years, as the integration degree of a MOSFET device rapidly increases, correspondingly, the line width of the gate electrode and the distance between the gate electrodes are rapidly reduced. As a result, since the bit line and the junction region have difficulty in direct contact, a method using a plug poly has been conventionally proposed.

That is, as shown in FIG. 1, the gate insulating film 2, the gate electrode conductive layer 3, and the hard mask film 4 are sequentially stacked on the semiconductor substrate 1, and then predetermined portions are patterned. The gate electrode g is formed. The spacers 5 are formed on the side walls of the gate electrode g by a known method. Then, impurities are injected into the substrate 1 on both sides of the spacer 5 to form source and drain regions 6A and 6B. Then, a polysilicon film is deposited on the resultant to a thickness sufficient to be in contact with the source and drain regions 6A and 6B, and then partially patterned to form a plug poly 8. Thereafter, the first interlayer insulating film 9 is formed on the resultant product in which the plug poly 8 is formed. Subsequently, the first interlayer insulating film 9 is etched to expose the plug poly 8B in contact with the drain region 6B, thereby forming a bit line contact hole (not shown). Thereafter, a bit line 10 is formed over the first interlayer insulating film 9 to contact the exposed plug poly 8B. Thereafter, a second interlayer insulating layer 11 is formed on the resultant bit line 10. Then, the second and first interlayer insulating layers 11 and 9 are etched to form a storage contact hole so that the plug poly 8A in contact with the source 6A can be exposed. At this time, since the thicknesses of the first and second interlayer insulating films 11 and 9 are relatively thick, in order to form a smooth contact, the contact hole is formed so that the radius of the inlet portion is larger than the contact portion. Thereafter, the storage electrode 12 is formed in the storage contact hole.

However, when the plug poly is used, it is effective to improve the high step, but the gap between the contacts is very fine, as shown in FIG. 1, between the storage node electrode 12 and the bit line 10. Short is easy to occur.

As a result, a fail of the semiconductor element occurs.

Accordingly, an object of the present invention is to provide a method for forming a contact of a semiconductor device capable of preventing a short between a storage node electrode and a bit line.

1 is a cross-sectional view for explaining a contact forming method of a conventional semiconductor device.

2A to 2E are cross-sectional views of respective processes for explaining a method for forming a contact of a semiconductor device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

20-semiconductor substrate 21-gate oxide

Conductive layer for 22-gate electrode 23-hard mask film

24-spacer 25A, 25B-source, drain region

26A, 26B-1st plug pulley 27-2nd plug pulley

28A-Bit Line 29-Resist Pattern

30-layer planarization film 31-storage electrode

In order to achieve the above object of the present invention, the present invention comprises the steps of providing a gate electrode having a spacer and a hard mask film, and a semiconductor substrate having a source, a drain region formed on both sides of the gate electrode; Forming a first plug poly in contact with a source and a drain region in spaces on both sides of the spacer of the gate electrode; Forming a first plug pulley contacting the source region and a second plug pulley having a predetermined height thereon; Forming a bit line over the first plug poly in contact with the drain region; Forming an interlayer planarization layer on the semiconductor substrate to have the same height as the second plug poly; And forming a storage electrode on the interlayer planarization layer to contact the second plug poly.

According to the present invention, a plug for electrically connecting the storage electrode and the first plug poly is formed in advance before forming the bit line and the interlayer planarization film (or the interlayer insulation film). Accordingly, the distance between the plug and the bit line for electrically connecting the storage electrode and the first plug pulley can be easily adjusted to prevent short circuit with the bit line.

Furthermore, since the storage node contact hole having a relatively deep depth is not formed and the trouble of filling it up is eliminated, the contact characteristic can be improved.

(Example)

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2A to 2E are cross-sectional views of respective processes for explaining a method for forming a contact of a semiconductor device according to the present invention.

First, as shown in FIG. 2A, the gate insulating film 21, the gate electrode conductive layer 22, and the hard mask film 23 are sequentially stacked on the semiconductor substrate 20, and then predetermined. Partial patterning is performed to form the gate electrode (G). The conductive layer 22 for the gate electrode may be formed of a doped polysilicon film and a transition metal silicide film. The spacers 24 are formed on both sidewalls of the gate electrode G by a known method. Then, impurities are implanted into the substrate 20 on both sides of the spacer 24 to form source and drain regions 25A and 25B. Then, a thickness of the polysilicon film, for example, 5000 to 1000 micrometers, is deposited to a thickness sufficient to contact the source and drain regions 25A and 25B on the resultant, and then the surface of the hard mask film 23 is exposed. By chemical mechanical polishing, first plug pulleys 26A and 26B are formed. In this case, the first plug polys 26A and 26B are contacted with the source and drain regions 25A and 25B and are buried in the space between the spacers 24.

Next, as shown in FIG. 2B, a polysilicon layer is formed to a predetermined thickness, for example, 2,000 to 10,000 micrometers thick, on top of the resultant product on which the first plug polys 26A and 26B are formed. Next, a predetermined partial pattern is made to contact the first plug pulley 26A which contacts the source region 26A, thereby forming the second plug pulley 27. At this time, the etching for forming the second plug poly 27 is performed using a C ₂ F ₆ / Cl ₂ / O ₂ gas at a pressure of 5 to 20mT and an energy of 50 to 500W.

As shown in FIG. 2C, the polysilicon film 28 for the bitline is formed shallower than the second plug poly 27, for example, about 500 to 2000 micrometers thick, on the resultant on which the second plug poly 27 is formed. do. Next, the photoresist pattern 29 is formed at a position corresponding to the first plug poly 27 that is in contact with the drain region 25B.

Referring to FIG. 2D, the bit line polysilicon film 28 is patterned using the photoresist pattern 29 as a mask to form the bit line 28A. At this time, in forming the bit line 28A, it is preferable to carefully etch until the surface of the second plug poly 27 is exposed, that is, the second plug poly 27 is not removed. The patterning is carried out using a C ₂ F ₆ / Cl ₂ / O ₂ / N ₂ gas at a pressure of 5 to 20 mT and an energy of 200 to 500 W. After patterning, the photoresist pattern 29 is removed by a known method. The bit line 28A thus formed is disposed at a predetermined distance from the second plug pulley 27 and has a lower height than the second plug pulley 27.

Then, as shown in FIG. 2E, an interlayer planarization film 30, for example, a BPSG film, is deposited on the resultant and then flowed. Subsequently, the BPSG film 30 is subjected to chemical mechanical polishing until the surface of the second plug poly 27 is exposed. The storage node electrode 31 is then formed to contact the exposed second plug poly 27.

Here, the first and second plug polys 25A, 25B and 27, the bit line 28A and the storage electrode 31 are formed of polysilicon having conductivity.

In this way, since a separate storage node contact hole does not have to be formed, a short between the bit line 28A and the storage electrode 31 can be prevented.

As described in detail above, according to the present invention, a plug for electrically connecting the storage electrode and the first plug poly is formed in advance before forming the bit line and the interlayer planarization film (or the interlayer insulation film). Accordingly, the distance between the plug and the bit line for electrically connecting the storage electrode and the first plug pulley can be easily adjusted to prevent short circuit with the bit line.

Furthermore, since the storage node contact hole having a relatively deep depth is not formed and the trouble of filling it up is eliminated, the contact characteristic can be improved.

Claims (9)

Providing a gate electrode having a spacer and a hard mask layer, and a semiconductor substrate having source and drain regions formed on both sides of the gate electrode; Forming a first plug poly in contact with a source and a drain region in spaces on both sides of the spacer of the gate electrode; Forming a first plug pulley contacting the source region and a second plug pulley having a predetermined height thereon; Forming a bit line over the first plug poly in contact with the drain region; Forming an interlayer planarization layer on the semiconductor substrate to have the same height as the second plug poly; And And forming a storage electrode on the interlayer planarization layer so as to contact the second plug poly. The method of claim 1, wherein the forming of the first plug poly comprises: forming a polysilicon layer on the semiconductor substrate to be sufficiently embedded in the result; And chemically mechanically polishing the polysilicon film to expose the hard mask film of the gate electrode. The method of forming a contact of a semiconductor device according to claim 2, wherein the thickness of the polysilicon film for the first plug poly is about 5000 to 10000 Pa. The method of claim 1, wherein the second plug pulley has a height of about 2000 to 10000 GPa. The method of claim 1, wherein the forming of the bit line comprises: forming a polysilicon film having a thickness smaller than that of the second plug poly; And partially patterning the polysilicon layer to be in contact with the first plug poly in contact with the drain region. The method of claim 5, wherein when the polysilicon layer is etched to form the bit line, patterning is performed until the surface of the second plug poly is exposed. 7. The method of forming a contact of a semiconductor device according to claim 5 or 6, wherein the bit line polysilicon film has a thickness of about 500 to 2000 mW. The method of claim 1, wherein the forming of the interlayer planarization layer to have the same height as the second plug poly comprises: forming an interlayer planarization layer on the resultant; And chemically polishing the interlayer planarization film until the surface of the second plug poly is exposed. 9. The method of claim 8, wherein the interlayer planarization film is a BPSG film.