KR20040008420A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20040008420A KR20040008420A KR1020020042057A KR20020042057A KR20040008420A KR 20040008420 A KR20040008420 A KR 20040008420A KR 1020020042057 A KR1020020042057 A KR 1020020042057A KR 20020042057 A KR20020042057 A KR 20020042057A KR 20040008420 A KR20040008420 A KR 20040008420A
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- film
- thin film
- hard mask
- pattern
- photoresist pattern
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 64
- 239000010409 thin film Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 29
- 238000003860 storage Methods 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 44
- 239000007789 gas Substances 0.000 claims description 18
- 238000009413 insulation Methods 0.000 claims description 10
- 238000000206 photolithography Methods 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 235000014653 Carica parviflora Nutrition 0.000 claims description 3
- 241000243321 Cnidaria Species 0.000 claims description 3
- 239000000654 additive Substances 0.000 claims description 3
- 230000000996 additive effect Effects 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게 높은 종횡비를 갖는 저장전극의 형성공정 시 사진식각공정에 대한 공정 마진을 확보하여 공정의 안정성을 확보하는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device to secure process stability by securing a process margin for a photolithography process during the formation of a storage electrode having a high aspect ratio.
반도체소자가 고집적화됨에 따라 소자의 동작에 필요한 최소한의 캐패시터의정전용량은 줄어드는데 한계가 있다. 이에 작은 면적에 최소한의 정전용량(C)을 확보하기 위하여 많은 노력을 기울이고 있다. 정전용량은 유전율(ε)과 저장전극 표면적(A)에 비례하고 유전막 두께(d)에 반비례하므로 정전용량을 증가시키는 방법으로는 여러가지가 있을 수 있지만, 그 중에서 유전율이 큰 고유전체인 BST((Ba1-xSrx)TiO3), PZT(Pb(ZrTi1-x)O3), Ta2O5등을 이용하여 캐패시터의 정전용량을 증가시키는 방법이 현재 많이 연구되고 있다.As semiconductor devices are highly integrated, there is a limit in that the capacitance of the minimum capacitor required for the operation of the device is reduced. In order to secure a small amount of capacitance (C) in a small area is making a lot of effort. Since the capacitance is proportional to the dielectric constant (ε) and the storage electrode surface area (A) and inversely proportional to the dielectric film thickness (d), there are various ways to increase the capacitance, but BST (( Ba 1-x Sr x ) TiO 3 ), PZT (Pb (ZrTi 1-x ) O 3 ), Ta 2 O 5 and the like to increase the capacitance of the capacitor is currently being studied a lot.
또한, 종래에는 전극 물질로서 다결정실리콘이 주로 사용되었으나, 상기 고유전체를 이용하여 캐패시터를 형성하는 경우 루테늄(Ru), 이리듐(Ir), 플라티늄(Pt) 등의 귀금속이 전극 물질로 사용되고 있다. 그러나, 상기 루테늄은 막질이 치밀하지 못하여 여러 가지 공정에 사용되는 케미칼(chemical) 및 플라즈마(plasma) 등을 통과시켜 하부 박막을 손상시키는 문제점이 있다.In addition, conventionally, polycrystalline silicon is mainly used as an electrode material, but when forming a capacitor using the high dielectric material, precious metals such as ruthenium (Ru), iridium (Ir), and platinum (Pt) are used as the electrode material. However, the ruthenium has a problem in that the film quality is not dense and the lower thin film is damaged by passing through chemical and plasma used in various processes.
이하, 종래기술에 따른 반도체소자의 제조방법에 대하여 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described.
먼저,소정의 하부구조물이 구비되는 반도체기판 상부에 저장전극 콘택플러그가 구비되는 층간절연막을 형성한다.First, an interlayer insulating film having a storage electrode contact plug is formed on a semiconductor substrate having a predetermined lower structure.
다음, 전체표면 상부에 식각방지막을 소정 두께 형성한다. 이때, 상기 식각방지막은 질화막으로 형성된 것이다.Next, an anti-etching film is formed on the entire surface to a predetermined thickness. In this case, the etch stop film is formed of a nitride film.
그 다음, 상기 식각방지막 상부에 코아절연막을 형성한다. 이때, 상기 코아절연막은 산화막으로 형성되며, 형성하고자 하는 저장전극의 높이만큼 형성한다.Next, a core insulating layer is formed on the etch stop layer. In this case, the core insulation layer is formed of an oxide layer and is formed by the height of the storage electrode to be formed.
다음, 상기 코아절연막 상부에 하드마스크용 박막을 소정 두께 형성한다. 이때, 상기 하드마스크용 박막은 다결정실리콘층으로 형성된 것이다.Next, a thin film for a hard mask is formed on the core insulation layer. In this case, the hard mask thin film is formed of a polycrystalline silicon layer.
그 다음, 상기 하드마스크용 박막 상부에 저장전극으로 예정되는 부분을 노출시키는 감광막패턴을 형성한다.Next, a photoresist pattern is formed on the hard mask thin film to expose a predetermined portion as a storage electrode.
다음, 상기 감광막패턴을 식각마스크로 상기 하드마스크용 박막을 식각하여 하드마스크용 박막 패턴을 형성한다.Next, the hard mask thin film is etched using the photoresist pattern as an etch mask to form a hard mask thin film pattern.
그 다음, 상기 감광막패턴 및 하드마스크용 박막패턴을 식각마스크로 상기 코아절연막 및 식각방지막을 식각하여 상기 저장전극 콘택플러그를 노출시키는 트렌치를 형성한다.Next, the core insulation layer and the etch stop layer are etched using the photoresist pattern and the thin film pattern for hard mask to form a trench to expose the storage electrode contact plug.
다음, 상기 하드마스크용 박막패턴을 제거한 후 세정공정을 실시한다.Next, the hard mask thin film pattern is removed and a cleaning process is performed.
그 후, 도시되어 있지는 않지만 저장전극, 유전체막 및 플레이트전극을 형성하여 캐패시터를 완성한다.Thereafter, although not shown, a storage electrode, a dielectric film, and a plate electrode are formed to complete the capacitor.
상기한 바와 같이 종래기술에 따른 반도체소자의 제조방법은, 반도체소자가 고집적화되어 감에 따라 저장전극의 표면적을 증가시키기 위하여 3차원 구조의 저장전극을 형성하는 등의 방법을 사용하였으나, 코아절연막의 식각 시 식각마스크로서 감광막패턴을 사용하는 공정에 비해 하드마스크용 박막의 증착, 하드마스크용 박막의 패터닝, 하드마스크용 박막의 제거 및 세정 공정 등 복잡한 공정이 요구되므로 제조 원가의 상승 및 공정 증가에 따른 수율이 감소하는 문제점이 있다.As described above, the semiconductor device manufacturing method according to the related art uses a method such as forming a storage electrode having a three-dimensional structure in order to increase the surface area of the storage electrode as the semiconductor device is highly integrated. Compared to the process of using the photoresist pattern as an etching mask during etching, complicated processes such as deposition of hard mask thin film, patterning of hard mask thin film, removal and cleaning of hard mask thin film are required. There is a problem that the yield is reduced.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 높은 종횡비를 갖는 저장전극의 형성공정 시 하부감광막/하드마스크용 박막/상부감광막 3중 구조를패터닝하여 이를 식각마스크로 사용함으로써 사진식각공정에 대한 공정 마진을 확보하여 공정의 안정성을 확보하고, 공정을 단순하게 하는 동시에 수율을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, in the photolithography process by patterning the triple structure of the lower photoresist film / hard mask thin film / upper photoresist film during the formation of the storage electrode having a high aspect ratio and using it as an etching mask It is an object of the present invention to provide a method for manufacturing a semiconductor device that secures process stability by securing a process margin, and simplifies the process and improves yield.
도 1 내지 도 5 는 본 발명에 따른 반도체소자의 제조방법을 도시한 공정 단면도.1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 제1층간절연막 13 : 비트라인11: first interlayer insulating film 13: bit line
15 : 제2층간절연막 17 : 저장전극 콘택플러그15: second interlayer insulating film 17: storage electrode contact plug
19 : 코아절연막 21 : 하부감광막19 core insulation film 21 lower photosensitive film
22 : 하부감광막패턴 23 : 하드마스크용 박막22: lower photoresist pattern 23: thin film for the hard mask
24 : 하드마스크용 박막 패턴 25 : 상부감광막24: thin film pattern for the hard mask 25: upper photosensitive film
26 : 상부감광막패턴 27 : 트렌치26 upper photoresist pattern 27 trench
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
반도체기판 상부에 저장전극 콘택플러그가 구비되는 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a storage electrode contact plug on the semiconductor substrate;
상기 층간절연막 상부에 코아절연막을 형성하는 공정과,Forming a core insulating film on the interlayer insulating film;
상기 코아절연막 상부에 하부감광막을 도포하는 공정과,Applying a lower photoresist film on the core insulation film;
상기 하부감광막 상부에 소정 두께의 하드마스크용 박막을 형성하는 공정과,Forming a thin film for a hard mask having a predetermined thickness on the lower photoresist;
상기 하드마스크용 박막 상부에 상부감광막을 도포하는 공정과,Coating an upper photoresist film on the thin film for hard mask;
저장전극 마스크를 이용한 사진공정으로 상기 상부감광막을 노광 및 현상하여 상부감광막패턴을 형성하는 공정과,Forming a top photoresist pattern by exposing and developing the top photoresist in a photolithography process using a storage electrode mask;
상기 상부감광막패턴을 식각마스크로 상기 하드마스크용 박막 및 하부감광막을 식각하여 하드마스크용 박막 및 하부감광막패턴을 형성하는 공정과,Etching the hard mask thin film and the lower photosensitive film by using the upper photoresist pattern as an etch mask to form a hard mask thin film and a lower photoresist pattern;
상기 상부감광막패턴, 하드마스크용 박막패턴 및 하부감광막패턴을 식각마스크로 상기 코아절연막을 식각하되, 상기 식각공정 후 상기 상부감광막패턴, 하드마스크용 박막 패턴 및 소정 두께의 하부감광막패턴이 제거되는 공정과,The core insulation layer is etched using the upper photoresist pattern, the hard mask thin film pattern, and the lower photoresist pattern as an etch mask, and after the etching process, the upper photoresist pattern, the hard mask thin film pattern, and the lower photoresist pattern having a predetermined thickness are removed. and,
상기 하드마스크용 박막은 다결정실리콘층, 산화막, 질화막 또는 저유전물질로 형성되는 것과,The hard mask thin film is formed of a polysilicon layer, an oxide film, a nitride film or a low dielectric material,
상기 저유전물질은 SiLK, Flare, BCB 또는 CORAL인 것과,The low dielectric material is SiLK, Flare, BCB or CORAL,
상기 하부감광막은 수소가스를 주식각가스로 이용하여 식각되는 것과,The lower photoresist is etched using hydrogen gas as a stock angle gas,
상기 하부감광막은 상기 주식각가스에 기화 H2O 플라즈마, CH3F, CH4, NH3또는 불활성가스를 첨가가스로 혼합한 혼합가스를 식각가스로 이용하여 식각되는 것과,The lower photoresist film is etched using the mixed gas of the gas mixture H 2 O plasma, CH 3 F, CH 4 , NH 3 or inert gas as an additive gas to the stock angle gas as an etching gas,
상기 하부감광막은 상기 하드마스크용 박막 패턴에 대하여 20 : 1 ∼ 50 : 1의 식각선택비를 갖는 것과,The lower photoresist layer has an etching selectivity of 20: 1 to 50: 1 with respect to the hard mask thin film pattern,
상기 하부감광막은 온도가 -100 ∼ 0℃, 압력이 30 ∼ 100mtorr, 바이어스 파워가 0 ∼ 30V인 공정 범위에서 디커플드 소오스(decoupled source)를 이용하는 조건에서 식각되는 것을 특징으로 한다.The lower photoresist layer is etched under the conditions of using a decoupled source in a process range in which the temperature is -100 to 0 ° C, the pressure is 30 to 100 mtorr, and the bias power is 0 to 30V.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1 내지 도 5 는 본 발명에 따른 반도체소자의 제조방법을 도시한 공정 단면도이다.1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저,소정의 하부구조물이 구비되는 반도체기판(도시안됨) 상부에 제1층간절연막(11)을 형성한다.First, a first interlayer insulating film 11 is formed on a semiconductor substrate (not shown) provided with a predetermined lower structure.
다음, 비트라인 콘택마스크를 이용한 사진식각공정으로 상기 제1층간절연막(11)을 식각하여 비트라인 콘택홀(도시안됨)을 형성한 후 상기 비트라인 콘택홀을 통하여 상기반도체기판에 접속되는 비트라인(13)을 형성한다.Next, the first interlayer insulating layer 11 is etched to form a bit line contact hole (not shown) by a photolithography process using a bit line contact mask, and then a bit line connected to the semiconductor substrate through the bit line contact hole. (13) is formed.
그 다음, 전체표면 상부에 제2층간절연막(15)을 형성한다.Next, a second interlayer insulating film 15 is formed over the entire surface.
다음, 저장전극 콘택 마스크를 이용한 사진식각공정으로 상기 제2층간절연막(15) 및 제1층간절연막(11)을 식각하여 저장전극 콘택홀(도시안됨)을 형성한다.Next, the second interlayer insulating layer 15 and the first interlayer insulating layer 11 are etched by a photolithography process using a storage electrode contact mask to form a storage electrode contact hole (not shown).
그 다음, 상기 저장전극 콘택홀을 포함한 전체표면 상부에 도전층(도시안됨)을 형성한 후 평탄화식각하여 저장전극 콘택플러그(17)를 형성한다.Next, a conductive layer (not shown) is formed on the entire surface including the storage electrode contact hole and then planarized to form the storage electrode contact plug 17.
다음, 전체표면 상부에 코아절연막(19)을 형성한다.Next, a core insulating film 19 is formed over the entire surface.
그 다음, 상기 코아절연막(19) 상부에 하부감광막(21)을 도포한다.Next, a lower photoresist layer 21 is coated on the core insulation layer 19.
다음, 상기 하부감광막(21) 상부에 하드마스크용 박막(23)을 소정 두께 형성한다. 이때, 상기 하드마스크용 박막(23)은 다결정실리콘, 산화막 또는 질화막으로 형성되며, 200 ∼ 400℃에서 형성함으로써 상기 하부감광막(21)의 손상을 방지한다. 또한, 상기 하드마스크용 박막(23)은 SiLK, Flare, BCB 또는 CORAL 등의 저유전물질로 형성할 수도 있다.Next, a thin film 23 for a hard mask is formed on the lower photoresist 21. In this case, the hard mask thin film 23 is formed of polycrystalline silicon, an oxide film or a nitride film, and formed at 200 to 400 ° C. to prevent damage to the lower photosensitive film 21. In addition, the hard mask thin film 23 may be formed of a low dielectric material such as SiLK, Flare, BCB, or CORAL.
그 다음, 상기 하드마스크용 박막(23) 상부에 상부감광막(25)을 소정 두께 도포한다. 이때, 상기 상부감광막(25)은 상기 하드마스크용 박막(23)을 패터닝하는 동안 식각마스크로 사용될 수 있을 정도의 두께로 형성된다.Next, an upper photosensitive film 25 is coated on the hard mask thin film 23 at a predetermined thickness. In this case, the upper photoresist layer 25 is formed to a thickness sufficient to be used as an etching mask while patterning the thin film 23 for hard mask.
다음, 저장전극 마스크를 이용한 사진공정으로 상기 상부감광막(25)을 노광 및 현상하여 상부감광막패턴(26)을 형성한다. (도 2 참조)Next, the upper photoresist layer 25 is exposed and developed by a photolithography process using a storage electrode mask to form an upper photoresist layer pattern 26. (See Figure 2)
그 다음, 상기 상부감광막(26)을 식각마스크로 상기 하드마스크용 박막 패턴(23)을 식각하여 하드마스크용 박막 패턴(24)을 형성한다.Next, the thin film pattern 23 for hard mask is etched using the upper photoresist layer 26 as an etch mask to form a hard mask thin film pattern 24.
다음, 상기 상부감광막패턴(26) 및 하드마스크용 박막패턴(24)을 식각마스크로 상기 하부감광막(21)을 식각하여 하부감광막패턴(22)을 형성한다.Next, the lower photoresist layer pattern 22 and the hard mask thin film pattern 24 are etched using the etching mask to form the lower photoresist layer pattern 22.
이때, 상기 하부감광막(21)은 수소가스를 주식각가스로 사용하고, 기화 H2O 플라즈마, CH3F, CH4또는 NH3를 첨가가스로 사용하는 혼합가스를 식각가스로 사용하여 식각된다. 여기서, 상기 식각공정은 20 : 1 ∼ 50 : 1의 식각선택비를 유지하며 실시되고, 상기 기화 H2O 플라즈마, CH3F, CH4또는 NH3는 주식각가스에 함유된 수소에 의해 폴리머를 유발시켜 하부감광막(21)의 측면이 식각되는 것을 방지하며 이를 위하여 상기 식각공정은 -100 ∼ 0℃의 저온에서 실시된다.In this case, the lower photosensitive film 21 is etched using hydrogen gas as a stock angle gas and a mixed gas using vaporized H 2 O plasma, CH 3 F, CH 4 or NH 3 as an additive gas as an etching gas. . Here, the etching process is carried out while maintaining an etching selectivity of 20: 1 to 50: 1, wherein the vaporized H 2 O plasma, CH 3 F, CH 4 or NH 3 is a polymer by hydrogen contained in the stock corner gas To prevent side surfaces of the lower photoresist film 21 from being etched, and the etching process is performed at a low temperature of -100 to 0 ° C.
또한, 상기 주식각가스에 Ar, He, Ne 또는 Xe 등의 불활성가스를 첨가가스를 혼합한 혼합가스를 식각가스로 사용함으로써 플라즈마를 안정화시킬 수 있다.In addition, the plasma can be stabilized by using a mixed gas in which an inert gas such as Ar, He, Ne, or Xe is added to the staple gas as an etching gas.
그리고, 상기 식각공정은 상기 하부감광막패턴(22)에 대한 식각선택비를 향상시키기 위하여 압력이 30 ∼ 100mtorr이고, 바이어스 파워가 0 ∼ 30V인 공정 범위에서 디커플드 소오스(decoupled source)를 이용하여 실시한다.In the etching process, a decoupled source is used in a process range in which the pressure is 30 to 100 mtorr and the bias power is 0 to 30 V to improve the etching selectivity with respect to the lower photoresist pattern 22. Conduct.
한편, 상기 하드마스크용 박막(23)을 다결정실리콘층으로 사용하는 경우 0 ∼ 20mtorr의 압력에서 0 ∼ 50V의 바이어스 파워를 사용하여 CD 바이어스를 최소화한다. (도 3 참조)On the other hand, when the hard mask thin film 23 is used as a polysilicon layer, CD bias is minimized by using a bias power of 0 to 50 V at a pressure of 0 to 20 mtorr. (See Figure 3)
그 다음, 상기 상부감광막패턴(26), 하드마스크용 박막패턴(24) 및 하부감광막패턴(22)을 식각마스크로 이용하여 상기 코아절연막(19)을 식각하여 상기 저장전극 콘택 플러그(17)를 노출시키는 트렌치(27)를 형성한다. 이때, 상기 식각공정 시 상기 상부감광막패턴(26), 하드마스크용 박막 패턴(24) 및 소정 두께의 하부감광막패턴(22)이 제거된다. (도 4 참조)Next, the core insulation layer 19 is etched using the upper photoresist pattern 26, the hard mask thin film pattern 24, and the lower photoresist pattern 22 as an etch mask to form the storage electrode contact plug 17. The trench 27 to be exposed is formed. At this time, the upper photoresist pattern 26, the hard mask thin film pattern 24, and the lower photoresist pattern 22 having a predetermined thickness are removed during the etching process. (See Figure 4)
그 후, 상기 식각공정 후 잔류하는 하부감광막패턴(22)을 제거한다. (도 5 참조)Thereafter, the lower photoresist pattern 22 remaining after the etching process is removed. (See Figure 5)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 높은 종횡비를 갖는 오목형 저장전극을 형성하기 위하여 저장전극 마스크로 사용되는 감광막패턴을 하부감광막/하드마스크층/상부감광막의 3중구조로 형성하여 사진공정 시 공정 마진을 확보하여 패턴을 프로파일을 균일하게 형성하고, 그에 따른 반도체소자의 고집적화를 유리하게 하는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, a photoresist pattern used as a storage electrode mask to form a concave storage electrode having a high aspect ratio has a triple structure of a lower photoresist / hard mask layer / upper photoresist. Forming to secure the process margin during the photo process to form a pattern uniformly, there is an advantage that the high integration of the semiconductor device thereby advantageous.
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