KR20040006321A - Method for forming isolation layer of semiconductor device - Google Patents
Method for forming isolation layer of semiconductor device Download PDFInfo
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- KR20040006321A KR20040006321A KR1020020040346A KR20020040346A KR20040006321A KR 20040006321 A KR20040006321 A KR 20040006321A KR 1020020040346 A KR1020020040346 A KR 1020020040346A KR 20020040346 A KR20020040346 A KR 20020040346A KR 20040006321 A KR20040006321 A KR 20040006321A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
Abstract
Description
본 발명은 STI(Shallow Trench Isolation) 공정을 이용한 반도체 소자의 소자분리막 형성방법에 관한 것으로, 보다 상세하게는, 스트레스(stress)에 기인된 서브-디펙트(sub-defect)의 발생을 방지할 수 있는 반도체 소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method for forming an isolation layer of a semiconductor device using a shallow trench isolation (STI) process, and more particularly, to prevent the occurrence of sub-defects caused by stress. The present invention relates to a method for forming a device isolation film of a semiconductor device.
주지된 바와 같이, 최근의 반도체 소자는 소자들간의 전기적 분리를 위한 소자분리막의 형성을 위해 STI(Shallow Trench Isolation) 공정을 이용하고 있다. 이것은 기존의 로코스(LOCOS) 공정에 의한 소자분리막이 그 가장자리 부분에 새부리 형상의 버즈-빅(bird's-beak)을 갖는 것과 관련해서 소자 형성 면적을 줄이는 단점이 있는 반면, 상기 STI 공정에 의한 소자분리막은 작은 폭으로의 형성이 가능하기 때문이다.As is well known, recent semiconductor devices use a shallow trench isolation (STI) process for forming an isolation layer for electrical isolation between devices. This has the disadvantage of reducing the device formation area in connection with the conventional LOCOS device isolation film having a bird's-beak of the beak shape at the edge thereof, while the device by the STI process This is because the separator can be formed in a small width.
이하, 종래의 STI 공정을 이용한 소자분리막 형성방법을 간략하게 설명하도록 한다.Hereinafter, a device isolation film forming method using a conventional STI process will be briefly described.
먼저, 실리콘 기판 상에 패드산화막과 패드질화막을 차례로 형성한 다음, 공지의 포토리소그라피 공정에 따라 상기 막들을 패터닝하여 소자분리 영역에 해당하는 기판 부분을 노출시키고, 이어서, 노출된 기판 부분을 식각하여 트렌치를 형성한다.First, a pad oxide film and a pad nitride film are sequentially formed on a silicon substrate. Then, the films are patterned according to a known photolithography process to expose a substrate portion corresponding to an isolation region, and then the exposed substrate portion is etched. Form a trench.
그 다음, 식각 데미지를 회복시키기 위해 희생 산화 공정을 수행한 후, 이 과정에서 트렌치 표면에 형성된 희생산화막을 습식 식각으로 제거하고, 이어서, 열산화 공정을 통해 월 산화막(wall oxide)을 형성한다.Then, after the sacrificial oxidation process is performed to recover the etch damage, the sacrificial oxide film formed on the trench surface is removed by wet etching in this process, and then a wall oxide is formed through the thermal oxidation process.
다음으로, 상기 트렌치를 매립하도록 기판 상에 HDP(High Density Plasma) 산화막을 증착하고, 이어서, 상기 HDP 산화막의 표면을 CMP(Chemical Mechanical Polishing)한다.Next, an HDP (High Density Plasma) oxide film is deposited on the substrate to fill the trench, and then the surface of the HDP oxide film is subjected to CMP (Chemical Mechanical Polishing).
이후, 상기 패드질화막과 패드산화막을 제거하여 트렌치형 소자분리막의 형성을 완성한다.Thereafter, the pad nitride layer and the pad oxide layer are removed to complete the formation of the trench type isolation layer.
그러나, 종래의 STI 공정을 이용한 소자분리막 형성방법에 따르면, 트렌치의 형성후에 액티브 영역의 가장자리는 샤프(sharp)한 형상을 갖게 되는데, 이러한 구조에서는 트렌치 식각시에 발생된 식각 스트레스(etch stress), 후속 공정중 산화 공정시의 부피 팽창(volume expansion)에 의한 열적 스트레스(thermal stress), 트렌치 매립을 위한 HDP 산화막 증착시의 기계적 스트레스(mechanical stress) 등이 트렌치 하단 코너부에 집중됨으로써, 이 부위에서 전위(dislocation)와 같은 서브-디펙트(sub-defect)가 발생하게 되며, 결국, 이러한 서브-디펙트로 인해 누설 전류 특성과 같은 소자 특성 저하는 물론 수율 저하가 야기된다.However, according to the conventional method of forming an isolation layer using an STI process, an edge of an active region has a sharp shape after formation of a trench. In such a structure, an etch stress generated during trench etching, In this process, thermal stress due to volume expansion during the oxidation process and mechanical stress during deposition of the HDP oxide for trench filling are concentrated in the lower corner of the trench. Sub-defects such as dislocations occur, which in turn results in lowered device characteristics such as leakage current characteristics and lowered yields.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 스트레스에 기인된 서브-디펙트의 발생을 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of preventing the occurrence of sub-defects caused by stress.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 소자분리막 형성방법을 설명하기 위한 공정 단면도.1A to 1D are cross-sectional views illustrating a method of forming an isolation layer in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 실리콘 기판 12 : 패드산화막11 silicon substrate 12 pad oxide film
13 : 패드질화막 14 : 트렌치13 pad nitride film 14 trench
15 : 산화막 16 : 선형질화막15 oxide film 16: linear nitride film
17 : 버퍼막 18 : HDP 산화막17: buffer film 18: HDP oxide film
20 : 소자분리막20: device isolation film
상기와 같은 목적을 달성하기 위하여, 본 발명은, 실리콘 기판 상에 패드산화막과 패드질화막을 차례로 형성하는 단계; 상기 패드질화막과 패드산화막을 패터닝하여 소자분리 영역에 해당하는 기판 부분을 노출시키는 단계; 상기 노출된 기판 부분을 식각하여 트렌치를 형성하는 단계; 상기 기판 결과물을 열처리하여 트렌치의 상단 및 하단 코너부를 라운딩 처리해 주는 단계; 상기 트렌치 표면 및 패드질화막 상에 박막의 선형질화막을 증착하는 단계; 상기 선형질화막 상에 상기 선형질화막과 트렌치 매립용 산화막간의 계면 특성을 향상시키기 위해 버퍼막을 증착하는단계; 상기 트렌치를 완전 매립하도록 기판 상에 HDP 산화막을 증착하는 단계; 상기 패드질화막이 노출될 때까지 HDP 산화막의 표면을 CMP하는 단계; 및 상기 패드질화막과 패드산화막을 제거하는 단계를 포함하는 반도체 소자의 소자분리막 형성방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of sequentially forming a pad oxide film and a pad nitride film on a silicon substrate; Patterning the pad nitride layer and the pad oxide layer to expose a substrate portion corresponding to an isolation region; Etching the exposed substrate portion to form a trench; Heat-treating the substrate resultant to round the top and bottom corners of the trench; Depositing a thin linear nitride film on the trench surface and the pad nitride film; Depositing a buffer film on the linear nitride film to improve an interface property between the linear nitride film and the trench filling oxide film; Depositing an HDP oxide film on a substrate to completely fill the trench; CMPing the surface of the HDP oxide film until the pad nitride film is exposed; And removing the pad nitride film and the pad oxide film.
여기서, 상기 선형질화막은 40∼100Å의 두께로 증착한다.Here, the linear nitride film is deposited to a thickness of 40 to 100 GPa.
또한, 상기 버퍼막은 TEOS 산화막 또는 실리콘막으로 형성하며, 상기 버퍼막으로서 실리콘막을 형성한 경우, 패드질화막의 제거 후에 1000∼1100℃ 및 O2분위기의 퍼니스(furnace) 내에서 90∼110Å의 산화막이 형성되도록 하는 조건으로 고온 건식 산화 공정을 추가로 수행한다.The buffer film is formed of a TEOS oxide film or a silicon film, and in the case where the silicon film is formed as the buffer film, after the pad nitride film is removed, an oxide film of 90 to 110 Pa is formed in a furnace at 1000 to 1100 ° C. and an O 2 atmosphere. A high temperature dry oxidation process is further carried out under conditions that allow it to form.
본 발명에 따르면, 트렌치 형성 후에 기판 산화를 방지할 수 있는 박막의 선형질화막 및 상기 선형질화막과 HDP 산화막간의 계면 특성 향상을 위한 버퍼막을 형성해 줌으로써 스트레스로 인한 서브-디펙트의 발생을 방지할 수 있다.According to the present invention, it is possible to prevent the occurrence of sub-defects due to stress by forming a linear nitride film of a thin film capable of preventing substrate oxidation after trench formation and a buffer film for improving interface characteristics between the linear nitride film and the HDP oxide film. .
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.1A to 1E are cross-sectional views of processes for describing a method of forming a device isolation film of a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 실리콘 기판(11) 상에 패드산화막(12)과 패드질화막(13)을 차례로 형성하고, 공지의 포토리소그라피 공정에 따라 상기 패드질화막(13)과 패드산화막(12)을 패터닝하여 소자분리 영역에 해당하는 기판 부분을 노출시킨다그런다음, 노출된 기판 부분을 식각하여 트렌치(14)를 형성한다.Referring to FIG. 1A, a pad oxide film 12 and a pad nitride film 13 are sequentially formed on a silicon substrate 11, and the pad nitride film 13 and the pad oxide film 12 are patterned according to a known photolithography process. The substrate portion corresponding to the device isolation region is exposed. Then, the exposed substrate portion is etched to form the trench 14.
이어서, 상기 트렌치 식각시의 식각 데미지를 회복시키기 위해 희생산화 공정을 수행하고, 이를 통해, 트렌치(14)의 라운딩(rounding) 처리가 이루어지도록 함과 동시에 상기 트렌치(14)의 표면에 산화막(15)을 형성한다.Subsequently, a sacrificial oxidation process is performed to recover the etch damage during the etching of the trench, through which the rounding treatment of the trench 14 is performed, and at the same time, the oxide film 15 is formed on the surface of the trench 14. ).
도 1b를 참조하면, 산화막(15)이 형성된 트렌치 표면을 포함한 상기 기판 결과물 상에 40∼100Å의 두께로 박막의 선형질화막(16)을 증착한다. 여기서, 상기 선형질화막(16)은 후속하는 열처리 공정에서 기판 산화에 의한 부피 팽창(volume expansion)으로 인해 기판 스트레스가 가중되는 것을 억제시키기 위해 형성해주는 일종의 기판 산화 방지용 베리어막이며, 이러한 선형질화막(16)의 증착으로 인해 후속 열처리 공정에서 발생되는 스트레스로 인한 서브-디펙트의 유발은 방지할 수 있게 된다.Referring to FIG. 1B, a linear nitride film 16 of thin film is deposited on the substrate resultant including the trench surface on which the oxide film 15 is formed to a thickness of 40 to 100 GPa. Here, the linear nitride film 16 is a kind of barrier film for preventing substrate oxidation, which is formed to suppress the weight of the substrate stress due to volume expansion due to substrate oxidation in a subsequent heat treatment process. The deposition of) can prevent the occurrence of sub-defect due to the stress generated in the subsequent heat treatment process.
계속해서, 선형질화막(16) 상에 TEOS 산화막(17)을 증착하고, 이어서, 기판 결과물을 고온 열처리하여 상기 TEOS 산화막(17)을 치밀화(densification)시킨다.Subsequently, a TEOS oxide film 17 is deposited on the linear nitride film 16, and then the substrate resultant is subjected to high temperature heat treatment to densify the TEOS oxide film 17.
여기서, 상기 TEOS 산화막(17)은 선형질화막(16)과 후속에서 트렌치 매립을 위해 증착되는 HDP 산화막간의 계면 특성을 좋게 하기 위한 버퍼막(buffer layer)이다. 즉, 상기 버퍼막의 형성없이 선형질화막(16) 상에 HDP 산화막을 증착할 경우, HDP 산화막 증착 장비의 플라즈마 스트라이킹(plasma striking)으로 인해 선형질화막과 HDP 산화막간의 계면 특성이 불량해질 수 밖에 없으며, 이에 따라, 상기 HDP 산화막의 벗겨짐(peeling) 현상이 발생된다. 따라서, 상기 TEOS 산화막(17)은 이와 같은 계면 특성의 불량으로 인한 HDP 산화막의 벗겨짐 현상이 일어나는 것을방지하기 위해 일종의 버퍼막으로서 상기 선형질화막(16) 상에 형성해준다.Here, the TEOS oxide layer 17 is a buffer layer for improving the interfacial properties between the linear nitride layer 16 and the HDP oxide layer subsequently deposited for trench filling. That is, when the HDP oxide film is deposited on the linear nitride film 16 without forming the buffer film, the interface between the linear nitride film and the HDP oxide film is deteriorated due to plasma striking of the HDP oxide film deposition equipment. Accordingly, peeling of the HDP oxide film occurs. Accordingly, the TEOS oxide layer 17 is formed on the linear nitride layer 16 as a buffer layer in order to prevent peeling of the HDP oxide layer due to such poor interface characteristics.
또한, 상기 선형질화막(16) 상에 버퍼막으로서 TEOS 산화막(17)을 증착하는 경우, 상기 TEOS 산화막(17)은 통상의 산화막에 비해 식각 속도가 빠르기 때문에 후속하는 패드질화막(13) 및 패드산화막(12)의 식각 공정에서 소자분리막 상단 가장자리에서 발생되는 에지 모트(edge moat)의 깊이를 더욱 깊게 할 수 있다. 따라서, 본 발명은 이러한 에지 모트의 증가를 방지하기 위해, 전술한 바와 같이, 상기 TEOS 산화막(17)의 증착 후에, 예컨데, 1000∼1100℃, 바람직하게 1050℃ 및 N2분위기에서 25∼35분, 바람직하게 30분 동안 고온 열처리를 행하여 TEOS 산화막(17)의 수축(shrinkage)을 통해 식각 속도가 감소되도록 하고, 이에 따라, 에지 모트가 감소되도록 한다.In addition, when the TEOS oxide film 17 is deposited as a buffer film on the linear nitride film 16, the TEOS oxide film 17 has a higher etching rate than the conventional oxide film, so that the subsequent pad nitride film 13 and pad oxide film are followed. In the etching process of (12), an edge moat generated at the upper edge of the device isolation layer may be further deepened. Therefore, in order to prevent such an increase in the edge mote, as described above, after deposition of the TEOS oxide film 17, for example, 25 to 35 minutes in 1000 to 1100 ° C, preferably 1050 ° C and N 2 atmosphere. Preferably, the high temperature heat treatment is performed for 30 minutes so that the etching rate is reduced through shrinkage of the TEOS oxide film 17, thereby reducing the edge mote.
도 1c를 참조하면, 트렌치가 완전 매립되도록 상기 기판 결과물 상에 HDP 산화막(18)을 증착한다. 그런다음, 패드질화막이 노출될 때까지 상기 HDP 산화막의 표면을 CMP한다.Referring to FIG. 1C, an HDP oxide film 18 is deposited on the substrate resultant to completely fill the trench. Then, the surface of the HDP oxide film is CMP until the pad nitride film is exposed.
도 1d를 참조하면, 인산 용액을 이용한 습식 식각 공정을 통해 패드질화막을 식각 제거하고, 이어, HF 용액을 이용한 습식 세정을 통해 패드산화막을 제거함으로써, 본 발명에 따른 소자분리막(20)의 형성을 완성한다.Referring to FIG. 1D, the pad nitride film is etched away through a wet etching process using a phosphoric acid solution, and then the pad oxide film is removed by wet cleaning using an HF solution, thereby forming the device isolation film 20 according to the present invention. Complete
상기와 같은 본 발명의 방법은 트렌치 형성 후에 박막의 선형질화막을 형성해 줌으로써, 이러한 선형질화막에 의해 후속하는 열처리 공정에서 기판 산화가 일어나는 것을 방지할 수 있으며, 아울러, HDP 산화막 증착시의 기계적 스트레스가 기판에 인가되는 것을 방지할 수 있다. 따라서, 본 발명의 방법은 스트레스에 의한서브-디펙트의 발생을 용이하게 방지할 수 있다.The method of the present invention as described above, by forming a linear nitride film of the thin film after the trench formation, it is possible to prevent the substrate oxidation occurs in the subsequent heat treatment process by this linear nitride film, and mechanical stress during the deposition of HDP oxide film Can be prevented. Thus, the method of the present invention can easily prevent the occurrence of sub-defects due to stress.
한편, 기판 식각시에 식각 장벽으로 이용된 패드질화막을 제거함에 있어서, 패드질화막의 식각은 제거될 질화막 두께의 2배 내지 3배의 두께를 제거할 수 있는 시간 동안 진행하는 것이 일반적이다.On the other hand, in removing the pad nitride film used as an etching barrier during substrate etching, the etching of the pad nitride film is generally performed for a time that can remove the thickness of 2 to 3 times the thickness of the nitride film to be removed.
그런데, 이러한 조건으로 패드질화막을 식각할 경우, 이 과정에서 선형질화막의 식각이 일어날 수 있으며, 이에 따라, 깊은 에지 모트(edge moat)가 발생하여 소자 특성에 치명적인 문제를 유발할 수 있다.However, when the pad nitride layer is etched under such conditions, the linear nitride layer may be etched in this process, and thus, deep edge moats may occur, which may cause a fatal problem in device characteristics.
따라서, 상기 선형질화막의 적용에 따른 깊은 에지 모트의 발생에 기인하는 소자 특성 저하를 방지하기 위해, 본 발명은 다른 실시예로서 버퍼막으로서 TEOS 산화막 대신 폴리실리콘막 또는 비정질실리콘막과 같은 실리콘막을 증착하고, 패드질화막의 제거 후에 고온 건식 산화 공정을 추가로 수행하여 상기 패드질화막의 제거시에 발생된 에지 모트를 제거해 준다.Accordingly, in order to prevent device characteristics deterioration due to the generation of deep edge mott due to the application of the linear nitride film, the present invention provides, as another embodiment, a silicon film such as a polysilicon film or an amorphous silicon film instead of a TEOS oxide film as a buffer film. After the pad nitride film is removed, a high temperature dry oxidation process is further performed to remove the edge mott generated when the pad nitride film is removed.
즉, 본 발명의 다른 실시예에서는 버퍼막으로서 실리콘막을 증착한 후, 패드질화막의 식각 공정에서 선형질화막에 에지 모트가 발생된 경우에 고온 건식 산화 공정을 추가로 수행하고, 이 과정에서 상기 실리콘막이 산화막으로 변하는 것에 의해 에지 모트가 매립되도록 함으로써, 상기 패드질화막의 제거시에 발생된 에지 모트를 제거해 준다.That is, in another embodiment of the present invention, after depositing a silicon film as a buffer film, a high temperature dry oxidation process is additionally performed when an edge mott is generated in the linear nitride film during the etching process of the pad nitride film. By making the edge mort be buried by changing to an oxide film, the edge mott generated at the time of removing the pad nitride film is removed.
여기서, 상기 고온 건식 산화 공정은 1000∼1100℃ 및 O2분위기의 퍼니스 (furnace) 내에서 90∼110Å, 바람직하게 100Å의 산화막이 형성되도록 하는 조건으로 수행한다.Here, the high temperature dry oxidation process is performed under conditions such that an oxide film of 90 to 110 Pa, preferably 100 Pa is formed in a furnace of 1000 to 1100 ° C. and an O 2 atmosphere.
이 실시에에 따르면, 트렌치 식각 후에 선형질화막을 형성함에 따라 서브-디펙트의 발생을 방지할 수 있으며, 아울러, 선형질화막의 적용에 따른 에지 모트의 발생을 실리콘막의 산화를 통해 용이하게 제거해 줄 수 있다.According to this embodiment, by forming the linear nitride film after the trench etching, it is possible to prevent the occurrence of sub-defects, and also to easily remove the edge mott generated by the application of the linear nitride film through oxidation of the silicon film. have.
이상에서와 같이, 본 발명은 트렌치 식각 후에 후속 열처리시에 기판 산화를 방지할 수 있는 박막의 선형질화막 및 상기 선형질화막과 HDP 산화막간의 계면 특성 향상을 위한 버퍼막을 형성해 줌으로써, 후속 열처리 공정에서의 스트레스로 인해 서브-디펙트가 발생되는 것을 방지할 수 있으며, 이에 따라, 소자 특성을 향상시킬 수 있음은 물론 제조수율을 향상시킬 수 있다.As described above, the present invention forms a linear nitride film of a thin film capable of preventing substrate oxidation during the subsequent heat treatment after the trench etching, and a buffer film for improving the interfacial property between the linear nitride film and the HDP oxide film. Due to this, it is possible to prevent the occurrence of sub-defects, and thus, it is possible to improve device characteristics as well as to improve manufacturing yield.
또한, 본 발명의 버퍼막의 재질로서 실리콘막을 이용하고, 아울러, 고온 건식 산화 공정을 추가로 수행하여 패드질화막의 제거시에 발생되는 에지 모트를 제거해 줌으로써, 소자 특성 및 제조수율을 더욱 향상시킬 수 있다.In addition, by using a silicon film as a material of the buffer film of the present invention, and further performing a high temperature dry oxidation process to remove the edge mott generated when the pad nitride film is removed, it is possible to further improve the device characteristics and manufacturing yield. .
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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| KR19990073663A (en) * | 1998-03-02 | 1999-10-05 | 김규현 | Trench manufacturing method for semiconductor device isolation |
| KR20010016698A (en) * | 1999-08-02 | 2001-03-05 | 박종섭 | Method of forming shallow trench isolation layer in semiconductor device |
| KR20020005849A (en) * | 2000-07-10 | 2002-01-18 | 윤종용 | Trench isolation method |
| KR20020071063A (en) * | 2001-03-02 | 2002-09-12 | 삼성전자 주식회사 | Dent free trench isolation structure and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR19990073663A (en) * | 1998-03-02 | 1999-10-05 | 김규현 | Trench manufacturing method for semiconductor device isolation |
| KR20010016698A (en) * | 1999-08-02 | 2001-03-05 | 박종섭 | Method of forming shallow trench isolation layer in semiconductor device |
| KR20020005849A (en) * | 2000-07-10 | 2002-01-18 | 윤종용 | Trench isolation method |
| KR20020071063A (en) * | 2001-03-02 | 2002-09-12 | 삼성전자 주식회사 | Dent free trench isolation structure and method for fabricating the same |
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