KR20040006312A - Gate forming method of dual gate logic element - Google Patents
Gate forming method of dual gate logic element Download PDFInfo
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- KR20040006312A KR20040006312A KR1020020040337A KR20020040337A KR20040006312A KR 20040006312 A KR20040006312 A KR 20040006312A KR 1020020040337 A KR1020020040337 A KR 1020020040337A KR 20020040337 A KR20020040337 A KR 20020040337A KR 20040006312 A KR20040006312 A KR 20040006312A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
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- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Abstract
Description
본 발명은 상보형 MOS에서 게이트의 전기적 특성 안정화를 위한 게이트 형성방법에 관한 것으로, 특히 산화속도차이에 의해 발생한 N형 게이트 및 P형 게이트의 높이차이를 방지하기 위한 듀얼게이트 로직소자에서의 게이트 형성방법에 관한 것이다.The present invention relates to a gate forming method for stabilizing the electrical characteristics of a gate in a complementary MOS, in particular the gate formation in the dual gate logic device to prevent the height difference between the N-type gate and the P-type gate caused by the oxidation rate difference It is about a method.
현재의 반도체 제조기술은 고집적화를 요구한다. 따라서, MOSFET의 게이트 선폭 축소기술은 반도체소자의 고집적화에 매우 밀접하게 연관되어 있어서 게이트선폭을 축소시키는데 많은 노력을 기울이고 있다.Current semiconductor manufacturing technology requires high integration. Therefore, the gate line width reduction technology of MOSFETs is very closely related to the high integration of semiconductor devices, and much efforts have been made to reduce the gate line width.
이와 같은 게이트 선폭 축소기술에 부응키 위해, 게이트 식각전 이온주입등을 통해 게이트를 도핑시켜서 게이트의 저항을 줄이는 기술등 여러형태로 게이트를 도핑시킨 후 식각을 하고 있다.In order to respond to the gate line reduction technology, the gate is etched in various forms such as a technique of reducing the resistance of the gate by doping the gate through ion implantation before the gate etching.
특히 상보형 MOS를 이용한 반도체소자의 경우, 게이트가 N형 불순물과 P형불순물로 각각 도핑되어 있으므로 게이트 식각후 산화공정 (10 ~ 50Å)을 거치게 된다.In particular, in the case of a semiconductor device using a complementary MOS, since the gate is doped with N-type impurities and P-type impurities, the gate is etched after the gate etching (10 to 50 kV).
이때 N형 게이트(1)에서는 주입되어 있는 도펀트인 비소(As) 또는 인(P)에 의한 산화속도 증가현상이 발생하게 되어 공정온도에 따라 100 ~ 200Å 두께의 산화를 발생시키는 반면에, P형 게이트(2)에서는 일반적으로 도핑하지 않거나 붕소(B)에 의한 산화속도로 인해 60 ~ 90Å 두께의 산화만을 발생시킨다.At this time, in the N-type gate 1, the oxidation rate is increased by arsenic (As) or phosphorus (P), which is an implanted dopant, so that oxidation occurs at a thickness of 100 to 200 Å depending on the process temperature. In the gate 2, generally, only oxidization of 60 to 90 kHz thickness occurs due to the oxidization rate due to undoping or boron (B).
또한, 후속공정으로서 LDD(Lightly Doped Drain) 스페이서 형성 및 식각공정이 연속수행되는데, 이때 도 1에서와 같이 스페이서 식각시 N형 게이트(1) 및 P형 게이트(2)의 높이차이가 발생되며, 이는 반도체제조기술이 추구하는 게이트선폭이작아짐에 따른 P형 및 N형 게이트간 높이차이의 영향은, 0.15 ㎛, 0.13㎛등으로 축소될수록 커지게 되어 다음과 같은 문제점이 발생한다.In addition, as a subsequent process, a lightly doped drain (LDD) spacer is formed and etched continuously. In this case, as shown in FIG. 1, a height difference between the N-type gate 1 and the P-type gate 2 is generated when the spacer is etched. The influence of the height difference between the P-type and N-type gates is reduced as 0.15 μm, 0.13 μm, etc., as the gate line width pursued by semiconductor manufacturing technology becomes smaller, resulting in the following problems.
특히 스페이서 식각공정, 실리사이드 블로킹 식각공정, 및 실리사이드 형성공정등을 거치면서 게이트 높이가 300 ~ 500Å 정도 리세스되기 때문에, 최초 게이트의 높이가 2000Å 인 경우 최종 실리사이드 형성후의 게이트 높이는 1700 ~ 1500Å 으로 낮아지고, 특히 최초 게이트의 높이가 1500Å 인 경우에는 최종 실리사이드 형성후의 게이트 높이가 1200 ~ 1000Å 정도로 낮아지게 된다는 문제점이 있다.In particular, since the gate height is recessed about 300 ~ 500Å through the spacer etching process, silicide blocking etching process, and silicide forming process, the gate height after the final silicide formation is lowered to 1700 ~ 1500Å when the gate height is 2000Å. In particular, when the height of the first gate is 1500 kW, the gate height after the final silicide formation is lowered to about 1200 to 1000 kW.
즉, 게이트의 도핑원소(인, 붕소, 비소)에 따라 달라지는 산화속도차이로 인해, 스페이서 식각공정, 실리사이드 블로킹 식각공정등을 거치는 동안 N형 게이트(1)와 P형 게이트(2)의 높이차이가 대략 50 ~ 200Å 정도 발생하게 되는 문제점이 있다.That is, due to the difference in oxidation rate depending on the doping element (phosphorus, boron, arsenic) of the gate, the height difference between the N-type gate 1 and the P-type gate 2 during the spacer etching process, the silicide blocking etching process, etc. There is a problem that occurs about 50 ~ 200Å.
이러한 문제는 단순히 게이트 높이가 달라지는데만 있는 것이 아니라, 소스/드레인 이온주입시 동일시 하는 게이트 높이에 의해 "붕소", "인" 또는 "비소"의 투사범위(Rp)가 게이트 산화막(20)에서 볼때 그 분포높이가 달라지게 되고, 후속 열공정등을 거칠때 "붕소", "인" 또는 "비소"에 의해 게이트 산화막(20)의 열화 가능성이 높아진다는 문제점이 있다.This problem is not only caused by the gate height being different, but when the projection range Rp of "boron", "phosphorus" or "arsenic" is seen in the gate oxide film 20 by the gate height equated at the time of source / drain ion implantation. The distribution height is changed, and there is a problem that the possibility of deterioration of the gate oxide film 20 is increased by "boron", "phosphorus" or "arsenic" when going through a subsequent thermal process.
또한, 티타늄 또는 코발트를 이용하여 실리사이드를 형성할 때 N형 게이트(1)와 P형 게이트(2)의 실리사이드 형성 프로파일의 차이를 발생시키게 되며, 이는 또다시 게이트의 전기적 구동에 있어 예기치 않은 변화를 발생시키게 된다는 문제점이 있다.In addition, when silicide is formed using titanium or cobalt, a difference in silicide formation profile of the N-type gate 1 and the P-type gate 2 is generated, which again causes unexpected changes in the electrical driving of the gate. There is a problem that occurs.
특히, 0.13㎛ 또는 0.10㎛급의 게이트높이는 1300 ~ 2000Å 내외이어서 N형 게이트(1)와 P형 게이트(2)의 높이차이 즉, N형 게이트(1)의 높이(L1)와 P형 게이트(2)의 높이(L2) 차이의 영향은 더욱 커지게 된다는 문제점이 있다.In particular, the gate height of 0.13 μm or 0.10 μm class is about 1300 to 2000 μs, so that the height difference between the N-type gate 1 and the P-type gate 2, that is, the height L1 of the N-type gate 1 and the P-type gate ( There is a problem that the influence of the height (L2) difference of 2) becomes larger.
따라서, 본발명은 상기 종래기술의 제반문제점을 해결하기 위하여 안출한 것으로서, P형 게이트영역보다 빠른 산화속도를 갖는 N형 게이트영역의 추가형성을 위하여 P형 게이트영역에 추가형성 블로킹막을 패터닝한 후 N형 게이트영역의 실리콘막을 증착하여, 도핑농도에 따른 산화속도 증가 및 게이트 손실량을 보상하는 듀얼게이트 로직소자에서의 게이트 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above-mentioned problems of the prior art, and after patterning the additional formation blocking film in the P-type gate region for the additional formation of the N-type gate region having a faster oxidation rate than the P-type gate region It is an object of the present invention to provide a gate forming method in a dual gate logic device in which a silicon film in an N-type gate region is deposited to compensate for an increase in oxidation rate and gate loss according to a doping concentration.
상기 목적을 달성하기 위한 본 발명은, 반도체 기판상에 게이트산화막과 폴리실리콘막을 적층하는 단계; 상기 폴리실리콘막상에 추가형성 블로킹막을 형성하는 단계; 상기 추가형성 블로킹막의 상부에 추가형성 마스크를 형성하는 단계; 상기 추가형성 마스크를 이용하여 상기 추가형성 블로킹막을 패터닝하여 제 2 도전형의 게이트영역을 노출시킨후 상기 추가형성 마스크를 제거하는 단계; 상기 노출된 제 2 도전형의 게이트영역에 선택적 에피택셜 성장법(SEG), 화학기상증착법(CVD : Chemical Vapor Deposition) 또는 열증착법 중 어느 하나에 의해 보상실리콘막을 추가로 형성하는 단계; 및 추가로 패터닝공정을 진행하여 동일한 높이의 제 1 도전형의 게이트와 상기 제 2 도전형의 게이트를 형성하는 단계를 포함하여 구성됨을 특징으로 한다.The present invention for achieving the above object, the step of laminating a gate oxide film and a polysilicon film on a semiconductor substrate; Forming an additionally forming blocking film on the polysilicon film; Forming an additional formation mask on the additional formation blocking film; Patterning the additional formation blocking layer using the additional formation mask to expose a gate region of a second conductivity type, and then removing the additional formation mask; Additionally forming a compensation silicon film in the exposed second gate region by one of selective epitaxial growth (SEG), chemical vapor deposition (CVD), or thermal deposition; And further performing a patterning process to form a gate of the first conductivity type and the second conductivity type having the same height.
또한 상기 목적을 달성하기 위한 본 발명은, 반도체 기판상에 게이트산화막과 폴리실리콘막을 적층하는 단계; 상기 폴리실리콘막상에 추가형성 블로킹막을 형성하는 단계; 상기 추가형성 블로킹막의 상부에 추가형성 마스크를 형성하는 단계; 상기 추가형성 마스크를 이용하여 상기 추가형성 블로킹막을 패터닝하여 제 2 도전형의 게이트영역을 노출시킨후 상기 추가형성 마스크를 제거하는 단계; 최종적으로 제 2 도전형의 게이트영역보다 적은 게이트손실을 갖는 제 1 도전형의 게이트영역을 상기 제 1 도전형의 게이트와 제 2 도전형의 게이트의 높이차이인 50 ~ 300Å 만큼 식각하는 단계; 및 추가로 패터닝공정을 진행하여 동일한 높이의 제 1 도전형의 게이트와 상기 제 2 도전형의 게이트를 형성하는 단계를 포함하여 구성된 것을 특징으로 한다.In addition, the present invention for achieving the above object, the step of laminating a gate oxide film and a polysilicon film on a semiconductor substrate; Forming an additionally forming blocking film on the polysilicon film; Forming an additional formation mask on the additional formation blocking film; Patterning the additional formation blocking layer using the additional formation mask to expose a gate region of a second conductivity type, and then removing the additional formation mask; Finally etching the gate region of the first conductivity type having a gate loss less than the gate area of the second conductivity type by 50 to 300 kV which is a difference between the heights of the gate of the first conductivity type and the gate of the second conductivity type; And further performing a patterning process to form a gate of a first conductivity type and a gate of the second conductivity type having the same height.
도 1은 종래기술에 따른 산화속도 차이에 의해 발생한 스페이서 식각후의 N형 게이트와 P형 게이트의 높이차이를 도시한 단면도.1 is a cross-sectional view showing a height difference between an N-type gate and a P-type gate after spacer etching caused by a difference in oxidation rate according to the prior art.
도 2a 내지 도 2c는 본 발명에 따른 N형 게이트(100)와 P형 게이트(200)가 동일한 높이로 구현되는 과정을 도시한 공정별 단면도.2A to 2C are cross-sectional views illustrating processes in which the N-type gate 100 and the P-type gate 200 according to the present invention are implemented at the same height.
(도면의 주요부분에 대한 부호설명)(Code description of main parts of drawing)
10 : 게이트산화막20 : 폴리실리콘막10 gate oxide film 20 polysilicon film
30 : 추가형성 블로킹막40 : 추가형성 마스크30: additional formation blocking film 40: additional formation mask
50 : 보상실리콘막100 : N형 게이트50: compensation silicon film 100: N-type gate
200 : P형 게이트200: P-type gate
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 N형 게이트(100)와 P형 게이트(200)가 동일한 높이로 구현되는 과정을 도시한 공정별 단면도이다.2A to 2C are cross-sectional views illustrating processes in which the N-type gate 100 and the P-type gate 200 according to the present invention are implemented at the same height.
도 2a에 도시된 바와 같이, 반도체기판(5)상에 게이트산화막(10)과 폴리실리콘막(20)을 차례로 형성한 후에 질화막 또는 질산화막등의 추가형성 블로킹막(30)을 형성한다.As shown in FIG. 2A, after the gate oxide film 10 and the polysilicon film 20 are sequentially formed on the semiconductor substrate 5, an additional forming blocking film 30 such as a nitride film or a nitride oxide film is formed.
그 다음, 추가형성할 부분(N형 게이트영역)과 그 나머지 부분(P형 게이트영역)을 구분하기 위해, 상기 추가형성 블로킹막(30)의 상부에 추가형성 마스크(40)를 형성한 후 상기 추가형성 마스크(40)의 패터닝을 수행하여 N형 게이트영역상에 있는 추가형성 블로킹막(30)부분을 제거한다.Next, to form the additional forming mask 40 on the additional forming blocking layer 30 to distinguish the portion to be additionally formed (N-type gate region) and the remaining portion (P-type gate region). The additional formation mask 40 is patterned to remove portions of the additional formation blocking film 30 on the N-type gate region.
이때, P형 게이트영역보다 빠른 산화속도를 갖는 N형 게이트영역에 보상실리콘막을 추가로 형성하기 위해 P형 게이트영역에서 패터닝을 수행한다. 이때, 상기 추가형성 블로킹막으로는 플라즈마 화학기상증착법(PECVD : Plasma Enhanced Chemical Vapor Deposition), 저압화학기상증착법(LPCVD : Low Pressure Chemical Vapor Deposition), 또는 열증착법 중 어느 하나가 적용된 산화막을 사용할 수 있다.At this time, patterning is performed in the P-type gate region in order to further form a compensation silicon film in the N-type gate region having a faster oxidation rate than the P-type gate region. In this case, as the additionally formed blocking film, an oxide film to which any one of plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or thermal vapor deposition is applied may be used. .
그 다음, 도 2b에 도시된 바와 같이, 상기 추가형성 마스크(40)를 제거한 후 선택적 에피택셜 성장법(SEG : Selective Epitaxial Growth), 화학기상증착법(CVD : Chemical Vapor Deposition) 또는 열증착법 중 어느 하나를 이용하여 상기 추가형성 블로킹막(30)이 제거된 상기 N형 게이트영역(즉, 산화속도가 빠른 영역)에 상기 보상 실리콘(50)을 추가로 형성한다.Next, as shown in FIG. 2B, after removing the additionally formed mask 40, any one of selective epitaxial growth (SEG), chemical vapor deposition (CVD) or thermal vapor deposition. The compensation silicon 50 is further formed in the N-type gate region (ie, the region having a high oxidation rate) from which the additionally formed blocking film 30 is removed.
이때, 상기 추가로 형성하는 보상 실리콘막의 높이는 P형 게이트와 N형 게이트간의 높이차이에 해당하는 50 ~ 300Å 으로 한다.In this case, the height of the additionally formed compensation silicon film is set to 50 to 300 kV corresponding to the height difference between the P-type gate and the N-type gate.
또한, 상기 보상 실리콘막을 형성한 후 200 ~ 1300℃ 의 온도로 어닐링하여 그 하부에 형성된 상기 폴리실리콘막과의 결정상태를 유사하게 함으로써, 후속의 게이트 식각공정에서 두 층의 동질화를 유도하여 식각공정을 안정화시킨다.In addition, by forming the compensation silicon film and then annealing at a temperature of 200 ~ 1300 ℃ to make the crystal state similar to the polysilicon film formed on the bottom, by inducing the homogenization of the two layers in the subsequent gate etching process, the etching process Stabilize.
이와 같이, N형 게이트영역에서 상기 보상 실리콘막(50)을 추가로 형성하게되면, N형 게이트의 산화속도 증가에 의해 초래되는 P형 게이트와의 높이차이를 보상할 수 있게 된다.As such, when the compensation silicon film 50 is further formed in the N-type gate region, it is possible to compensate for the height difference with the P-type gate caused by the increase in the oxidation rate of the N-type gate.
또한, 도펀트의 도핑농도에 따른 산화속도증가에 의해 초래되는 게이트간 높이차이뿐만 아니라, 게이트 손실량도 보상할 수 있게 된다.In addition, the gate loss amount as well as the difference in height between gates caused by an increase in oxidation rate according to the doping concentration of the dopant can be compensated.
한편, 본 발명의 다른 실시예로서, 도면에는 도시하지 않았지만, 도 2b에서와 같이 보상실리콘막(50)을 추가로 형성하지 않고, 손실이 적은 P형 게이트지역에 있는 폴리실리콘막을 50~300Å 정도를 습식 또는 건식으로 제거하여 N형과 P형 게이트의 높이 즉, N형 게이트의 높이(L1)와 P형 게이트의 높이(L2)를 동일하게 유지하는 방법을 이용할 수도 있다.Meanwhile, as another embodiment of the present invention, although not shown in the drawing, the polysilicon film in the P-type gate region having a low loss is approximately 50-300 kPa without additionally forming the compensation silicon film 50 as shown in FIG. 2B. May be removed by a wet or dry method to maintain the height of the N-type and P-type gates, that is, the height L1 of the N-type gate and the height L2 of the P-type gate.
이어서, 도 2c에 도시된 바와 같이, 최종적인 게이트식각공정 및 스페이서형성등의 공정을 거쳐 동일한 높이의 N형 게이트(100) 및 P형 게이트(200)를 확보하게 된다.Subsequently, as shown in FIG. 2C, an N-type gate 100 and a P-type gate 200 having the same height are secured through a final gate etching process and a spacer formation process.
상술한 바와 같이, 본 발명은 N형 게이트(100) 및 P형 게이트(200)의 높이를 거의 동일하게 할 수 있으므로, 소스/드레인 이온주입시의 게이트내의 도펀트들의 투사범위 Rp등의 예상이 충분히 가능하다.As described above, the present invention can make the heights of the N-type gate 100 and the P-type gate 200 substantially the same, so that the projection range Rp of the dopants in the gate during the source / drain ion implantation is sufficiently predicted. It is possible.
또한, 실리사이드 형성공정등에서 게이트산화막의 열화현상등을 억제할 수 있으므로 게이트의 전기적 특성안정화에 크게 기여할 수 있다.In addition, since degradation of the gate oxide film and the like can be suppressed in the silicide formation process or the like, it can greatly contribute to stabilization of electrical characteristics of the gate.
이상에서는 본 발명의 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.
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