KR20040001533A - Method for burying contact using stacked Ti/TiN - Google Patents

Method for burying contact using stacked Ti/TiN Download PDF

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KR20040001533A
KR20040001533A KR1020020036765A KR20020036765A KR20040001533A KR 20040001533 A KR20040001533 A KR 20040001533A KR 1020020036765 A KR1020020036765 A KR 1020020036765A KR 20020036765 A KR20020036765 A KR 20020036765A KR 20040001533 A KR20040001533 A KR 20040001533A
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film
tin
layer
collimator
stacked
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KR1020020036765A
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KR100480913B1 (en
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김우현
노재선
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B23/00—Telescopes, e.g. binoculars; Periscopes; Instruments for viewing the inside of hollow bodies; Viewfinders; Optical aiming or sighting devices
    • G02B23/16—Housings; Caps; Mountings; Supports, e.g. with counterweight
    • G02B23/22—Underwater equipment
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K13/00—Thermometers specially adapted for specific purposes
    • G01K13/02—Thermometers specially adapted for specific purposes for measuring temperature of moving fluids or granular materials capable of flow
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S206/00—Special receptacle or package
    • Y10S206/811—Waterproof

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Astronomy & Astrophysics (AREA)
  • Optics & Photonics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: A contact filling method using a stacked Ti/TiN structure is provided to be capable of reinforcing the adhesive force of a TiN layer for preventing particles generated from the TiN layer. CONSTITUTION: After forming an interlayer dielectric(23) at the upper portion of a semiconductor substrate(21), a via contact hole(25) is formed at the inner portion of the interlayer dielectric. A collimator Ti layer(27) is formed along the surface of the resultant structure. A Ti layer(29) is formed at the upper portion of the collimator Ti layer. Then, a TiN layer(31) is formed at the upper portion of the Ti layer. Preferably, the thickness ratio of the Ti and TiN layer, is in the range of 1:1 -1:10. Preferably, the collimator Ti layer is formed at one chamber and the Ti/TiN layer are formed at another chamber.

Description

적층된 티아이/티아이엔을 이용한 콘택 매립방법{Method for burying contact using stacked Ti/TiN}Method for burying contact using stacked Ti / TiN}

본 발명은 반도체소자의 콘택 형성방법에 관한 것으로서, 보다 상세하게는 적층된 Ti/TiN를 이용한 콘택 매립방법에 관한 것이다.The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to a contact filling method using stacked Ti / TiN.

기존 공정에서의 제1금속층과 제2금속층의 배선연결에 사용하는 비아매립방법은 현재 가장 많이 사용하는 방법으로서, 도 1에서와 같이, 콜리메이터(collimator)가 장착된 챔버에서 스퍼터링방법으로 Ti(17)를 증착하고, 이후 전면 증착이 가능한 챔버에서 종래방법으로 TiN(19)을 스퍼터링에의해 증착하여 진행하는 이른바 콜리메이터 Ti/기존의 TiN 이 사용되고 있다.Via filling method used for wiring connection of the first metal layer and the second metal layer in the existing process is the most commonly used method, as shown in Figure 1, as a sputtering method in a chamber equipped with a collimator (collimator) Ti (17 ), And the so-called collimator Ti / traditional TiN, which proceeds by depositing TiN 19 by sputtering in a conventional method in a chamber capable of front deposition, is used.

이러한 기존 방법은 반도체공정 진행에 있어서, 각각의 챔버에서 진행하기 때문에 각 필름이 지속적으로 사용되고 있으며 이러한 현상에 의해 각 챔버의 측벽에 필름이 증착된다.In the conventional method, each film is continuously used in the process of semiconductor processing, and the film is deposited on the sidewall of each chamber by this phenomenon.

이렇게 측벽이 증착된 필름은 연속적으로 진행된 각 웨이퍼에 떨어져 배선 불량을 일으킬 수 있는 파타클 공급원으로 작용을 하고 있는 실정이다.The sidewall-deposited film acts as a particle source that can fall on each wafer continuously processed and cause wiring defects.

특히, 기존 방법으로 증착된 TiN 막의 경우는 그 정도가 심하여 매우 큰 사이즈의 파티클이 형성되어 반도체소자의 품질을 불량하게 하는 원인이 되고, 심한 경우 반도체소자의 동작을 하지 않는 경우가 된다.In particular, the TiN film deposited by the conventional method is so severe that particles of a very large size are formed, which causes the quality of the semiconductor device to be poor, and in severe cases, the semiconductor device is not operated.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 파티클을 발생시키는 각 챔버측벽으로 증착되는 TiN막을 Ti/TiN의 구조로 형성하여 그 증착된 막의 접착력을 강화시켜 후속공정에서 커다란 파티클 공급원이 되는 것을 방지할 수 있는 적층된 Ti/TiN를 이용한 콘택 매립방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above problems of the prior art, by forming a TiN film deposited on each side wall of the chamber generating particles with a structure of Ti / TiN to strengthen the adhesion of the deposited film is large in a subsequent process It is an object of the present invention to provide a method for filling a contact using stacked Ti / TiN, which can be prevented from becoming a particle source.

도 1은 종래기술에 따른 반도체소자의 콘택 매립방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a contact filling method of a semiconductor device according to the prior art.

도 2는 본 발명에 따른 반도체소자의 콘택 매립방법을 설명하기 위한 단면도.2 is a cross-sectional view illustrating a contact filling method of a semiconductor device according to the present invention.

도 3은 본 발명을 적용하여 나타난 파티클 스펙아웃 레이트를 나타낸 그래프.3 is a graph showing the particle spec out rate shown by applying the present invention.

[도면부호의설명][Description of Drawing Reference]

21 : 반도체기판23 : 층간절연막21 semiconductor substrate 23 interlayer insulating film

25 : 비아콘택홀27 : 콜리메이터 Ti막25: via contact hole 27: collimator Ti film

29 : Ti막31 : TiN막29 Ti film 31 TiN film

상기 목적을 달성하기 위한 본 발명에 따른 적층된 Ti/TiN를 이용한 콘택 매립방법은, 하부금속층과 상부금속층의 층간연결을 위한 비아콘택 매립방법에 있어서, 반도체기판상에 형성된 층간절연막내에 비아콘택홀을 형성하는 단계; 상기 비아콘택홀을 포함한 층간절연막상에 콜리메이터 Ti막을 형성하는 단계; 상기 콜리메이터 Ti막상에 Ti막을 형성하는 단계; 및 상기 Ti막상에 TiN막을 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.In the contact filling method using the stacked Ti / TiN according to the present invention for achieving the above object, in the via contact filling method for the interlayer connection between the lower metal layer and the upper metal layer, a via contact hole in the interlayer insulating film formed on the semiconductor substrate Forming a; Forming a collimator Ti film on the interlayer insulating film including the via contact hole; Forming a Ti film on the collimator Ti film; And forming a TiN film on the Ti film.

(실시예)(Example)

이하, 본 발명에 따른 적층된 Ti/TiN를 이용한 콘택 매립방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a contact filling method using stacked Ti / TiN according to the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 반도체소자의 콘택 매립방법을 설명하기 위한 단면도이고, 도 3은 본 발명을 적용하여 나타난 파티클 스펙아웃 레이트를 나타낸 그래프이다.2 is a cross-sectional view illustrating a method of filling a contact of a semiconductor device according to the present invention, and FIG. 3 is a graph illustrating a particle spec out rate applied by applying the present invention.

본 발명은 챔버 측벽에 증착되어 있는 필름이 떨어져 나와 증착진행중인 웨이퍼표면에 붙지 못하도록 측벽에 붙어 있는 필름들을 접착력이 강한 Ti 막을 이용한다. 즉, TiN막을 증착하는 챔버에 정기적으로 Ti막을 증착할 수 있도록 만들어 주는 것으로 이 방법은 공정을 진행하기 전에 챔버의 분위기를 잡아 주기 위하여 Ti 페이스팅(pasting)하는 방법이다.The present invention utilizes a Ti film having strong adhesion to the films attached to the sidewalls so that the films deposited on the sidewalls of the chamber do not come off and adhere to the wafer surface being deposited. That is, the Ti film is periodically deposited in the chamber for depositing the TiN film. This method is a method of Ti pasting (pasting) to catch the atmosphere of the chamber before proceeding.

그렇지만, 이러한 방법의 경우 연속적으로 공정을 진행하는데 따로 더미 웨이퍼를 이용해야 하느 방법으로 추가 웨이퍼가 필요한 방법이다.However, this method requires additional wafers as a method of using a dummy wafer separately in order to continuously process the process.

본 발명에 따른 적층된 Ti/TiN를 이용한 콘택 매립방법에 대해 구체적으로설명하면, 먼저 도 2에 도시된 바와같이, 반도체기판(21)상에 층간절연막(23)을 증착한후 이를 선택적으로 패터닝하여 비아콘택홀(25)을 형성한다.A method of filling a contact using stacked Ti / TiN according to the present invention will be described in detail. First, as shown in FIG. 2, the interlayer insulating film 23 is deposited on the semiconductor substrate 21 and then selectively patterned. The via contact hole 25 is formed.

그다음, 상기 비아콘택홀(25)을 포함한 층간절연막(23)상에 콜리메이터 Ti막(27)을 형성한다.Next, a collimator Ti film 27 is formed on the interlayer insulating film 23 including the via contact hole 25.

이어서, 상기 콜리메이터 Ti막(27)상에 Ti막(29)을 형성한후 그 위에 TiN막(31)을 형성한다.Subsequently, after forming the Ti film 29 on the collimator Ti film 27, a TiN film 31 is formed thereon.

이때, 비아콘택홀 매립공정에서 한 챔버에서 Ti막(25)을 형성하고, 다른 챔버에서 Ti막(27)/TiN막(29)을 형성하는 방법을 이용한다.At this time, the Ti film 25 is formed in one chamber in the via contact hole filling process, and the Ti film 27 / TiN film 29 is formed in the other chamber.

이렇게 하여, 본 발명에서는 Ti막을 증착하는 동시에 Ti 패이스팅(pasting)효과를 보기 위해 Ti/TiN막 증착공정을 진행하면서 접착력이 좋은 Ti막을 각 챔버에서 증착과정에서의 TiN막과의 사이에서 접착제 역할을 하게 된다.In this way, in the present invention, while the Ti film is deposited and the Ti / TiN film deposition process is performed to see the Ti pasting effect, the adhesive film has a good adhesion between the TiN film and the TiN film during the deposition process in each chamber. Will be

상기에서 설명한 바와같이, 본 발명에 따른 적층된 Ti/TiN를 이용한 콘택 매립방법에 의하면, 챔버의 측벽에 증착되는 막이 비아 콘택 매립공정을 진행하기 위한 배리어 메탈공정을 연속진행할 때 발생되는 파티클의 발생을 줄일 수 있다. 특히, 기존 TiN 공정을 연속으로 진행하면서 발생되는 측벽의 증착을 Ti/TiN 구조로 바꾸어 이 막의 균열에 의해 발생될 수 있는 파티클을 효과적으로 막아 파티클을 줄일 수 있다.As described above, according to the contact filling method using the stacked Ti / TiN according to the present invention, generation of particles generated when the film deposited on the sidewall of the chamber is continuously subjected to the barrier metal process for the via contact filling process. Can be reduced. In particular, it is possible to reduce the particles by effectively preventing the particles that can be generated by the crack of the film by changing the deposition of the sidewall generated during the continuous TiN process to the Ti / TiN structure.

따라서, 이러한 효과는 바로 연속공정진행중에 Ti 패이스팅(pasting)효과를 발생시켜 더미 웨이퍼를 사용하여 진행하는 Ti 패이스팅 효과를 얻을 수 있으며,이로 인하여 더미웨이퍼의 사용을 줄이며, 반도체소자의 제조에서 그 생산원가를 줄일 수 있는 효과가 있다.Therefore, this effect can produce Ti pasting effect during the continuous process to obtain Ti pasting effect that proceeds using dummy wafers, thereby reducing the use of dummy wafers, and in manufacturing semiconductor devices. The cost of production can be reduced.

또한, 현재 진행되고 있는 양산공정에서 본 발명을 적용한 경우에 그 반도체수율을 확인해 보면 약 0.2 % 정도 상승되는 효과가 있다.In addition, when the present invention is applied in the mass production process currently in progress, the semiconductor yield is increased by about 0.2%.

아울러, 도 3에서와 같이, 파티클 패일(particle fail)을 현저히 줄여 주어 그 스펙아웃 레이트(spec out rate)를 15% 정도 개선됨을 보여 주고 있으며, 이로 인하여 장비의 다운로스(down loss)도 5% 정도 개선된다.In addition, as shown in FIG. 3, the particle fail is significantly reduced, and the spec out rate is improved by about 15%, resulting in a 5% down loss of the equipment. Degree is improved.

그러므로, 본 발명은 장기적인 관점에서 반도체소자의 안정화 및 원가절감에 매우 큰 효과를 보일 수 있다.Therefore, the present invention can show a very large effect on the stabilization and cost reduction of the semiconductor device in the long term.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (4)

하부금속층과 상부금속층의 층간연결을 위한 비아콘택 매립방법에 있어서,In the via contact filling method for the interlayer connection between the lower metal layer and the upper metal layer, 반도체기판상에 형성된 층간절연막내에 비아콘택홀을 형성하는 단계;Forming a via contact hole in an interlayer insulating film formed on the semiconductor substrate; 상기 비아콘택홀을 포함한 층간절연막상에 콜리메이터 Ti막을 형성하는 단계;Forming a collimator Ti film on the interlayer insulating film including the via contact hole; 상기 콜리메이터 Ti막상에 Ti막을 형성하는 단계; 및Forming a Ti film on the collimator Ti film; And 상기 Ti막상에 TiN막을 형성하는 단계를 포함하여 구성되는 것을 특징으로하는 적층된 Ti/TiN를 이용한 콘택 매립방법.Forming a TiN film on the Ti film comprising a contact filling method using a stacked Ti / TiN. 제1항에 있어서, 상기 Ti막과 TiN막의 두께 비는 1:1∼1:10인 것을 특징으로하는 적층된 Ti/TiN를 이용한 콘택 매립방법.The method of claim 1, wherein the thickness ratio of the Ti film and the TiN film is 1: 1 to 1:10. 제1항에 있어서, 상기 Ti막/TiN막의 구조를 다층으로 형성하는 것을 특징 으로 하는 적층된 Ti/TiN를 이용한 콘택 매립방법.2. The method of claim 1, wherein the Ti film / TiN film has a multilayer structure. 제1항에 있어서, 콜리메이터 Ti막은 한 챔버에서 형성하고, Ti막/TiN막은 다른 챔버에서 형성하는 것을 특징으로하는 적층된 Ti/TiN를 이용한 콘택 매립방법.The method of claim 1, wherein the collimator Ti film is formed in one chamber and the Ti film / TiN film is formed in another chamber.
KR10-2002-0036765A 2002-06-28 2002-06-28 Method for burying contact using stacked Ti/TiN KR100480913B1 (en)

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KR19980030949A (en) * 1996-10-30 1998-07-25 김광호 Manufacturing Method of Semiconductor Device
KR19980030948A (en) * 1996-10-30 1998-07-25 김광호 Semiconductor device manufacturing method using sputtering equipment
KR19990005452A (en) * 1997-06-30 1999-01-25 김영환 Method of forming barrier metal film in semiconductor device

Cited By (1)

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Publication number Priority date Publication date Assignee Title
KR200457800Y1 (en) * 2009-03-06 2012-01-04 노수희 Road line delineator

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