KR20030097881A - 반도체 메모리 장치의 제조 방법 - Google Patents

반도체 메모리 장치의 제조 방법 Download PDF

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Publication number
KR20030097881A
KR20030097881A KR10-2003-7015025A KR20037015025A KR20030097881A KR 20030097881 A KR20030097881 A KR 20030097881A KR 20037015025 A KR20037015025 A KR 20037015025A KR 20030097881 A KR20030097881 A KR 20030097881A
Authority
KR
South Korea
Prior art keywords
region
memory device
layer
manufacturing
memory
Prior art date
Application number
KR10-2003-7015025A
Other languages
English (en)
Korean (ko)
Inventor
요아힘 뉴에쯜
시그프라이트 슈바르쯜
Original Assignee
인피네온 테크놀로지스 아게
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인피네온 테크놀로지스 아게 filed Critical 인피네온 테크놀로지스 아게
Publication of KR20030097881A publication Critical patent/KR20030097881A/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
KR10-2003-7015025A 2001-05-18 2002-05-07 반도체 메모리 장치의 제조 방법 KR20030097881A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10124366.9 2001-05-18
DE10124366A DE10124366A1 (de) 2001-05-18 2001-05-18 Verfahren zum Herstellen einer Halbleiterspeichereinrichtung
PCT/DE2002/001651 WO2002095827A2 (de) 2001-05-18 2002-05-07 Verfahren zum herstellen einer halbleiterspeichereinrichtung

Publications (1)

Publication Number Publication Date
KR20030097881A true KR20030097881A (ko) 2003-12-31

Family

ID=7685353

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2003-7015025A KR20030097881A (ko) 2001-05-18 2002-05-07 반도체 메모리 장치의 제조 방법

Country Status (4)

Country Link
KR (1) KR20030097881A (zh)
CN (1) CN1509498A (zh)
DE (1) DE10124366A1 (zh)
WO (1) WO2002095827A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10804320B2 (en) 2017-06-05 2020-10-13 Samsung Electronics Co., Ltd. Insulation layer arrangement for magnetic tunnel junction device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784091B1 (en) * 2003-06-05 2004-08-31 International Business Machines Corporation Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices
US11437431B2 (en) 2020-01-15 2022-09-06 Taiwan Semiconductor Manufacturing Company Limited Memory device with flat-top bottom electrodes and methods for forming the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5650958A (en) * 1996-03-18 1997-07-22 International Business Machines Corporation Magnetic tunnel junctions with controlled magnetic response
US5838608A (en) * 1997-06-16 1998-11-17 Motorola, Inc. Multi-layer magnetic random access memory and method for fabricating thereof
EP1097457B1 (de) * 1998-07-15 2003-04-09 Infineon Technologies AG Speicherzellenanordnung, bei der ein elektrischer widerstand eines speicherelements eine information darstellt und durch ein magnetfeld beeinflussbar ist, und verfahren zu deren herstellung
EP1157388B1 (de) * 1999-02-26 2002-07-31 Infineon Technologies AG Speicherzellenanordnung und verfahren zu deren herstellung
US6165803A (en) * 1999-05-17 2000-12-26 Motorola, Inc. Magnetic random access memory and fabricating method thereof
DE10043159A1 (de) * 2000-09-01 2002-03-21 Infineon Technologies Ag Speicherzellenanordnung und Verfahren zu deren Herstellung

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10804320B2 (en) 2017-06-05 2020-10-13 Samsung Electronics Co., Ltd. Insulation layer arrangement for magnetic tunnel junction device
US11462584B2 (en) 2017-06-05 2022-10-04 Samsung Electronics Co., Ltd. Insulation layer arrangement for magnetic tunnel junction device

Also Published As

Publication number Publication date
WO2002095827A3 (de) 2003-08-21
CN1509498A (zh) 2004-06-30
DE10124366A1 (de) 2002-11-28
WO2002095827A2 (de) 2002-11-28

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application