KR20030097881A - Method for producing a semiconductor storage device - Google Patents

Abstract

The invention relates to a particularly simple method of producing a semiconductor storage device (1). This method involves depositing a material in the region for the first passivation region 30 and subsequently polishing the barrier layer on the common layer 26a by nature of the storage element 20. Can be formed between the storage elements 20 arranged in the horizontal direction.

Description

METHODS FOR PRODUCING A SEMICONDUCTOR STORAGE DEVICE

The purpose of developing modern semiconductor memory techniques is to achieve the highest possible integration density, in particular. At the same time, high functional reliability of the resulting memory device and relatively simple process sequences within the fabrication method should be taken into account.

Particularly in the case of MRAM memory devices, the alignment of the individual material layers is important for obtaining the underlying TMR effect in the memory cell. In this case, complex process sequences are sometimes optimally matched geometrically with each other only by high outlays, with process steps that are distinguished in time and method for individual target regions in the processing of semiconductor substrates. Entails the disadvantage of being able to achieve

The present invention relates to a method of manufacturing a semiconductor memory device according to the provision of claim 1.

1-12 show schematic and cross-sectional side views of an intermediate state leading to one embodiment of a manufacturing method according to the present invention for a semiconductor memory device.

The present invention is based on the object of describing a method of manufacturing a semiconductor memory device, in particular an MRAM memory, etc., which can achieve high functional reliability, especially with a few process steps.

In the case of a general type method of manufacturing a semiconductor memory device, this object can be achieved according to the invention by characterizing the matter of claim 1. The dependent claims relate to the useful development of the method according to the invention for manufacturing a semiconductor memory device.

In a general type of method of manufacturing a semiconductor memory device, in particular an MRAM device, etc., on at least one material region, in particular essentially a flat surface area, a plurality of memories in a spaced apart manner in a spatially horizontal direction. Form the device. In addition, the memory elements are formed by spacer elements, which are essentially space-in-between directly adjacent memory elements, covering spacer elements covering lateral, edge and / or marginal regions, in particular as electrically insulating diffusion barriers and the like. In the same way, it is embedded in the first passivation region.

According to a general type of method, a method according to the invention for manufacturing a semiconductor memory device deposits a material region with respect to a first passivation region and removes a stop at a common layer or a protection point thereof by its nature. And forming spacer elements by subsequent polishing, in particular by the CMP method.

Known methods of manufacturing semiconductor memory devices, such as, for example, selective etching-back methods, are used to form the corresponding necessary spacer elements, and the formation of spacer elements and / or alignment of the etching process, where appropriate. -Causes problems and / or complexity in both the horizontal and vertical directions. In contrast, the process of first depositing a material region and then subsequently eroding the material region back to the corresponding level by means of a polishing step, comprises intermediate regions of the memory elements arranged horizontally apart. Or provide a simple and robust method of forming the corresponding spacer elements as barrier regions, in particular facilitating the geometrical alignment of the successive process steps.

In a preferred embodiment of the method according to the invention, magnetoresistive memory elements, in particular TMR stacked elements and the like, are formed as memory elements.

Therefore, the memory element provides a tunnel layer, in particular between a hard-magnetic layer and a soft-magnetic layer, and in particular away from the tunnel layer, the hard-magnetic layer and / or It is advantageous to have a multilayer design that forms the barrier layer in a manner that bonds the soft magnetic layers.

If the memory device is patterned by a lithography and / or etching method using a mask structure as a protective layer, in particular for a memory device, from a layer region formed in a manner in large areas and / or in all areas in two dimensions, a manufacturing method according to the invention Turns out to be particularly simple.

In particular, in the first contact connection, the memory element is provided on a metallization region, in particular on a first access line device and / or in particular in the bottommost case in each case. It is defined to form on the metallization region having one barrier layer.

In another preferred embodiment of the method according to the invention, it is defined to form additional passivation regions, in particular in two dimensions, essentially in large areas and / or in all areas, and / or in particular in the area of the plate surface in nature. Also in this case the arrangement of memory elements and / or spacer elements is defined to be covered and / or buried accordingly. Thus, on the one hand, it is achieved that the pre-formed memory element and the spacer element are protected and, on the other hand, if appropriate, electrically insulated with respect to other circuits or memory elements, or metallization regions arranged thereon.

In each case the cut-outs are formed as trenches or portions thereof which extend at least in part in the horizontal direction, in particular in the longitudinal direction of the individual metallization regions of the first access line device. Particularly advantageous is a form which extends at least locally in nature vertically or horizontally. Therefore, in particular, it is possible to form an access line device which essentially extends perpendicularly to each other, and then accurately position individual memory devices at the intersections of the above access line devices.

For this reason, particularly in the second contact connection of the memory element, in particular to form a second access line device and / or in particular, by appropriately removing the individual protective layer of the individual memory cell, if appropriate, To inherently contact the individual second barrier layers, the cut-out is filled with an intrinsically electrically conductive material. What is achieved by this method is that the first and second access line devices, which are provided with the memory elements between the intersections, are formed in the form of TMR stacks.

The features and further aspects of the invention set forth above will become apparent from the following description.

The present invention represents a simple and robust method for manufacturing large scale integrated magnetic memory cells based on TMR effects. To date, magnetic memories have been formed on a much larger scale in terms of geometry and only based on GMR effects.

The method according to the invention provides a few process steps, particularly in the manufacture of memory elements of semiconductor memory devices. The hard mask used in this case also serves to form self-aligning contacts at the same time, especially for the second or top metallization of the individual TMR stacks of the memory cells. In this case, the process sequence presented in accordance with the present invention does not need to rely on matching the maximum spacing between TMR elements or memory cells in order to achieve filling of the passivation region, for example by nitride deposition or the like.

The process sequences presented according to the present invention are simultaneously robust against lithography litho-misalignment, and have a high degree of freedom for possible circuit designs, precisely with respect to the spacing of TMR cells, and also in tunnels. It is useful in the effect of enabling hard mask robustness for difficult etch processes that result in the simultaneous natural orientation of the contact etch processes for the contacts.

One possible process sequence may in particular have the following steps.

a) forming a starting point for the CMOS wafer including all required transistor circuits.

b) at the top of the initiation point, form one or more wiring planes using a single / dualscene technique using Cu, Al, W or other suitable material—preferably but not essential; Referred to as metallizations.

c) barrier layer or liner (e.g., but not limited to, Ta, TaN, Ti, TiN, etc.) ferromagnetic layer, thin tunnel insulating layer (e.g. subsequent in-situ) depositing a finished TMR layer structure, referred to as a stack hereinafter, comprising a second ferromagnetic layer and a barrier or liner layer.

d) a layer that can be etched with any selectivity to the liner material used to withstand subsequent process temperatures, typically above 200 ° C. and sometimes above 320 ° C. and the insulating materials described below (eg, Oxide, Silk, etc.), hereinafter referred to as hard mask.

e) lithographic patterning of the hard mask and then the stack using a typical but not necessary anisotropic etch (reactiveion etch (RIE)). In this case, the photoresist may be removed before or after etching the stack. In this case, however, the hard mask should not be completely removed.

f) filling gaps created between TMR elements using a suitable insulating material (e.g., SiN, etc.), hereinafter referred to as an insulator. This material should constitute an appropriate diffusion barrier for the metallization and stack material used. The height of the fill should reach such that it does not exceed or exceed the height of the stack and hard mask.

g) planarizing the insulator to approximately the height of the hard mask. This is preferably done by chemical mechanical planarization (CMP). In this case, conventional polishing methods using slurries and pads and methods not using slurries (eg 3M pads, obsidian tools, etc.) can be used. It is advantageous to have a higher polishing rate for the insulator compared to the hard mask, but this is not absolutely necessary. Higher corrosion rates are necessary when projecting the structure. This process step is facilitated by additional deposition (eg, deposition of silicon oxide, etc.) as appropriate and by preplanarization of this auxiliary material.

h) At this point, it is possible to carry out (partial) removal of nitride outside of the cell array, but it is not absolutely necessary. This facilitates subsequent contact connection for metallization between the underlying TMR device and the underlying device. This step may be omitted by proper dishing during insulator planarization and / or high selectivity etching of the subsequently deposited etch stop layer to the hard mask.

i) depositing an insulating etch stop layer, typically silicon nitride. Deposition of a dielectric, typically silicon oxide.

j) lithographic patterning the dielectric for subsequent metal fill with an etch barrier on the etch barrier layer.

k) removing the etch stop layer in the interconnect trench as selectively as possible for the underlying hard mask and metallization outside the cell array.

l) Etching the hard mask as selectively as possible for the liner on the hard mask, insulator, metallization and tunnel element stack.

m) subsequent metallization using standard techniques such as dual damascene, liner deposition, Cu deposition, planarization and the like.

n) Thereafter, applying NO to a plurality of metallization planes using standard techniques such as Cu / Al single / dual damming machine, Al-RIE and the like.

The invention is described in more detail below with reference to the schematic drawings on the basis of a preferred exemplary embodiment of a method according to the invention for manufacturing a semiconductor memory device.

In the following drawings, like reference numerals refer to like elements and structures, and descriptions thereof are not repeated for each situation in every drawing.

Figure 1 is a side cross-sectional view, showing the basic basic structure of this embodiment of the manufacturing method according to the present invention.

This basic structure 10 includes a real semiconductor substrate 11 having a CMOS structure therein, which is not explicitly shown here.

Considering the surface area 11a of the actual semiconductor substrate 11, the surface area 11a of the first metallization layer is patterned in the form of the first access line device 13 having the flat surface area 13a. There is a passivation region 12 having.

Switching to the intermediate state shown in FIG. 2, a so-called TMR stack is formed as the memory element 20. As shown in FIG. These memory elements 20 are independently provided on the surface area 13a of the first access line device 13. Individual layers 21-26 of memory element 20 extend substantially parallel to surface regions 13a, 12a of first passivation region 12 and first access line device 13. In this case a protective layer having a first barrier layer 21, a hard magnetic layer 22, a tunnel barrier layer 23, a soft magnetic layer 24, a second barrier layer 25 and a flat surface 26a ( 26). The last mentioned protective layer 26 is produced, for example, in a previous lithography step in which the memory element 20 is patterned correctly. This protective layer 26 may also certainly act as a protective layer in subsequent process steps.

Switching to the intermediate state of FIG. 3, the device of the memory element 20 on the surface area 13a of the first access line device 13 is embedded in the first passivation area 30 having the flat surface 30a. As a result, the corresponding spacer element 30f is created as a diffusion barrier between adjacent memory elements 20 in the intermediate region 28.

Where appropriate, the spacer element 30f is not formed as a separate geometric object, but rather as part of the necessary fill provided in the horizontal direction between the TMR elements in the intermediate region 28.

What is decisive in the present invention is that when the transition from the intermediate state of FIG. 3 to the intermediate state of FIG. 4, the first passivation region ( 30 is formed with a lower surface area 30a '. As a result, all surface areas remain flat and can create even more possibilities of self-aligned contact processes.

Switching to the intermediate state shown in FIG. 5, the corresponding mask 40 is partially and / or by covering the lower region within the area of the surface 12a of the passivation region 12 where the corresponding metallization 13 is formed. Or a memory element 20 which is optionally deposited, that is to say provided with a (lacuna) spacer element 30f, which is in particular embedded in the first passivation region 30, is subjected to the etching process indicated by the arrows in FIG. Are protected against. By the protection of the mask 40, the passivation region 30 is next passivated region underlying the semiconductor substrate 11, outside the region of the memory element 20, and especially outside the metallization region 13. Up to a free surface 12a. In practice, this region may be regarded as a peripheral region and further patterned. This state is shown in FIG.

In the transition to the intermediate state of FIG. 7, the free surfaces 26a, 30a ′ of the device with the memory cells 20 embedded in the spacer element 30f are then removed by removing the corresponding mask regions 40. Initially exposed. In particular, an etch stop layer 50 made of, for example, nitride or oxide is formed conformally.

Next, as shown in FIG. 8, an additional passivation region on the free surface 50a of the etch stop layer 50 in such a way that there is a cut-out 61 at least at the point where the memory element 20 is located. By forming 60, the cut-out 61 keeps the free surface 50a of the etch stop layer 50 exposed by the additional passivation region 60.

Switching to the intermediate state of FIG. 9, the region of the etch stop layer 50, which then serves as the lower region of the cut-out 61, is further removed by removing it on the memory element 20 and the metallization region 13. An etching step is performed.

Thereafter, an additional etching step is followed in which the protective layer 26 or hard mask 26 of the memory element 20 as shown in FIG. 10 is removed.

Switching to the state of FIG. 11, it may be formed, for example, as a trench extending perpendicular to the first access line 13 to form the second access line device 14 in contact with the memory element 20. All cut-outs 61 are filled with an electrically conductive material 70 by nature having a flat surface 70a.

Switching to the state of FIG. 12, the entire device is covered and protected by an additional passivation region 80.

Explanation of Reference Marks

1: semiconductor memory device 10: basic structure

11: semiconductor substrate 11a: surface region

12: passivation region 12a: surface region

13 first access line device 13a surface area

14 second access line device 20 memory element

21: first barrier layer 22: hard magnetic layer

23: tunnel barrier layer 24: soft magnetic layer

25 second barrier layer 26 protective layer, hard mask

26a: surface area 28: intermediate area

30: first passivation region 30a: surface region

30a ': lower surface area 40: mask area, mask

40a: surface area 50: etch stop layer

50a: surface area 60: second passivation area

60a: surface area 61: cut-out

70 second metallization region 70a surface area

80: third passivation region 80a: surface region

Claims (9)

In the at least one material region 10, 13, in particular on the surface region 13a, which is essentially a flat plate, a plurality of memory elements 20 are formed in a manner spaced apart from each other in the horizontal direction, Between the spatially intimately adjacent memory elements 20, spacer elements 30f covering the lateral, edge and / or marginal regions 20b, in particular inherently electrically insulated diffusions Embedding the memory device 20 in a first passivation region 30 in a manner that forms as a diffusion barrier. In the method of manufacturing a semiconductor memory device such as an MRM memory, The spacer element 30f is deposited with material in the region for the first passivation region 30 and subsequently, in particular a common level in nature of the memory element 20 or its protective layer 26. Formed by polishing using a CMP method with a stop on (26a) Method of manufacturing a semiconductor memory device. The method of claim 1, A method of manufacturing a semiconductor memory device, characterized by forming magnetoresistive memory elements, in particular TMR stacked elements, as memory elements. The method of claim 2, The memory device 20 has, in particular, a tunnel layer 23 provided between the hard-magnetic layer 22 and the soft-magnetic layer 24. In a manner that couples the hard magnetic layer 22 and / or the soft magnetic layer 24, a barrier layer 21, 25 is formed, in particular away from the tunnel layer 23. A method of manufacturing a semiconductor memory device, characterized in that the design). The method according to any one of claims 1 to 3, The memory element 20 is essentially a protective layer 26 for the memory element 20, by lithographic and / or etching methods, from layer regions formed in large and / or all regions in two dimensions. And patterning using a mask structure as a semiconductor memory device. The method according to any one of claims 1 to 4, For the first contact connection, the memory element 20 is formed and / or on a metallization region 13, in particular a first access line device 13. A method of manufacturing a semiconductor memory device, characterized in that the first barrier layer (21) is formed at the bottom. The method according to any one of claims 1 to 5, In particular, by way of example, an additional passivation region 60 is formed within the two-dimensional large region and / or all regions, in particular having the plate surface region 60a in essence, Thereby covering and / or embedding the device of the memory element 20 and / or the spacer element 30f. A method of manufacturing a semiconductor memory device, comprising: The method of claim 6, The cut-outs 61 are selectively formed essentially in the additional passivation region 60, Thereby exposing the surface areas 25a, 26a of the memory element 20, in particular its individual protective layer 26. A method of manufacturing a semiconductor memory device, comprising: The method of claim 7, wherein In each case a trench or part thereof extending at least partially in the horizontal direction, in particular at least locally in nature, in particular in the longitudinal direction of the individual metallization region 13 of the first access line device 13 And forming the cut-out in a form extending vertically or horizontally with respect to the shape of the semiconductor memory device. The method according to claim 7 or 8, For the second contact connection of the memory element 20, in particular for forming the second access line device 14, and / or if appropriate, the individual protective layer 26 of the individual memory cell 20 in advance. Semiconductor, characterized in that the cut-out 61 is essentially filled with an electrically conductive material in order to contact the individual memory elements 20, in particular the individual second barrier layers 25 by removal. Method of manufacturing a memory device.