KR20030097450A - Method for forming capacitors of semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to reduce resistance by forming a concave pad instead of a conventional buried contact plug, and to prevent a bridge phenomenon by disposing the lower surface of a lower electrode inside a buried contact hole. CONSTITUTION: A pad interlayer dielectric is formed on a semiconductor substrate(101). The pad interlayer dielectric is patterned to form the buried contact hole(117) exposing a predetermined region of the semiconductor substrate. A conformal pad conductive layer is formed on the substrate including the inside of the buried contact hole. A sacrificial insulation layer filling the buried contact hole is formed on the pad conductive layer. The sacrificial insulation layer and the pad conductive layer are planarized until the pad interlayer dielectric is exposed, so that the concave pad(118a) and a sacrificial insulation layer pattern are formed. An etch barrier layer(120) and a mold insulation layer are sequentially formed on the concave pad and the sacrificial insulation layer pattern. The mold insulation layer, the etch barrier layer and the sacrificial insulation layer pattern are continuously patterned to form a lower electrode hole exposing the concave pad. A lower electrode layer is formed on the substrate including the inside of the lower electrode hole. The lower electrode layer is separated to form a cylindrical lower electrode(123a). The concave pad is formed of a conductive layer having etch selectivity to the sacrificial insulation layer pattern.

Description

Method for forming capacitors of semiconductor device

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device.

The DRAM cell of the semiconductor device is composed of one transistor and one capacitor. The capacitor is a place for storing data. The capacitor includes a lower electrode, a dielectric layer, and an upper electrode. Typically, the lower electrode is formed in a cylindrical shape with a high key to increase the capacitance. The cylindrical type can use both the inner wall and the outer wall as the area of the capacitor. However, according to the tendency of high integration of semiconductor devices, various problems occur in the method of forming the lower electrode.

1 and 2 are cross-sectional views illustrating a method of forming a conventional capacitor.

Referring to FIG. 1, a buffer plug 5 forming a lower interlayer insulating film 3 on a semiconductor substrate 1 and penetrating the lower interlayer insulating film 3 to contact a predetermined region of the semiconductor substrate 1. To form. A plurality of bit line patterns 11 are formed to cross the lower interlayer insulating layer 3 on which the buffer plug 5 is formed. Each of the bit line patterns 11 includes a conductive layer 7 and a hard mask pattern 9 that are sequentially stacked on the lower interlayer insulating layer 3. Spacers 13 are formed on both sidewalls of each of the bit line patterns 11. An upper interlayer insulating film 15 is formed on the entire surface of the semiconductor substrate 1 having the spacers 13. A buried contact plug 17 penetrates the upper interlayer insulating layer 15 to contact the upper surface of the pad plug 5, and a cone is formed on the entire surface of the semiconductor substrate 1 having the buried contact plug 17. A foamed anti-etching film 19 is formed. A mold conductive layer 21 is formed on the etch stop layer 19.

Referring to FIG. 2, the mold conductive layer 21 and the etch stop layer 19 are successively patterned to form a lower electrode hole exposing an upper surface of the buried contact plug 17, and inside the lower electrode hole. A conformal lower electrode film is formed on the entire surface of the semiconductor substrate. A buffer insulating layer filling the lower electrode hole is formed on the lower electrode layer, and the buffer insulating layer and the lower electrode layer are planarized until the mold conductive layer 21 is exposed to form a cylindrical lower electrode 25 having a large height. ). In accordance with the tendency of high integration of semiconductor devices, the size of wirings or contact holes constituting the semiconductor devices is gradually decreasing. For this reason, the size of the upper surface of the buried contact plug 17 is also reduced. As a result, the contact resistance between the lower electrode 25 and the buried contact plug 17 increases. Due to the increase in the contact resistance, an operating speed of the DRAM cell may decrease. In addition, the bottom electrode hole, the buried contact plug 17 and the alignment margin may be insufficient.

The buffer insulating film and the mold conductive film 21 remaining in the lower electrode hole are removed by performing wet etching, which is an isotropic etching. In this case, the lower electrode 25 may be inclined due to the large height of the lower electrode 25 and the wet etching. As a result, a bridge (k, bridge) may occur due to contact with the neighboring lower electrode 25.

An object of the present invention is to provide a method of forming a capacitor that can reduce the resistance between the bottom electrode of the capacitor and the buried contact plug in contact with the bottom surface of the bottom electrode.

Another technical problem to be achieved by the present invention is to provide a method of forming a capacitor to minimize the bridge caused by the inclined lower electrodes.

1 and 2 are cross-sectional views illustrating a method of forming a conventional capacitor.

3 to 8 are cross-sectional views illustrating a method of forming a capacitor in accordance with a preferred embodiment of the present invention.

Provided is a method of forming a capacitor of a semiconductor device for solving the above technical problems. The method includes forming a pad interlayer insulating film on a semiconductor substrate. The pad interlayer insulating layer is patterned to form a buried contact hole exposing a predetermined region of the semiconductor substrate, and a pad conductive layer is conformally formed on the entire surface of the semiconductor substrate including the inside of the buried contact hole. A sacrificial insulating layer filling the buried contact hole is formed on the pad conductive layer, and the sacrificial insulating layer and the pad conductive layer are planarized until the pad interlayer insulating layer is exposed to form a concave pad and a sacrificial insulating pattern. . An etch stop layer and a mold insulating layer are sequentially formed on the concave pad and the sacrificial insulating layer pattern, and the mold insulating layer, the etch stop layer and the sacrificial insulating layer pattern are sequentially etched to form a lower electrode hole exposing the concave pad. do. A lower electrode film is formed on the entire surface of the semiconductor substrate including the lower electrode hole, and the lower electrode film is separated to form a cylindrical lower electrode. Thus, the contact area between the lower surface of the lower electrode and the concave pad can be increased than that of the conventional one. In addition, a lower surface of the lower electrode is disposed in the buried contact hole. As a result, it is possible to minimize the bridge caused by the lower electrode is inclined.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the implementations introduced herein are provided so that the disclosure may be thorough and complete, and the spirit of the present invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

3 to 8 are cross-sectional views illustrating a method of forming a capacitor in accordance with a preferred embodiment of the present invention.

Referring to FIG. 3, an isolation region 102 is formed in a predetermined region of the semiconductor substrate 101 to define an active region. Impurity diffusion layers 103 are formed by implanting impurity ions into the active region. A buffer plug is formed on an entire surface of the semiconductor substrate 101 including the impurity diffusion layer 103, and passes through the buffer interlayer insulating layer 104 to contact a predetermined region of the impurity diffusion layer 103. 105). The device isolation film 102 is preferably formed of a trench device isolation film, and the buffer interlayer insulating film 104 is preferably formed of a CVD silicon oxide film used as a general interlayer insulating film. The buffer plug 105 is preferably formed of a doped polysilicon film. In addition, the buffer plug 105 may be formed of a tungsten film, which is a metal film.

The bit line conductive layer 110 and the hard mask layer 111 are sequentially formed on the entire surface of the semiconductor substrate 101 having the buffer plug 105. The bit line conductive film 110 may be formed of a tungsten film. When the bit line conductive layer 110 is formed of a tungsten layer, a diffusion barrier layer may be further formed on the buffer interlayer dielectric layer 104 before the bit line conductive layer 110 is formed. The hard mask layer 111 may be formed of an insulating layer having an etching selectivity, for example, a silicon nitride layer, with respect to a silicon oxide layer used as a general interlayer insulating layer.

Referring to FIG. 4, the hard mask layer 111 and the bit line conductive layer 110 are successively patterned to form a plurality of bit line patterns 112 that cross the buffer interlayer dielectric layer 104. In this case, an upper surface of the buffer plugs 105 is exposed between the plurality of bit line patterns 112. Each of the bit line patterns 112 includes a conductive film line 110a and a hard mask pattern 111a that are sequentially stacked. Spacers 113 are formed on both sidewalls of the bit line patterns 112. The spacer 113 may be formed of an insulating film having an etching selectivity, for example, a silicon nitride film, with respect to a silicon oxide film used as a general interlayer insulating film.

The lower interlayer insulating film 114, the middle interlayer insulating film 115, and the upper interlayer insulating film 116 are sequentially formed on the entire surface of the semiconductor substrate 101 having the spacer 113. The lower, middle, and upper interlayer insulating layers 114, 115, and 116 constitute a pad interlayer insulating layer 130.

The lower interlayer insulating film 114 and the upper interlayer insulating film 116 are preferably formed of a silicon oxide film used as a general interlayer insulating film, for example, a CVD silicon oxide film. The intermediate interlayer insulating film 115 may be formed of an insulating film having an etching selectivity with respect to the upper interlayer insulating film 116, for example, a silicon nitride film.

Referring to FIG. 5, a buried contact hole exposing the top surface of the buffer plug 105 by successively patterning the upper interlayer insulating layer 116, the intermediate interlayer insulating layer 115, and the lower interlayer insulating layer 114. 117). In this case, the buried contact hole 117 may be formed as a self-aligned contact hole due to the spacer 113 and the hard mask pattern 111a. In other words, one side wall of the spacer 113 forms part of the sidewall of the buried contact hole 117. In addition, an upper surface of the hard mask pattern 111a may form part of a sidewall of the buried contact hole 117.

The pad conductive layer 118 is conformally formed on the entire surface of the semiconductor substrate 101 including the inside of the buried contact hole 117, and the buried contact hole 117 is filled on the pad conductive layer 118. A sacrificial insulating film 119 is formed. The sacrificial insulating film 119 is preferably formed of an insulating film used as a general interlayer insulating film, for example, a CVD silicon oxide film. The pad conductive layer 118 may be formed of a conductive layer having an etching selectivity with respect to the sacrificial insulating layer 119. For example, it is preferable to form the doped polysilicon film.

Referring to FIG. 6, the sacrificial insulating layer 119 and the pad conductive layer 118 are planarized until the upper interlayer insulating layer 116 is exposed to form a concave pad 118a and a sacrificial insulating layer pattern 119a. To form. The concave pad 118a corresponds to a conventional buried contact plug. The conveyor pad 118a has a larger surface area than that of the conventional buried contact plug.

An etch stop layer 120 and a mold insulating layer 121 are sequentially formed on the concave pad 118a and the sacrificial insulating layer 119a. The mold insulating film 121 is preferably formed of an insulating film used as a general interlayer insulating film, for example, a CVD silicon oxide film. The etch stop layer 120 is formed of an insulating layer having an etch selectivity with respect to the mold insulating layer 121. For example, it is preferable to form with a silicon nitride film.

Referring to FIG. 7, the mold insulating layer 121, the etch stop layer 120, and the sacrificial insulating layer 119a are successively patterned to form a lower electrode hole 122 exposing the concave pad 118a. . In this case, the concave pad 118a is not etched with the etching selectivity with respect to the sacrificial insulating layer pattern 119a. The lower electrode layer 123 is formed on the entire surface of the semiconductor substrate 101 including the lower electrode hole 122. In this case, the contact surface of the lower electrode film 123 and the concave pad 118a has a larger area than the contact area between the conventional buried contact plug and the lower electrode film. The lower electrode layer 123 may be formed of a doped polysilicon layer.

An auxiliary insulating layer 124 is formed on the lower electrode layer 123 to fill the lower electrode hole 122. The auxiliary insulating layer 124 is formed of an insulating layer, for example, a CVD silicon oxide layer, which is used as a general interlayer insulating layer. It is preferable. Thus, the auxiliary insulating layer 124 has an etching selectivity with respect to the etch stop layer 120.

The intermediate interlayer insulating film 114 serves to increase the misalignment margin when the lower electrode hole 122 is formed. In other words, when misalignment occurs when the lower electrode hole 122 is formed, the upper interlayer insulating layer 116 is etched when the sacrificial insulating layer pattern 119a is etched. In this case, since the intermediate interlayer insulating film 115 is an insulating film having an etching selectivity with the upper interlayer insulating film 116, the lower interlayer insulating film 114 under the intermediate interlayer insulating film 115 may be prevented from being etched. In addition, a predetermined region of the concave pad 118a in contact with the upper interlayer insulating layer 116 may be exposed, and the lower electrode layer 123 may be formed in the predetermined region. When the hard mask pattern 111a and the spacer 113 are formed of a silicon nitride film, the intermediate interlayer insulating film 115 may be omitted.

Referring to FIG. 8, the auxiliary insulating layer 124 and the lower electrode layer 123 are planarized until the mold insulating layer 121 is exposed to form a cylindrical lower electrode 123a. At this time, as described above, the contact area between the lower electrode 123a and the concave pad 118a has a larger area than the contact area between the conventional buried contact plug and the lower electrode. Therefore, the contact resistance between the lower electrode 123a and the concave pad 118a can be reduced. As a result, the phenomenon that the operation speed of the capacitor decreases due to the increase in the contact resistance can be suppressed.

The auxiliary insulating layer 124 and the mold insulating layer 121 remaining in the lower electrode hole 122 are removed by isotropic etching, for example, wet etching. In this case, the pad interlayer insulating layer 130 is protected by the etch stop layer 120.

The lower surface of the lower electrode 123a is disposed in the buried contact hole 117. As a result, the bridge phenomenon caused by tilting the lower electrode 123a may be minimized.

The dielectric film 125 and the upper electrode film 126 are sequentially formed on the entire surface of the semiconductor substrate 101 having the lower electrode 123a. As a result, a capacitor including the lower electrode 123a, the dielectric layer 125, and the upper electrode 126 is formed. The dielectric film 125 may be formed of a silicon oxide film-silicon nitride film-silicon oxide film used as a general dielectric film. In addition, it can be formed of a high dielectric insulating film having a higher dielectric constant than that of the silicon nitride film. The upper electrode 126 may be formed of a doped polysilicon film.

As described above, according to the present invention, by forming a concave pad in place of the conventional buried contact plug, the contact surface area of the lower electrode of the capacitor and the concave pad can be increased than that of the conventional one, thereby reducing the resistance. In addition, since the lower surface of the lower electrode is disposed in the buried contact hole, it is possible to minimize the bridge phenomenon caused by the inclined lower electrode.

Claims (11)

Forming a pad interlayer insulating film on the semiconductor substrate; Patterning the pad interlayer insulating film to form a buried contact hole exposing a small region of the semiconductor substrate; Forming a conformal pad conductive film on an entire surface of the semiconductor substrate including the buried contact hole; Forming a sacrificial insulating layer filling the buried contact hole on the pad conductive layer; Planarizing the sacrificial insulating film and the pad conductive film until the pad interlayer insulating film is exposed to form a concave pad and a sacrificial insulating pattern; Sequentially forming an etch stop layer and a mold insulating layer on the concave pad and the sacrificial insulating layer pattern; Successively patterning the mold insulating layer, the etch stop layer and the sacrificial insulating layer pattern to form a lower electrode hole exposing the concave pad; Forming a lower electrode layer on an entire surface of the semiconductor substrate including the lower electrode hole; And And separating the lower electrode layer to form a cylindrical lower electrode, wherein the concave pad is formed of a conductive layer having an etching selectivity with respect to the sacrificial insulating layer pattern. The method of claim 1, Before forming the pad interlayer insulating film, Forming a buffer interlayer insulating film on the semiconductor substrate; Forming a buffer plug penetrating the buffer interlayer insulating layer to make electrical contact with a predetermined region of the semiconductor substrate; Forming a bit line conductive film and a hard mask film on the buffer interlayer insulating film having the buffer plug; Continuously patterning the hard mask layer and the bit line conductive layer to form a plurality of bit line patterns; Forming a spacer on both sidewalls of each of the bit line patterns, wherein the buried contact hole exposes an upper surface of the buffer plug, and one side wall of the spacer forms part of a sidewall of the buried contact hole. Forming method of a capacitor, characterized in that. The method of claim 2, And the hard mask layer and the spacer are formed of a silicon nitride layer. The method of claim 1, Forming the pad interlayer insulating film, And sequentially forming a lower interlayer insulating film, an intermediate interlayer insulating film, and an upper interlayer insulating film on the semiconductor substrate, wherein the intermediate interlayer insulating film is formed of an insulating film having an etch selectivity with respect to the upper interlayer insulating film. Formation method. The method of claim 4, wherein And the intermediate interlayer insulating film is formed of a silicon nitride film. The method of claim 1, And the sacrificial insulating film pattern is formed of a CVD silicon oxide film. The method of claim 1, The concave pad is formed of a doped polysilicon film. The method of claim 1, And the lower electrode is formed of a doped polysilicon film. The method of claim 1, And the etching preventing film is formed of an insulating film having an etching selectivity with respect to the mold insulating film. The method of claim 1, Forming the lower electrode, Forming an auxiliary insulating layer filling the lower electrode hole on the lower electrode layer; Forming a lower electrode by planarizing the auxiliary insulating layer and the lower electrode layer until the mold insulating layer is exposed; And And removing the auxiliary insulating layer and the mold insulating layer remaining in the lower electrode hole by isotropic etching. The method of claim 1, After forming the lower electrode, And forming a dielectric film and an upper electrode on the lower electrode in sequence.