KR20070111795A - A contact structure and method of manufacturing the same - Google Patents

Abstract

A contact structure and a manufacturing method thereof are provided to prevent a contact error between adjacent storage node contact plugs by forming an etching stopper pattern for surrounding the storage node contact plug. A contact structure includes first and second interlayer dielectrics(108,112), an etching stopper pattern(130), and a contact plug(138). The first interlayer dielectric is formed on a substrate and includes contact pads therein. The second interlayer dielectric is formed on the first interlayer dielectric and includes bit line structures which are elongated in a first direction. The etching stopper pattern is formed on the second interlayer dielectric and elongated in a second direction, which is perpendicular to the first direction. The contact plug is electrically connected to the contact pads through the first and second interlayer dielectrics between the etching stopper patterns. An upper portion of the contact plug is contacted with the etching stopper pattern.

Description

Contact structure and method of manufacturing the same

1A-1B are cross-sectional views of a DRAM device in accordance with one embodiment of the present invention.

2A to 9B are cross-sectional views illustrating a method of manufacturing a DRAM device in accordance with an embodiment of the present invention.

10 is a plan view at steps 9a and 9b.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 device isolation region

104: gate 108: first interlayer insulating film

110a and 110b: first contact pad and second contact pad

112: second interlayer insulating film 122: bit line structure

124: third interlayer insulating film 130: etch stop layer pattern

136: fourth interlayer insulating film 138: contact plug

140: storage electrode

The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device including a storage node contact plug and a method of manufacturing the same.

Recent semiconductor devices require high speed operation while having a high storage capacity in terms of functionality. To this end, the semiconductor devices have been developed with manufacturing techniques in order to improve the degree of integration, response speed and reliability.

As the semiconductor device, a DRAM device having free input and output of information and having a high capacity is widely used. Each memory cell of the DRAM device includes one access transistor and one storage capacitor.

As the degree of integration of the memory cells is increased, the horizontal area in which each cell is formed is further reduced. Therefore, the formation of a capacitor having a high capacitance in the reduced area is a more important problem.

In order to increase the effective area of the electrode included in the capacitor is changed from the initial planar capacitor structure to the stack (stack) or trench (trench) capacitor structure, the stack capacitor structure is also changed to the cylindrical capacitor structure. .

In the case of the DRAM device, the cylindrical capacitors should be formed without being in contact with each other in a narrow area. However, since the capacitor must be electrically connected to any one region of the source / drain of the access transistor, the region in which the capacitor is formed is defined according to the position of the source / drain underneath. As a result, the margin between neighboring capacitors is narrow, and the problem of frequent contact between the capacitors occurs.

Recently, a process has been developed to allow the capacitors to be widely disposed between neighboring capacitors regardless of the position of the underlying source / drain.

As a method for widening the spaces between the capacitors, there is a method of forming a wide range of storage node contacts connecting to the capacitors. However, when the storage node contacts are formed to be wide, bridge storage between the storage node contacts may easily occur because the storage contacts are too close to each other.

Accordingly, there is a need for a contact that does not cause bridge failure between neighboring storage node contacts and a method of forming the same.

One object of the present invention for solving the above problems is to provide a contact structure with reduced bridge failure between contacts.

Another object of the present invention for solving the above problems is to provide a method of manufacturing a contact structure as described above.

According to an aspect of the present invention for achieving the above object, the contact structure is provided on the first interlayer insulating film and a first interlayer insulating film provided on the substrate, including the contact pads therein, A second interlayer insulating film including bit line structures extending in a first direction, and an etch provided on the second interlayer insulating film and extending in a second direction perpendicular to the first direction and the first direction and intersecting with each other; A contact plug may be electrically connected to the contact pads through the first and second interlayer insulating layers between the barrier layer pattern and the etch barrier layer, and may have a top portion in contact with the etch barrier layer pattern.

The etch stop layer pattern may be silicon nitride.

According to an aspect of the present invention for achieving the above another object, in the method of manufacturing a contact structure, on the substrate, to form a first interlayer insulating film including contact pads therein. A bit line structure extending in a first direction is formed on the first interlayer insulating layer. The bit line structure is buried on the bit line structure, and a preliminary second interlayer insulating film is formed on the bit line structure, the preliminary second interlayer insulating layer having trenches extending in the direction perpendicular to the first direction and perpendicular to the first direction. An etch stop layer pattern filling the inside of the trench is formed. A portion of the preliminary second interlayer insulating layer and the first interlayer insulating layer between the etch stop layer patterns are etched to form a contact hole through which the contact pads are exposed and a second interlayer insulating layer having a lower height than the preliminary second interlayer insulating layer. The contact holes are buried to form contact plugs having upper portions in contact with the etch stop layer pattern.

The etch stop layer pattern may be formed using silicon nitride. The etch stop layer pattern may include a photoresist pattern extending in the first and second directions and intersecting with each other on the preliminary second interlayer insulating layer, and using the photoresist pattern as an etching mask. The opening may be formed by removing a portion of the upper portion of the insulating layer, and may be formed by filling the inside of the opening. The contact holes may include a photoresist pattern masking a portion of the etch stop layer pattern and a part of the preliminary second interlayer insulating layer on the preliminary second interlayer insulating layer on which the etch stop layer pattern is formed, and use the photoresist pattern as an etch mask. The preliminary contact holes are formed by removing the preliminary second interlayer insulating layer, and exposing the contact pad upper surface, and isotropically etching the preliminary contact holes.

According to the present invention as described above, by forming a vertically cross-etched anti-etching layer pattern it is possible to reduce the bridge failure that the upper contact of the neighboring storage node contacts.

Hereinafter, the contact structure according to a preferred embodiment of the present invention will be described in detail.

1A-1B are cross-sectional views of a DRAM device in one embodiment of the present invention.

1A is a cross-sectional view taken in the word line direction, and FIG. 1B is a cross-sectional view taken in the bit line direction.

1A and 1B, a gate is provided on a substrate 100 having an isolated active region. The isolated active region has a shape extending in a first direction and the gate 104 has a line shape extending in a second direction perpendicular to the first direction. Two gates 104 may be provided in the isolated active region.

Specifically, the gate 104 has a shape in which a gate insulating layer pattern, a gate electrode pattern, and a hard mask pattern are stacked. That is, the gate 104 may be provided as a word line of the DRAM device.

Both side walls of the gate 104 are provided with a first spacer 106 made of silicon nitride. In addition, impurity regions are provided under the surface of the substrate 100 on both sides of the gate 104 to serve as a source and a drain. The first impurity region corresponding to the center portion of the isolated active region becomes a region for connecting with the bit line structure 122, and the second impurity region corresponding to both sides of the active region becomes a region in contact with the capacitor. .

A first interlayer insulating layer 108 is formed to fill the gate 104. In the first interlayer insulating layer 108, contact pads 110a and 110b are connected to the first impurity region and the second impurity region, respectively.

A second interlayer insulating layer 112 is further provided on the first interlayer insulating layer 108 including the contact pads 110a and 110b. Bit line contacts connected to the first contact pads 100a connected to the first impurity regions are provided in the second interlayer insulating layer 112. A bit line structure 122 is formed on the bit line contact. The bit line structure may include, for example, a barrier film pattern 114 and a tungsten pattern 116.

The first and second interlayer insulating films 108 and 112 are made of silicon oxide.

A third interlayer insulating layer 124 including bit line structures 122 extending in the first direction is provided on the second interlayer insulating layer 112. The bit line structure 122 has a shape in which a conductive film pattern and a capping film pattern having a line shape are stacked. In this case, the conductive layer pattern may be formed of a metal pattern, a polysilicon pattern, a metal silicide pattern, or a structure in which the patterns are stacked. For example, the conductive layer pattern may have a structure in which the barrier layer pattern 114 and the tungsten pattern 116 are stacked as illustrated. A portion of the lower surface of the conductive film pattern is in contact with the bit line contact. Therefore, the conductive film pattern is electrically connected to the first impurity region through the bit line contact.

A second spacer 120 may be disposed on both sidewalls of the bit line structures 122.

Meanwhile, the third interlayer insulating layer 124 is thick enough to completely cover the bit line structure 122 on the second interlayer insulating layer 112. In addition, the third interlayer insulating layer 124 may be formed of silicon oxide.

An etch stop layer pattern 130 is provided on the third interlayer insulating layer 124 and has a line shape extending in the first direction and a second direction perpendicular to the first direction and crossing each other. That is, the etch stop layer pattern 130 has a net structure.

In addition, the etch barrier pattern 130 is not positioned at a portion where the storage node contact plug is to be formed, and defines the storage node contact plug region by the etch barrier pattern 130.

Here, the etch stop layer pattern 130 is provided to prevent the third interlayer insulating layer 124 from being excessively etched so that neighboring contacts are connected to each other in the process of extending the storage node contact hole. Therefore, the etching selectivity with respect to the interlayer insulating film is preferably formed of a material, specifically, the etch stop layer pattern 130 may be formed of silicon nitride.

Storage node contact plugs 138 are provided to penetrate through the third interlayer insulating layer 124 and the second interlayer insulating layer 112 and to be connected to the second contact pad 100b that is connected to the second impurity region.

In addition, the height of the storage node contact plugs 138 is the same as the etch barrier pattern 130, and an upper portion of the storage node contact plugs 138 is between the etch barrier pattern 130 and the etch barrier pattern 130. Contact with

The storage node contact plug 138 may be made of polysilicon.

Upper surfaces of the storage node contact plugs 138 include capacitors (not shown) including a storage electrode 140, a dielectric layer (not shown), and a plate electrode (not shown).

In the semiconductor device according to an exemplary embodiment, an etch barrier layer pattern 130 is formed to extend and intersect in a first direction and a second direction on the storage node contact plugs 138 to be adjacent to the storage node contact plug. Bridge failures on top of field 138 can be reduced.

Hereinafter, a method suitable for manufacturing the DRAM device described above will be described.

2A to 9B are cross-sectional views illustrating a method of manufacturing a DRAM device in accordance with an embodiment of the present invention, and FIG. 10 is a plan view at steps 9A and 9B.

2A to 9B, each a diagram is a cross-sectional view of the DRAM device in the word line direction, and each b diagram is a cross-sectional view of the DRAM device in the bit line direction.

2A and 2B illustrate a shallow trench isolation process (STI) on a semiconductor substrate 100 to separate an isolated active region and an isolation region 102 having a first direction in a longitudinal direction. do.

Specifically, a buffer oxide film (not shown) is formed on the semiconductor substrate 100. The buffer oxide film is a film for relieving stress when forming a silicon nitride film (not shown). Subsequently, a silicon nitride film is formed on the buffer oxide film. A portion of the silicon nitride film is removed by a photo process to form a silicon nitride film pattern (not shown). Dry etching the buffer oxide layer using the silicon nitride layer pattern as an etch mask to form a buffer oxide layer pattern. Subsequently, the exposed substrate 100 is etched to a predetermined depth by using the silicon nitride layer pattern as an etch mask. Not shown). In this case, an anti-reflection layer may be formed on the nitride layer to increase the margin of the photolithography process for the active pattern. A silicon oxide film is embedded in the trench and planarized to expose the silicon nitride film pattern (not shown). The silicon isolation layer pattern and the buffer oxide layer pattern are removed by a wet etching process to separate the device isolation region 102 and the active region.

After a thin gate oxide film (not shown) is grown on the surface of the active region by thermal oxidation, a gate electrode film (not shown) and a hard mask film (not shown) made of a conductive material are formed. The hard mask layer and the gate electrode layer are patterned to form a gate 104 in which a gate electrode pattern and a hard mask pattern are stacked.

The gate 104 has a line shape extending in a second direction perpendicular to the first direction. The gate 104 is used in common with the word line. In the isolated active region, two gates 104 are formed side by side.

First spacers 106 made of silicon nitride are formed on both sides of the gate 104. By implanting impurities using the gate 104 and the first spacer 106 as a mask, a first impurity region (not shown) to be provided as a source / drain under the substrate 100 on both sides of the gate 104. And second impurity regions (not shown). An impurity region formed at a center portion of the isolated active region is a first impurity region connected to a bit line, and an impurity region formed at both edges of the isolated active region is a second impurity region connected to a storage electrode of a capacitor. to be.

Forming a first interlayer insulating film 108 to sufficiently fill the gate 104 and partially etching the first interlayer insulating film 108 by a photolithography process to expose the first and second impurity regions, respectively. An in contact hole (not shown) is formed. The first interlayer insulating layer 108 may be formed using silicon oxide.

After the doped polysilicon is deposited in the contact hole, the planarization process is performed to form first and second contact pads 100a and 100b that are connected to the first and second impurity regions. In the following description, a contact pad connected to the first impurity region is referred to as a first contact pad 100a and a second contact pad 100b connected to the second impurity region.

3A and 3B, a second interlayer insulating layer 112 is formed on the first interlayer insulating layer 108 including the first and second contact pads 100a and 100b.

A predetermined portion of the second interlayer insulating layer 112 is etched to form a bit line contact hole (not shown) for selectively exposing only the first contact pad 100a. Subsequently, a barrier metal film (not shown) is formed on the bit line contact hole and the second interlayer insulating film 112. The barrier metal film is formed of a titanium, a titanium nitride film, a tantalum, a tantalum nitride film, or a film in which at least two of them are stacked. Subsequently, a tungsten film (not shown) is formed on the barrier metal film.

A silicon nitride film (not shown) is formed on the tungsten film as a capping film. The capping film serves as a hard mask when etching the tungsten film, and also serves to protect the tungsten film during the self-aligned contact forming process. Therefore, the capping film must be thick enough to remain above a predetermined thickness until the patterning process and the contact forming process of the tungsten film are completely performed.

A first photoresist pattern (not shown) is formed on the capping layer to form the bit line structure 122. Subsequently, the capping layer is etched using the first photoresist pattern as an etching mask to form a capping layer pattern 118. The first photoresist pattern is removed by an ashing and strip process.

The tungsten film and the barrier film are etched anisotropically using the capping film pattern 118 as an etching mask. Through the etching process, the bit line structure 122 and the bit line contact including the barrier layer pattern 114, the tungsten pattern 116, and the capping layer pattern 118 are simultaneously formed. The bit line structure 122 is formed to have a line shape extending in the first direction. In addition, the bit line structure 122 is electrically connected to the first impurity region by being connected to the first contact pad 100a through the bit line contact.

Subsequently, a second spacer 120 is formed on sidewalls of the bit line structure 122.

4A and 4B, a third interlayer insulating layer 124 is formed to completely bury the bit line structure 122. The third interlayer insulating layer 124 may be formed by depositing silicon oxide by chemical vapor deposition.

Subsequently, a rectangular etching mask pattern 126 is formed on the third interlayer insulating layer 124. The etching mask pattern 126 includes a photoresist pattern formed by a photo process.

The etching mask pattern 126 masks a portion where the storage node contact plug is formed and exposes a portion where the storage node contact plug is not formed. In this case, the portion exposed to the etch mask pattern 126 has a line shape extending in the first direction and the second direction, and the lines defined by the etch mask pattern 126 have intersection points that cross each other. That is, it has a net shape and is exposed.

5A and 5B, trenches 128 are formed by partially etching an upper portion of the exposed third interlayer insulating layer 124 using the etching mask pattern 126 as an etching mask.

The trench 128 has a line shape extending in the first direction and the second direction, and the trench 128 has a cross space intersecting with each other.

Next, the etching mask pattern 126 is removed. In this case, when the etching mask pattern 126 is a photoresist pattern, the etching mask pattern 126 may be removed through a strip and an ashing process.

6A and 6B, an etch stop layer (not shown) is formed on the third interlayer insulating layer 124 to fill the inside of the trench 128. The etch stop layer is provided to prevent excessively etched the storage contact holes laterally when partially etching the third interlayer insulating layer 124 to form a storage contact hole in a subsequent process. Therefore, it is preferable that the etch stop layer is formed using a material that is hardly etched under the condition of etching the third interlayer insulating layer 124. Specifically, the etch stop layer may be formed using silicon nitride.

Next, the etch stop layer pattern 130 is formed inside the trench 128 by polishing the etch stop layer to expose the top surface of the third interlayer insulating layer 124.

Referring to FIG. 10, the etch stop layer pattern 130 formed by performing the above process may be formed in a first direction and a second direction to define a portion where a storage node contact plug is formed in the upper side of the third interlayer insulating layer 124. It is formed to extend. In addition, since the etch stop layer pattern 130 extends in the first direction and the second direction, the etch stop layer pattern 130 has an intersection point. Since the etch barrier layer pattern 130 has the shape as described above, a bridge node can be prevented because a subsequent storage node contact plug is not in contact with an adjacent storage node contact plug in any direction.

7A and 7B, a photoresist pattern masking portions of the etch stop layer pattern 130 and the third interlayer insulating layer 124 on the third interlayer insulating layer 124 on which the etch stop layer pattern 130 is formed. To form. The preliminary storage node contact hole 132 exposing the top surface of the second contact pad 100b is formed by removing the exposed third interlayer insulating layer 124 using the photoresist pattern as an etching mask.

After forming the preliminary storage node contact holes 132, the photoresist pattern is removed by an ashing or strip process.

8A and 8B, the third interlayer insulating layer 124 is isotropically etched to create a storage node contact hole 134 having a width wider than that of the preliminary storage node contact holes 132. In this case, an upper portion of the third interlayer insulating layer 124 remaining on the sidewall of the etch stop layer pattern 130 is removed to form a fourth interlayer insulating layer 136 having a height lower than that of the third interlayer insulating layer 124.

In addition, since the etch stop layer pattern 130 is formed on the preliminary storage node contact hole 132, the neighboring storage node contacts by excessive etching in the process of expanding the preliminary storage node contact hole 132. The problem that the holes 134 are connected to each other does not occur.

9A and 9B, the conductive material and the hard mask pattern may be polished so as to fill a conductive material in the storage node contact hole 134 and expose the upper surface of the capping layer pattern 118. 138).

The storage node contact plug 138 is provided between the bit line structures 122 to be electrically connected to the second contact pad 100b. In addition, an upper portion of the storage node contact plug 138 is provided between the etch stop layer patterns 130 and contacts the etch barrier layer 130. That is, as shown in FIG. 10, the etch stop layer pattern 130 has a net structure formed to surround an upper outer wall of the storage node contact plug 138.

As a result, a bridge phenomenon between adjacent storage node contact plugs 138 may be prevented.

Referring again to FIGS. 1A and 1B, cylindrical storage electrodes 140 are formed on the storage node contact plugs 138.

A method of forming the storage electrode 140 will be briefly described. First, a BPSG, TEOS, or a mold film (not shown) in which the storage node contact plug 138 is formed is formed on the fourth interlayer insulating film 136. A predetermined region of the mold layer is etched to form an opening (not shown) that exposes an upper surface of the storage node contact plug. Next, a doped polysilicon film is deposited on the surface of the opening and the mold film surface, and a sacrificial film (not shown) is formed of a material such as USG to bury the opening in which the polysilicon film is deposited. Next, the polysilicon film formed on the mold film is removed to perform a chemical mechanical polishing process so that each node is separated. Next, the sacrificial film and the mold film are removed by an isotropic etching process to form the cylindrical storage electrode 140.

Subsequently, a dielectric film is deposited on the inner and outer surfaces of the storage electrode 140, and then plate electrodes (not shown) are formed on the dielectric film (not shown).

As described above, according to the preferred embodiment of the present invention, an etch barrier layer pattern is formed to surround the storage node contact plug, thereby reducing bridge failures between adjacent storage node contact plugs.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (6)

A first interlayer insulating layer provided on the substrate and including contact pads therein; A second interlayer insulating layer provided on the first interlayer insulating layer and including bit line structures extending in a first direction therein; An etch stop layer pattern provided on the second interlayer insulating layer and extending in a second direction perpendicular to the first direction and the first direction; And And a contact plug electrically connected to the contact pads through the first and second interlayer insulating layers between the etch stop layer patterns and having an upper portion contacting the etch stop layer pattern. The contact structure of claim 1, wherein the etch stop layer pattern is silicon nitride. Forming a first interlayer insulating film on the substrate, the first interlayer insulating film including contact pads therein; Forming a bit line structure extending in a first direction on the first interlayer insulating film; Burying the bit line structure on the bit line structure, forming a preliminary second interlayer insulating film on the bit line structure, the preliminary second interlayer insulating layer having trenches extending in the first direction and perpendicular to the first direction and intersecting with each other; Forming an etch stop layer pattern filling the inside of the trench; Etching a portion of the preliminary second interlayer insulating layer and the first interlayer insulating layer between the etch stop layer patterns to form a contact hole through which the contact pads are exposed and a second interlayer insulating layer having a lower height than the preliminary second interlayer insulating layer; And Burying the contact hole to form contact plugs having upper portions contacting the etch stop layer pattern. The method of claim 3, wherein the etch stop layer pattern is formed using silicon nitride. The method of claim 3, wherein the forming of the etch stop layer pattern comprises: Forming a photoresist pattern on the preliminary second interlayer insulating layer and extending in the first and second directions and intersecting with each other; Removing an upper portion of the preliminary second interlayer insulating layer using the photoresist pattern as an etching mask to create an opening; And And forming an etch stop layer to fill the inside of the opening. The method of claim 3, wherein the contact holes, Forming a photoresist pattern on the preliminary second interlayer insulating layer on which the etch stop layer pattern is formed, masking a portion of the etch stop layer pattern and the preliminary second interlayer insulating layer; Forming preliminary contact holes exposing the upper surface of the contact pad by removing the preliminary second interlayer insulating layer using the photoresist pattern as an etching mask; And And isotropically etching the preliminary contact holes.

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