KR20030088665A - High efficient solar cell and fabrication method thereof - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- 230000006641 stabilisation Effects 0.000 claims description 14
- 238000011105 stabilization Methods 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 229910052709 silver Inorganic materials 0.000 claims description 13
- 229910052804 chromium Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000007772 electroless plating Methods 0.000 claims description 5
- 229910052742 iron Inorganic materials 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000007654 immersion Methods 0.000 claims description 3
- 229910052745 lead Inorganic materials 0.000 claims 2
- 238000009713 electroplating Methods 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 238000002161 passivation Methods 0.000 abstract description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000001771 vacuum deposition Methods 0.000 description 8
- 229910052763 palladium Inorganic materials 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- -1 that is Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Description
본 발명은 고효율 태양전지 및 그 제조방법에 관한 것으로, 더욱 상세하게는 도금법을 이용하여 전면 전극 및 후면 전극을 형성하는 고효율 태양전지 및 그 제조방법에 관한 것이다.The present invention relates to a high efficiency solar cell and a method of manufacturing the same, and more particularly, to a high efficiency solar cell and a method of manufacturing the same to form a front electrode and a rear electrode using a plating method.
일반적으로 태양전지는, 외부에서 들어온 빛에 의해 태양전지의 반도체 내부에서 전자와 정공의 쌍이 생성되고, 이러한 전자와 정공의 쌍에서 pn 접합에서 발생한 전기장에 의해 전자는 n형 반도체로 이동하고 정공은 p형 반도체로 이동함으로써 전력을 생산한다.In general, a solar cell has a pair of electrons and holes generated inside the semiconductor of the solar cell by light from outside, and electrons move to an n-type semiconductor by an electric field generated at a pn junction in the pair of electrons and holes. Moving to p-type semiconductors produces power.
종래 태양전지의 효율을 높이기 위해 고안된 고효율 태양전지 구조의 하나인 피이알엘(PERL : passivated emitter rear locally diffused, 이하 PERL이라 칭한다) 구조에서는, p형의 실리콘 기판의 표면이 광흡수를 높이기 위해텍스처링(texturing)되고, 기판의 상면에는 인(P) 도핑에 의해 n층이 형성되며, n층 및 기판의 후면에는 표면 부동화(passivation) 및 반사방지 효과를 위해 SiO2층이 형성된다. 전면 전극 부분에는 SiO2층이 오프닝(opening)되어 그 하부에 형성된 고농도 인 도핑 영역인 n+영역을 노출시키는 전면 전극 패턴이 형성되며, 전면 전극 패턴을 통해 n+영역과 연결되도록 전면 전극이 형성된다.In the PIL (passivated emitter rear locally diffused) structure, which is one of the high-efficiency solar cell structures designed to improve the efficiency of conventional solar cells, the surface of the p-type silicon substrate may be textured to increase light absorption. In the upper surface of the substrate, n layers are formed by phosphorus (P) doping, and the SiO 2 layer is formed on the n layer and the rear surface of the substrate for surface passivation and antireflection effects. In the front electrode portion, a SiO 2 layer is opened to form a front electrode pattern exposing an n + region, which is a highly doped region formed underneath, and a front electrode is formed to be connected to the n + region through the front electrode pattern. do.
즉, n+영역 상에 Ti층 및 Pd층이 진공증착법에 의해 적층되고, 그 위에 Ag가 진공증착 또는 도금방법으로 형성된다.That is, the Ti layer and the Pd layer are laminated on the n + region by the vacuum deposition method, and Ag is formed thereon by the vacuum deposition or plating method.
후면의 경우 후면필드(back surface field : BSF) 효과에 의해 개방전압(open-circuit voltage)을 증가시켜 태양전지의 효율을 향상시키기 위해, 후면 전극 패턴을 통해 노출되는 p+영역을 포함하여 SiO2층 상에 Al을 진공증착법으로 증착하고 열처리한 후, Al층 상에 Ti층 및 Pd층을 진공증착법으로 적층하고, 그 위에 Ag을 진공증착 또는 도금방법으로 형성함으로써, 후면 전극을 형성한다.In order to improve the efficiency of the solar cell by increasing the open-circuit voltage by the back surface field (BSF) effect, the rear side includes SiO 2 including p + region exposed through the rear electrode pattern. After the deposition of Al on the layer by vacuum deposition and heat treatment, the Ti layer and the Pd layer are laminated on the Al layer by vacuum deposition, and Ag is formed on the layer by vacuum deposition or plating to form a back electrode.
이러한 종래 방법에서는 고가의 진공 장비에서 금속막을 증착하고, 진공 증착법에 의해 금속물질을 적층하며, 일 예로 미국 특허 제4,082,568호에 진공증착법을 이용하여 Ti, Pd을 적층하고 Ag를 도금법에 의해 적층하여 태양전지의 전극을 형성하는 공정이 개시되어 있다.In this conventional method, a metal film is deposited in an expensive vacuum equipment, and a metal material is deposited by vacuum deposition. For example, in US Pat. No. 4,082,568, Ti, Pd is laminated by vacuum deposition, and Ag is deposited by plating. A process for forming an electrode of a solar cell is disclosed.
그러나, 이러한 종래 방법에서는 Ti, Pd을 적층하기 위해 고가의 진공 장비가 필요하고, 금속물질을 진공증착한 후에 포토리소그래피 공정을 통해 전극부분을 제외한 나머지 부분에 증착된 금속물질을 제거하는 리프트 오프(lift-off) 공정을 포함하기 때문에 공정 비용이 높은 단점이 있고, 또한, 실리콘 기판과 전극간의 접착력의 향상 및 콘택 저항의 저하를 위해 사용되는 Ti, Pd와 같은 금속 물질은 재료 자체의 원가가 높은 단점이 있으므로 대량 생산에 적용이 불가능한 문제점이 있었다.However, such a conventional method requires expensive vacuum equipment to deposit Ti and Pd, and lift-off of removing metal materials deposited on the remaining portions except the electrode portion through a photolithography process after vacuum depositing the metal materials. The process cost is high because it includes a lift-off process, and metal materials such as Ti and Pd, which are used to improve adhesion between the silicon substrate and the electrode and lower contact resistance, have a high cost of the material itself. Because of the disadvantages, there was a problem that can not be applied to mass production.
따라서, 고효율 태양전지의 대량생산을 위해서는 그 성능을 유지하면서 저렴한 공정 비용으로 제조할 수 있는 방법이 필요하다.Therefore, for mass production of high efficiency solar cells, there is a need for a method that can be manufactured at low process cost while maintaining its performance.
이러한 요구를 충족시키는 태양전지의 전극 형성 방법으로는 도금 방법이 있다.As a method of forming an electrode of a solar cell that satisfies these requirements, there is a plating method.
전면 전극의 경우 Ti 및 Pd 층을 대체할 수 있는 방법으로 실리콘 기판 상에 Ni 무전해 도금층을 형성하는 방법이 미국 특허 제4,144,139호에서 제안된 바 있다.In the case of the front electrode, a method of forming a Ni electroless plating layer on a silicon substrate as a method to replace the Ti and Pd layers has been proposed in US Pat. No. 4,144,139.
그러나, 후면 전극의 경우에는 접촉전극으로 사용되는 알루미늄층의 기전력(electromotive force)이 높기 때문에 Ni의 도금이 불가능한 문제점이 있다. 예를 들면, 알루미늄의 이온화 경향은 -1.69로서 Ni 도금액에 넣으면 용해되어 버릴 뿐 도금이 되지 않는다.However, in the case of the back electrode, since the electromotive force of the aluminum layer used as the contact electrode is high, there is a problem in that plating of Ni is impossible. For example, the ionization tendency of aluminum is -1.69, and when it is put in a Ni plating solution, it dissolves and is not plated.
한편, 미국특허 5,118,362에서는 도금법이 아닌 금속 페이스트(paste)를 이용한 프린팅(printing) 방법으로 후면전극에서도 Ti 및 Pd층을 Ni로 대체하여 전극을 형성하는 방법이 개시되어 있다. 이 때 프린팅에 의한 Ag와 Al의 접촉 특성이나쁘기 때문에 접촉 부위에 해당하는 Al층을 제거한 후 실리콘 기판이 노출된 부위를 통해 Ni층을 형성하고 그 위에 Ag 전극을 형성한다. 그러나, 이와 같은 프린팅 방법으로는 미세한 구조의 전극을 형성하기가 어려우며 또한 페이스트 자체의 불순물로 인해 고순도의 전극을 형성하기가 어려운 단점이 있다.Meanwhile, US Pat. No. 5,118,362 discloses a method of forming an electrode by replacing Ti and Pd layers with Ni in the back electrode by a printing method using a metal paste rather than a plating method. At this time, since the contact characteristics of Ag and Al by printing are poor, after removing the Al layer corresponding to the contact portion, a Ni layer is formed through the exposed portion of the silicon substrate, and an Ag electrode is formed thereon. However, such a printing method has a disadvantage in that it is difficult to form an electrode having a fine structure and it is difficult to form an electrode of high purity due to impurities in the paste itself.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 효율이 향상된 고효율 태양전지를 저렴한 공정 비용으로 제조하는 데 있다.The present invention is to solve the problems as described above, the object is to manufacture a high efficiency solar cell with improved efficiency at a low process cost.
본 발명의 다른 목적은 Al층 상에 금속 전극 물질을 도금하여 전면 전극 뿐만 아니라 후면 전극 역시 도금법으로 형성하는 데 있다.Another object of the present invention is to plate a metal electrode material on the Al layer to form not only the front electrode but also the rear electrode by the plating method.
도 1은 본 발명의 일 실시예에 따른 고효율 태양전지 구조를 도시한 단면도이다.1 is a cross-sectional view showing a structure of a high efficiency solar cell according to an embodiment of the present invention.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 후면에 Al층이 형성된 반도체 기판을 전처리하여 Al층 상에 안정화층 및 버퍼층을 형성한 후 버퍼층 상에 전극을 도금하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that the electrode substrate is plated on the buffer layer after forming a stabilization layer and a buffer layer on the Al layer by pretreatment of the semiconductor substrate having an Al layer formed on the rear surface.
이하, 본 발명에 따른 고효율 태양전지의 구성에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a configuration of a high efficiency solar cell according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 일 실시예에 따른 고효율 태양전지 구조를 도시한 단면도로서, PERL 구조의 태양전지가 도시되어 있다. 여기서, 제1도전형, 예를 들면 p형의 반도체 기판(1) 상에는 이와 반대 도전형을 가지는 제2도전형, 예를 들면 n형의 반도체층(2)이 형성되어 있고, p형의 반도체 기판(1)과 n형의 반도체층(2) 사이의 계면에는 pn 접합이 형성되어 있어 태양전지의 필수 구성 요소인 pn 구조가 도시되어 있다.1 is a cross-sectional view showing a structure of a high efficiency solar cell according to an embodiment of the present invention, a solar cell of a PERL structure is shown. Here, the second conductive type, for example, the n-type semiconductor layer 2 having the opposite conductivity type is formed on the first conductive type, for example, the p-type semiconductor substrate 1, and the p-type semiconductor is formed. A pn junction is formed at the interface between the substrate 1 and the n-type semiconductor layer 2, so that the pn structure, which is an essential component of the solar cell, is shown.
n형의 반도체층(2)에서 전극이 형성될 부분에는 불순물이 고농도로 도핑된 n+영역(4)이 형성되어 있고, n형의 반도체층(2) 상에는 표면 부동화(passivation) 및 반사방지 효과를 위한 SiO2층(5a)이 형성되어 있다. n+영역(4) 상에는 SiO2층(5a)의 일부분이 오프닝된 전면 전극 패턴(11)을 통해서 Ni 또는 Cr 등의 하부 금속층(12)이 형성되어 있고, 그 상부에는 Ag 또는 Cu로 이루어진 전면 도금층(13)이 하부 금속층을 덮도록 형성되어 있어 전면 전극을 이룬다.In the n-type semiconductor layer 2, an n + region 4 doped with a high concentration of impurities is formed in the portion where the electrode is to be formed. On the n-type semiconductor layer 2, surface passivation and antireflection effects are obtained. SiO 2 layer 5a is formed. A lower metal layer 12, such as Ni or Cr, is formed on the n + region 4 through the front electrode pattern 11 in which a part of the SiO 2 layer 5a is opened. The plating layer 13 is formed to cover the lower metal layer to form a front electrode.
p형의 반도체 기판(1)에는 후면 전극이 형성될 부분에 후면으로부터 불순물이 도핑된 p+영역(3)이 형성되어 있고, 반도체 기판(1)의 후면에는 p+영역(3)을 노출시키도록 일부분이 오프닝된 후면 전극 패턴(6)을 가지는 SiO2층(5b)이 형성되어 있다. 후면 전극 패턴(6)을 통해 노출된 p+영역(3)을 포함하여 SiO2층(5b) 상에는 Al층(7)이 형성되어 있고, Al층(7) 상에는 안정화층(8), 버퍼층(9), 및 후면 도금층(10)이 차례로 형성되어 후면 전극을 이루고 있다.In the p-type semiconductor substrate 1, p + regions 3 doped with impurities from the rear surface are formed in a portion where the rear electrode is to be formed, and the p + region 3 is exposed on the rear surface of the semiconductor substrate 1. The SiO 2 layer 5b having the rear electrode pattern 6 partially opened is formed. An Al layer 7 is formed on the SiO 2 layer 5b including the p + region 3 exposed through the rear electrode pattern 6, and a stabilization layer 8 and a buffer layer on the Al layer 7. 9) and the back plating layer 10 are formed in order to form a back electrode.
여기서 안정화층(8)은 Al층(7) 표면에 형성된 표면 산화막의 산소를 금속원자로 치환하여 형성한 매우 얇은 막으로, 그 두께는 10~100 Å 정도가 되며, 이온화도가 Al 보다는 낮고 전극재료인 Ag 또는 Cu 보다는 높은 금속이면 어느 것이든 사용가능하며, 일례로 Zn, Fe, Ni, Sn, 또는 Pb를 사용할 수 있다.Here, the stabilization layer 8 is a very thin film formed by substituting the oxygen of the surface oxide film formed on the surface of the Al layer 7 with metal atoms, and the thickness thereof is 10 to 100 kPa. As long as the degree of ionization is lower than Al and higher than Ag or Cu as an electrode material, any metal can be used. For example, Zn, Fe, Ni, Sn, or Pb can be used.
버퍼층(9)은 얇은 안정화층(8)이 이후의 두꺼운 도금에 의해 파괴되어 Al층(7) 손상으로 인한 도금표면 불량이 일어나지 않도록 하기 위해 형성하는 것으로서, Ni, Cr, Cu, 또는 Ag 등으로 이루어진다.The buffer layer 9 is formed in such a way that the thin stabilization layer 8 is broken by subsequent thick plating to prevent plating surface defects from occurring due to damage of the Al layer 7. The buffer layer 9 may be formed of Ni, Cr, Cu, or Ag. Is done.
그러면, 상기한 바와 같은 본 발명의 일 실시예에 따른 고효율 태양전지를 제조방법에 대해 상세히 설명한다.Then, a method for manufacturing a high efficiency solar cell according to an embodiment of the present invention as described above will be described in detail.
먼저, 표면에서의 광흡수를 높이기 위해 p형의 실리콘 기판(1)의 표면을 텍스처링한 후 기판의 전면에 인(P)을 도핑하여 n층(2)을 형성한다.First, in order to increase light absorption at the surface, the surface of the p-type silicon substrate 1 is textured, and then the n layer 2 is formed by doping phosphorus (P) on the entire surface of the substrate.
다음, 포토리소그래피 공정에 의해 산화막(미도시)을 마스크로 하여 후면에는 붕소(B)를 도핑하여 실리콘 기판(1) 내에 p+영역(3)을 형성하고, 전면에는 인(P)을 고농도로 도핑하여 n+영역(4)을 형성한다.Next, a p + region 3 is formed in the silicon substrate 1 by doping boron (B) on the back surface using an oxide film (not shown) as a mask by a photolithography process, and phosphorus (P) on the front surface at a high concentration. Doped to form n + region 4.
다음, 마스크로 사용한 산화막을 제거하고, 표면 부동화(passivation) 및 반사방지 효과를 위해 실리콘 기판의 전면 및 후면에 SiO2층(5a, 5b)을 형성한다.Next, the oxide film used as a mask is removed, and SiO 2 layers 5a and 5b are formed on the front and rear surfaces of the silicon substrate for surface passivation and antireflection effects.
다음, 후면 전극이 형성될 부분의 SiO2, 즉, 후면의 p+영역(3) 상의 SiO2(5b) 일부분을 제거하여 오프닝함으로써 후면 전극 패턴(6)을 형성하고, 후면 전극 패턴(6)을 통해 노출된 p+영역(3)을 포함하여 SiO2층(5b)의 상부 전면에 Al층(7)을 약 5000Å 이상의 두께로 증착한 후, 도금을 위한 전처리 공정을 진행한다.Next, the rear electrode pattern 6 is formed by removing and opening a portion of SiO 2 , that is, SiO 2 (5b) on the p + region 3 on the rear side, to form the rear electrode pattern 6. After the Al layer 7 is deposited to a thickness of about 5000 Pa or more on the upper front surface of the SiO 2 layer 5b including the p + region 3 exposed through, a pretreatment process for plating is performed.
전처리를 위해서는 먼저, Al층(7)이 증착된 실리콘 기판(1)을 상온에서 Zn 용액, 일예로 물 1리터당 NaOH 400~500g와 ZnO 80~100g이 혼합된 용액 내에 수 초간 침지하여 Al층(7) 상에 얇은 Zn층(8)을 형성한다. 이 때, Zn층(8)은 Al층(7) 표면 산화막의 산소를 금속원자로 치환하여 형성한 것으로, 그 두께는 10~100 Å 정도가 된다.For pretreatment, first, the silicon substrate 1 on which the Al layer 7 is deposited is immersed for several seconds in a Zn solution, for example, a solution containing 400 to 500 g of NaOH and 80 to 100 g of ZnO per liter of water at room temperature for several seconds. 7) A thin Zn layer 8 is formed on it. At this time, the Zn layer 8 is formed by replacing oxygen of the surface oxide film of the Al layer 7 with a metal atom, and the thickness thereof is 10 to 100 kPa. It is about.
안정화층을 형성하기 위하여 사용된 금속은, 이온화도가 Al 보다는 낮고 전극재료인 Ag 또는 Cu 보다는 높은 금속이면 어느 것이든 사용가능하며, Zn 이외에도 Fe, Ni, Sn, 또는 Pb를 사용할 수 있다.The metal used to form the stabilization layer may be any metal having an ionization degree lower than Al and higher than Ag or Cu as an electrode material, and Fe, Ni, Sn, or Pb may be used in addition to Zn.
다음, Ni, Cr, Cu, 또는 Ag 등을 침지법 또는 금속 스트라이킹(striking) 방법을 이용하여 Zn층(8) 상에 버퍼층(9)을 0.5~10 ㎛의 두께로 형성한다. 버퍼층(9)은 얇은 Zn층(8)이 이후의 두꺼운 도금에 의해 파괴되어 Al층(7) 손상으로 인한 도금표면 불량이 일어나지 않도록 하기 위해 형성하는 것이다.Next, the buffer layer 9 is formed on the Zn layer 8 to a thickness of 0.5 to 10 μm by Ni, Cr, Cu, Ag, or the like by immersion or metal striking. The buffer layer 9 is formed so that the thin Zn layer 8 is broken by subsequent thick plating so that plating surface defects due to Al layer 7 damage do not occur.
다음, Ag 또는 Cu를 전기도금하여 후면 도금층(10)을 10~50 ㎛의 두께로 형성하며, 이로써 안정화층(8), 버퍼층(9) 및 후면 도금층(10)으로 이루어진 후면 전극 형성을 완료한다.Next, Ag or Cu is electroplated to form the back plating layer 10 to a thickness of 10 to 50 μm, thereby completing the formation of the back electrode consisting of the stabilization layer 8, the buffer layer 9, and the back plating layer 10. .
다음, 전면 전극이 형성될 부분의 SiO2(5a), 즉, 전면의 n+영역(4) 상의 SiO2(5a)일부분을 제거하여 오프닝함으로써 전면 전극 패턴(11)을 형성한 후, 전면 전극 패턴(11)을 통해 노출된 n+영역(4) 상에 Ni 또는 Cr을 무전해도금하여 하부 금속층(12)을 형성하고, 그 위에 Ag 또는 Cu를 전기도금하여 전면 도금층(13)을 형성하여 하부 금속층(12) 및 전면 도금층(13)으로 이루어진 전면 전극 형성을 완료한다.Next, after forming the front electrode pattern 11 by opening by removing the SiO 2 (5a) a portion on the SiO 2 (5a), that is, on the front n + regions 4 of the portion to be the front surface electrode is formed, the front electrode Ni or Cr is electroless plated on the n + region 4 exposed through the pattern 11 to form the lower metal layer 12, and Ag or Cu is electroplated thereon to form the front plating layer 13. The formation of the front electrode including the lower metal layer 12 and the front plating layer 13 is completed.
이로써, 본 발명의 일 실시예에 따른 고효율 태양전지의 제조가 완료된다.As a result, the manufacturing of the high efficiency solar cell according to the embodiment of the present invention is completed.
한편, 본 발명의 다른 실시예에서는 전면 및 후면을 동시에 도금할 수도 있다. 이는, 전처리 공정에서 안정화층(8) 형성 후에 버퍼층(9)을 무전해 도금 방법으로 형성하는 것에 의해 가능하다.Meanwhile, in another embodiment of the present invention, the front and rear surfaces may be plated at the same time. This is possible by forming the buffer layer 9 by the electroless plating method after the stabilization layer 8 is formed in the pretreatment step.
이 경우에는, 전면 및 후면에 형성된 SiO2층(5a, 5b)의 일부분, 즉 전면의 n+영역(4) 상의 SiO2일부분 및 후면의 p+영역(3) 상의 SiO2일부분을 오프닝하여 전면 전극 패턴(11) 및 후면 전극 패턴(6)을 형성한 후에, 후면 전극 패턴(6)을 통해 노출된 p+영역(3)을 포함하여 후면 SiO2층(5b)의 상부 전면에 Al층(7)을 약 5000Å 이상의 두께로 증착한 다음, 앞에서 설명한 바와 같은 도금을 위한 전처리 공정을 진행한다.In this case, a portion of the SiO 2 layers 5a and 5b formed on the front and rear surfaces, that is, a portion of SiO 2 on the n + region 4 on the front side and a portion of the SiO 2 on the p + region 3 on the rear side, is opened. After the electrode pattern 11 and the back electrode pattern 6 are formed, an Al layer is formed on the upper front surface of the back SiO 2 layer 5b including the p + region 3 exposed through the back electrode pattern 6. 7) is deposited to a thickness of about 5000 kPa or more, and then the pretreatment process for plating as described above is performed.
전처리 공정에서는 안정화층(8) 형성 후에 Ni 또는 Cr 등을 무전해 도금 방법으로 전면 및 후면에 동시에 형성하여 후면의 버퍼층(9) 및 전면의 하부 금속층(12)을 동시에 형성하고, 그 위에 Ag 또는 Cu를 광 유도 도금(light induced plating)하여 전면 도금층(13) 및 후면 도금층(10)을 동시에 형성한다. 이로써, 전면 전극 및 후면 전극이 동시에 형성되는 것이다.In the pretreatment process, after the stabilization layer 8 is formed, Ni or Cr is simultaneously formed on the front and rear surfaces by an electroless plating method, thereby simultaneously forming the buffer layer 9 on the rear surface and the lower metal layer 12 on the front surface, and forming Ag or Cr on the surface. Cu is light induced plating to simultaneously form the front plating layer 13 and the back plating layer 10. Thus, the front electrode and the rear electrode are formed at the same time.
상기한 바와 같이, 본 발명에 따라 태양전지의 전면 전극 및 후면 전극을 도금법으로 형성하면, 고가의 진공장비를 저렴한 도금장비로 대체할 수 있으므로 공정 비용이 절감되는 효과가 있다.As described above, according to the present invention, if the front electrode and the rear electrode of the solar cell are formed by the plating method, an expensive vacuum equipment can be replaced by an inexpensive plating equipment, thereby reducing the process cost.
또한, 도금법을 이용하면 진공증착법에 비해 공정 시간이 단축되므로 생산성이 향상되는 효과가 있다.In addition, when the plating method is used, the process time is shorter than that of the vacuum deposition method, thereby improving productivity.
그리고, 종래 사용하였던 Ti 및 Pd와 같은 고가의 재료를 Ni, Cu, Zn 등의 저가의 재료로 대체할 수 있으므로 원가가 절감되는 효과가 있다.In addition, since expensive materials such as Ti and Pd, which are conventionally used, can be replaced with inexpensive materials such as Ni, Cu, and Zn, cost is reduced.
또한, 전면 전극 및 후면 전극을 동시에 형성하는 것이 가능하며, 이로 인해 공정이 간소화되고 생산성이 향상되는 효과가 있다.In addition, it is possible to form the front electrode and the rear electrode at the same time, thereby simplifying the process and the productivity is improved.
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| KR101106484B1 (en) * | 2009-12-15 | 2012-01-20 | 이원표 | Device which is prevented ill-smelling of a drainage |
| KR20120015997A (en) * | 2010-08-13 | 2012-02-22 | 삼성전자주식회사 | Conductive paste and electronic device and solar cell including an electrode formed using the conductive paste |
| CN105006495A (en) * | 2015-06-19 | 2015-10-28 | 中国科学院高能物理研究所 | Method for producing selective nanometer textured silicon photocell |
| US9324886B2 (en) | 2008-11-19 | 2016-04-26 | Lg Electronics Inc. | Solar cell and method of manufacturing the same |
| EP3144978A1 (en) * | 2009-12-21 | 2017-03-22 | LG Electronics Inc. | Solar cell |
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| KR101023144B1 (en) * | 2004-02-26 | 2011-03-18 | 삼성에스디아이 주식회사 | Solar cell using layer transfer process and fabrication method thereof |
| US9324886B2 (en) | 2008-11-19 | 2016-04-26 | Lg Electronics Inc. | Solar cell and method of manufacturing the same |
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| KR101106484B1 (en) * | 2009-12-15 | 2012-01-20 | 이원표 | Device which is prevented ill-smelling of a drainage |
| EP3144978A1 (en) * | 2009-12-21 | 2017-03-22 | LG Electronics Inc. | Solar cell |
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| CN105006495A (en) * | 2015-06-19 | 2015-10-28 | 中国科学院高能物理研究所 | Method for producing selective nanometer textured silicon photocell |
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