KR20030056350A - Liquid crystal display panel and apparatus and method of driving the same - Google Patents

Abstract

PURPOSE: An LCD(Liquid Crystal Display) and a device and a method for driving the same are provided to reduce the number of data lines by selectively supplying data to red, green and blue data lines. CONSTITUTION: A pixel(50) of an LCD is composed of a red sub-pixel(R), a green sub-pixel(G), and two blue sub-pixels(B1,B2). The sub-pixels are driven by auxiliary gate lines(GS1,GS2...) interposed between gate lines. The sub-pixels contained in one pixel are supplied with data signals via two data lines. A device for driving the LCD has a timing control unit for controlling the driving time of a data driver and a gate driver in response to the red, green and blue data, a vertical synchronizing signal, a horizontal synchronizing signal, and a dot clock output from a graphic control unit.

Description

Liquid crystal display panel, its driving device and driving method {LIQUID CRYSTAL DISPLAY PANEL AND APPARATUS AND METHOD OF DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, a driving apparatus and a driving method thereof, and more particularly, to a liquid crystal display panel, a driving apparatus and a driving method thereof capable of reducing the number of data driver and data lines.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving device for driving the liquid crystal panel.

In fact, the liquid crystal display includes a liquid crystal panel 2 in which liquid crystal cells are arranged in a matrix as shown in FIG. 1, and a gate driver 4 for driving gate lines GL0 to GLn of the liquid crystal panel 2. ), A data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, a gamma voltage generator 8 for supplying a gamma voltage to the data driver 6, and a gate. A timing controller 10 for controlling the driver 4 and the data driver 6 is provided.

The timing controller 10 controls the driving timing of the gate driver 4 and the data driver 6 in response to a clock signal, horizontal and vertical synchronization signals, etc. input from the outside. In other words, the timing controller 10 generates and supplies a gate shift clock GSC, a gate start pulse GSP, and the like to the gate driver 4 in response to the clock signal and the horizontal and vertical synchronization signals. In addition, the timing controller 10 generates a data clock signal, a data control signal, a polarity control signal, and the like in response to the input clock signal and the horizontal and vertical synchronization signals, and supplies the same to the data clock signal. The red (R), green (G), and blue (B) video data input from the outside are supplied to the data driver 6.

The gate driver 4 supplies the gate high voltage to the gate lines GL1 to GLn during the corresponding syringe period (1H) in response to the control of the timing controller 10 to drive the thin film transistors TFT. In the period, the gate low voltage is applied. In addition, the gate driver 4 applies a gate low voltage to the uppermost gate line GL0 formed for the storage capacitor Cst of the first scan line.

The data driver 6 converts a digital data signal from the timing controller 10 into an analog data signal in response to the control of the timing controller 10 to supply a gate high voltage to the gate lines GL1 to GLn for one horizontal period. The data signal for one horizontal line is supplied to the data lines DL1 to DLm every (1H). At this time, the gamma voltage generator 8 supplies the data driver 6 with a gamma voltage which is set in advance so as to have a different level according to the voltage level of the data signal. The data driver 6 converts the digital data signal into an analog data signal using the gamma voltage so that the gamma characteristic of the liquid crystal display device is corrected. In addition, the data driver 6 inverts the polarity of the data signals supplied to the data lines DL1 to DLm according to the polarity control signal from the timing controller 10. In the case of driving the liquid crystal panel 2 in a dot inversion method, the data driver 6 is opposed to data signals supplied to liquid crystal cells adjacent to each of the liquid crystal cells on the liquid crystal panel 10 in the vertical and horizontal directions. The polarity of the data signals is supplied and the polarities of the data signals supplied to all liquid crystal cells on the liquid crystal panel are reversed in each frame.

The liquid crystal panel 2 is a thin film transistor TFT formed at intersections of liquid crystal cells arranged in a matrix form and n + 1 gate lines GL0 to GLn and m data lines DL1 to DLm. It is provided. The thin film transistor TFT supplies a data signal from the data lines DL1 to DLm to the liquid crystal cell in response to the gate high voltages from the gate lines GL1 to GLn. The liquid crystal cell may be equivalently represented by a liquid crystal capacitor Clc including a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. A storage capacitor Cst is further formed in the liquid crystal cell to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged, that is, while the gate low voltage is applied. The storage capacitor Cst is formed between the previous gate line and the pixel electrode.

The structure of the liquid crystal panel 2 is shown in FIG. 2 in detail. Referring to FIG. 2, a pixel electrode 20 is provided in a cell region provided with a cross structure of gate lines GL1, GL2,..., And data lines DL1, DL2,. The pixel electrode 20 is connected to any one of the data lines DL1, DL2, ... via the source and drain electrodes of a thin film transistor (not shown). The gate electrode of the thin film transistor is connected to one of the gate lines GL1, GL2,... Each of the data lines DL1, DL2, ... is supplied with red, green, and blue data signals for color display.

In the liquid crystal panel 2, red, green, and blue color filters are formed on an upper substrate (not shown) facing each other with the liquid crystal layer interposed therebetween to correspond to the cell region where the pixel electrode 20 is formed, and a reference voltage is applied to the liquid crystal layer. A common electrode for supplying is formed. Each of the liquid crystal cells in which the red, green, and blue color filters are formed corresponds to the subpixels (R, G, and B), and is a combination of the red, green, and blue subpixels (R, G, and B) arranged side by side. The pixel is represented.

The red, green, and blue sub-pixels R, G, and B are connected to the gate lines and driven, and receive data signals from the data lines connected to the gate lines. This is because the output terminal of the data driver supplies red, green, and blue subpixels (R, G, B) to supply a data signal to each of the data lines connected to the red, green, and blue subpixels (R, G, B). It can be seen that the required number corresponding to. Accordingly, as many data drivers as the red, green, and blue subpixels R, G, and B are required.

Accordingly, an object of the present invention is to provide a liquid crystal display panel capable of reducing the number of data drivers and data lines, a driving device thereof, and a driving method thereof.

1 is a block diagram showing a driving apparatus of a conventional liquid crystal display panel.

2 is a plan view showing a conventional liquid crystal display panel.

3 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

4 is a block diagram illustrating a driving device of a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 5 is a table showing video data stored in the memory shown in FIG. 4; FIG.

<Description of Symbols for Main Parts of Drawings>

2, 32; LCD Panel 4, 34: Gate Driver

6, 36: data driver 8: gamma voltage generator

10, 40: timing controller 20: pixel electrode

30: graphic controller 42: memory

50 pixels

In order to achieve the above object, the liquid crystal display panel according to the present invention includes a first sub-pixel for displaying a first color; A second subpixel for displaying a second color; A third subpixel displaying a third color and having a different size than the first and second subpixels; A fourth subpixel displaying the third color and having the same size as the third subpixel; A first data line shared to the first and third subpixels and for supplying the first and third color data to the first and third subpixels; A second data line shared to the second and fourth subpixels and for supplying data of the second and third colors to the second and fourth subpixels; A first scan line for supplying scan signals for selecting the first and second subpixels to the first and second subpixels; And a second scan line for supplying scan signals for selecting the third and fourth subpixels to the third and fourth subpixels.

The third and fourth subpixels may be smaller than the first and second subpixels.

The first color is any one of red, green, and blue, and the second color is any one of red, green, and blue except for the first color, and the third color is other than the first and second colors. It is characterized by any one of red, green and blue.

The first color is red, the second color is green, and the third color is blue.

The driving apparatus of the liquid crystal display panel according to the present invention includes a first subpixel for displaying a first color, a second subpixel for displaying a second color, and a third color for displaying the first and second subpixels. A third subpixel having a different size, a liquid crystal display panel displaying the third color and having a fourth subpixel having the same size as the third subpixel; A data driver for supplying the first and third color data to the first and third subpixels in common, and to supply the second and fourth color data to the second and fourth subpixels in common. Wow; The scan signal for selecting the first and second subpixels is supplied to the first subpixel and the second subpixel in common, and the scan signal for selecting the third and fourth subpixels is supplied to the third and fourth subpixels. And a scan driver for supplying to the fourth subpixel in common.

The apparatus may further include a controller configured to control driving timing of each of the data driver and the scan driver, and to separate the first to fourth color data from input data.

The controller generates a source sampling clock and a gate shift clock twice as fast as a reference clock, and supplies them to the data driver and the scan driver, respectively.

The control unit may generate a source start pulse and a gate start pulse which are twice as small as a width of a reference clock, and supply the source start pulse and the gate start pulse to the data driver and the scan driver, respectively.

The controller generates a source output enable signal and a gate output enable signal that are two times smaller than the width of the reference clock, and supply the same to the data driver and the scan driver.

A method of driving a liquid crystal display panel according to the present invention includes supplying a first scan signal to a first scan line including a first subpixel for displaying a first color and a second subpixel for displaying a second color; And simultaneously supplying data of the first and second colors to the first and second subpixels so as to be synchronized with the first scan signal, displaying a third color different from the first and second colors. Supplying a second scan signal to a second scan line including a plurality of third subpixels having a size different from that of the first and second subpixels, and supplying data of the third color to be synchronized with the second scan signal. Simultaneously supplying to each of the third subpixels.

Other objects and features of the present invention in addition to the above objects will be apparent from the description of the embodiments with reference to the accompanying drawings.

A preferred embodiment of the present invention will be described with reference to FIGS. 3 to 5.

3 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention. In the liquid crystal display panel, each pixel 50 includes one red subpixel R, a green subpixel G, and two blue subpixels B1 and B2. As each pixel 50 is composed of four subpixels R, G, B1, and B2, the number of conventional data lines can be reduced.

In FIG. 3, four subpixels R, G, B1, and B2 included in one pixel 50 are disposed between two gate lines, that is, gate lines GL1, GL2,... It is driven by the auxiliary gate lines GS1, GS2, .... For example, four subpixels R, G, and B1 are provided between the gate lines GL1, GL2,... And the auxiliary gate lines GS1, GS2,... , The red and green subpixels R and G positioned at the top of the B2 are driven during the period when the gate high voltage is supplied to the gate lines GL1, GL2, ..., and the auxiliary gate line GS1, The first sub-pixel R, G, B1, and B2 disposed between the GS2, ..., and the gate lines GL1, GL2, ..., constituting the pixels 50; And the second blue subpixels B1 and B2 are driven during a period when the gate high voltage is supplied to the auxiliary gate lines GS1, GS2,...

In addition, the subpixels R, G, B1, and B2 included in one pixel 50 receive a data signal through two data lines. For example, the red subpixel R and the first blue subpixel B1 positioned on the left side among the subpixels R, G, B1, and B2 of one pixel 50 may have the odd data line DL1, The green subpixel G and the second blue subpixel B2, which are connected to DL3, ... and located on the right side, are connected to even-numbered data lines DL2, DL4, ....

As shown in FIG. 4, the driving device of the liquid crystal display panel for driving the pixels 50 includes red, green, and blue data R, G, and B and a vertical synchronous signal from the graphic controller 30. And a timing controller 40 for controlling the driving timing of the data driver 36 and the gate driver 34 in response to the V) and the horizontal synchronizing signal H, the dot clock DCLK, and the like.

The timing controller 40 generates a gate shift clock GSC, a gate start pulse GSP, and the like in response to the dot clock DCLK, the vertical synchronization signal V, and the horizontal synchronization signal H, thereby generating the gate driver 34. To feed. In addition, the timing controller 40 may include a source output enable SOE, a source sampling clock SSC, and a source start pulse SSP in response to a dot clock DCLK, a vertical synchronization signal V, and a horizontal synchronization signal H. ), The polarity control signal (POL), etc. are generated and supplied to the data driver 36 and the red (R), green (G), and blue inputted from the graphic controller 30 in synchronization with the source output enable (SOE). (B) Supply data to the data driver 36.

In detail, the timing controller 40 stores the red (R), green (G), and blue (B) data input from the graphic controller 30, and the sub-pixels R, G, B1, and B2 of the pixels 50. (R), green (G), blue (B) is further provided with a memory 42 for storing separately.

The memory 42 includes red (R1, R2, ..., Rn) and green (G1, G2) for supplying the red and green subpixels (R, G) of the pixels 50, as shown in FIG. , ..., Gn) Data are stored alternately. Also, the same blue data B1, B1, B2, B2, ..., Bn, and Bn are converted into two and stored in the memory 42 to supply the blue subpixels B of the pixels 50. . In other words, the red (R), green (G), and blue (B) data input from the graphic controller 30 are driven by the timing controller 40 to drive the gate lines GL1, GL2,... In this case, red (R1, R2, ..., Rn) and green (G1, G2, ..., Gn) data are supplied to the data lines DL1, DL2, ..., and the auxiliary gate lines ( When the GS1, GS2, ... are driven, the memory (so that the blue data B1, B1, B2, B2, ..., Bn, Bn) is supplied to the data lines DL1, DL2, ... 42).

In addition, the timing controller 40 generates a frequency of the source sampling clock SSC and the gate shift clock GSC to have a frequency twice that of the prior art in order to drive the gate lines twice that of the conventional liquid crystal display panel. . That is, the timing controller 40 reduces the pulse widths of the source sampling pulses SSP and the gate shift clock GSC to twice the size of the conventional source sampling clock SSC and the gate shift clock GSC having twice the frequency. Create In addition, the timing controller 40 generates the frequency of the source output enable SOE and the gate output enable GOE to be twice as small as before.

The timing controller 40 supplies the modulated gate output enable GOE, the gate shift clock GSC, and the gate start pulse GSP to the gate driver 34. In addition, the timing controller 40 controls control signals such as the modulated source sampling clock SSC, the source output enable SOE, and the source start pulse SSP, and red (R) and green stored in the memory 42. Two blue (B) data equal to (G) are supplied to the data driver 36.

When the gate driver 34 supplies the red (R) and green (G) data to the liquid crystal panel 32 in response to the modulated control signal of the timing controller 40, the gate driver 34 scans the gate lines GL1 to GLn. The thin film transistors are driven by supplying a gate high voltage during the period (1H), and a gate low voltage is applied during the remaining period. In addition, when the blue data B is supplied to the liquid crystal panel 32, the thin film transistors are driven by supplying a gate high voltage to the auxiliary gate lines GS1, GS2,... During the corresponding syringe (1H). In the remaining period, the gate low voltage is applied.

The data driver 36 converts the digital data signal from the timing controller 40 into an analog data signal in response to the modulated control signal of the timing controller 40 to supply a gate high voltage to the gate lines GL1 to GLn. The data signal for one horizontal line is supplied to the data lines DL1 to DLm every one horizontal period 1H.

The liquid crystal panel 32 includes liquid crystal cells arranged in a matrix and thin film transistors formed at intersections of n gate lines GL1 to GLn and m data lines DL1 to DLm, respectively. The thin film transistor supplies a data signal from the data lines DL1 to DLm to the liquid crystal cell in response to the gate high voltages from the gate lines GL1 to GLn. The liquid crystal cell may be equivalently represented by a liquid crystal capacitor including a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor. Further, a storage capacitor is further formed in the liquid crystal cell to maintain the data voltage charged in the liquid crystal capacitor until the next data voltage is charged, that is, while the gate low voltage is applied. The storage capacitor is formed between the previous gate line and the pixel electrode.

The driving method of such a liquid crystal display device is as follows. First, when the gate lines GL1, GL2,... Are driven in response to the drained control signal of the timing controller 40, red (R) and green (G) stored in the memory 42 of the timing controller 40 are driven. ) Data are supplied to the data driver 36 and supplied to the data lines DL1, DL2, .... Then, when the auxiliary gate lines GS1, GS2,... Are driven in response to the drained control signal of the timing controller 40, blue B1 and B1 stored in the memory 42 of the timing controller 40. ) Data are supplied to the data driver 36 and supplied to the data lines DL1, DL2, .... That is, only the red (R) and green (G) data is supplied to the data lines when the odd gate lines are driven, and only the blue (B) data is supplied to the data lines when the even gate lines are driven. .

Meanwhile, in the present invention, when the gate lines GL1, GL2, ... are driven, red and green data are supplied to the data lines DL1, DL2, ..., for example. And data of any two colors of green and blue.

In addition, when the auxiliary gate lines GS1, GS2,... Are driven, the blue data is supplied to the data lines DL1, DL2..., And driven. However, the gate lines GL1. , GL2, ...) may be one color data except for any two colors of red, green, and blue supplied to the data lines DL1, DL2, .... For example, when the gate lines GL1, GL2, ... are driven, red and blue data are supplied to the data lines DL1, DL2, ..., and the auxiliary gate lines GS1, GS2, ... When ...) is driven, green data may be supplied to the data lines DL1, DL2, ....

On the other hand, when the gate lines GL1, GL2, ... are driven, green and blue data are supplied to the data lines DL1, DL2, ..., respectively, and the auxiliary gate lines GS1, GS2,. When ..) is driven, red data may be supplied to the data lines DL1, DL2, ....

As described above, in the liquid crystal display panel according to the present invention, a driving device and a driving method thereof, a pixel is formed by arranging one pixel by arranging red and green subpixels on the top and blue subpixels separated on the bottom. The number of data lines can be reduced by supplying only red and green data to the data lines during line driving, and supplying only blue data to the data lines when driving even gate lines. In this way, the number of data drivers may be reduced due to the reduction in the number of data lines.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (15)

A first subpixel for displaying a first color; A second subpixel for displaying a second color; A third subpixel displaying a third color and having a different size than the first and second subpixels; A fourth subpixel displaying the third color and having the same size as the third subpixel; A first data line shared to the first and third subpixels and for supplying the first and third color data to the first and third subpixels; A second data line shared to the second and fourth subpixels and for supplying data of the second and third colors to the second and fourth subpixels; A first scan line for supplying scan signals for selecting the first and second subpixels to the first and second subpixels; And a second scan line for supplying scan signals for selecting the third and fourth subpixels to the third and fourth subpixels. The method of claim 1, And the third and fourth subpixels are smaller than the first and second subpixels. The method of claim 1, The first color is any one of red, green, and blue, The second color is any one of red, green, and blue except for the first color. And the third color is any one of red, green, and blue except for the first and second colors. The method of claim 3, wherein The first color is red, The second color is green, And the third color is blue. A first subpixel for displaying a first color, a second subpixel for displaying a second color, a third subpixel for displaying a third color and having a different size than the first and second subpixels, the third A liquid crystal display panel displaying a color and having a fourth subpixel having the same size as the third subpixel; A data driver for supplying the first and third color data to the first and third subpixels in common, and to supply the second and fourth color data to the second and fourth subpixels in common. Wow; The scan signal for selecting the first and second subpixels is supplied to the first subpixel and the second subpixel in common, and the scan signal for selecting the third and fourth subpixels is supplied to the third and fourth subpixels. And a scan driver for supplying to the fourth subpixel in common. The method of claim 5, And a control unit for controlling the driving timing of each of the data driver and the scan driver, and for separating the first to fourth color data from the input data. The method of claim 6, And the controller generates a source sampling clock and a gate shift clock twice as fast as a reference clock, and supplies them to the data driver and the scan driver, respectively. The method of claim 6, And the control unit generates source start pulses and gate start pulses that are twice as small as a width of a reference clock, and supplies them to the data driver and the scan driver, respectively. The method of claim 6, And the controller generates a source output enable signal and a gate output enable signal that are twice as small as a width of a reference clock, and supply them to the data driver and the scan driver, respectively. The method of claim 5, And the first and fourth subpixels are smaller than the first and second subpixels. The method of claim 5, The first color is any one of red, green, and blue, The second color is any one of red, green, and blue except for the first color. And the third color is any one of red, green, and blue except for the first and second colors. The method of claim 11, The first color is red, The second color is green, And the third color is blue. Supplying a first scan signal to a first scan line comprising a first subpixel for displaying a first color and a second subpixel for displaying a second color; Simultaneously supplying data of the first and second colors to the first and second subpixels so as to be synchronized with the first scan signal; Supplying a second scan signal to a second scan line including a plurality of third subpixels displaying a third color different from the first and second colors and having a different size from the first and second subpixels; , And simultaneously supplying data of the third color to each of the third subpixels so as to be synchronized with the second scan signal. The method of claim 13, The first color is any one of red, green, and blue, The second color is any one of red, green, and blue except for the first color. And the third color is any one of red, green, and blue except for the first and second colors. The method of claim 14, The first color is red, The second color is green, And the third color is blue.