KR20030054804A - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
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- KR20030054804A KR20030054804A KR1020010085216A KR20010085216A KR20030054804A KR 20030054804 A KR20030054804 A KR 20030054804A KR 1020010085216 A KR1020010085216 A KR 1020010085216A KR 20010085216 A KR20010085216 A KR 20010085216A KR 20030054804 A KR20030054804 A KR 20030054804A
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- gate
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- gate electrodes
- insulating layer
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 3
- 125000006850 spacer group Chemical group 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 239000000463 material Substances 0.000 description 6
- 238000009413 insulation Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000005054 agglomeration Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 특히 게이트의 살리사이드 형성 영역을 최대한 확보한후 공정을 진행하여 저저항 및 우수한 열적 안정성을 갖도록한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method of manufacturing a semiconductor device having a low resistance and excellent thermal stability by performing a process after securing the salicide forming region of the gate to the maximum.
일반적으로 고속의 반도체 소자를 구성하기 위하여 게이트 전극과 소오스/드레인 영역의 면저항과 콘택 저항을 감소시켜야 한다. 이를 위하여, 게이트 전극과 소오스/드레인 영역에만 선택적으로 비저항이 낮은 실리사이드(silicide)를 형성시키는 살리사이드 공정이 널리 사용되고 있다.In general, in order to form a high-speed semiconductor device, the sheet resistance and the contact resistance of the gate electrode and the source / drain regions should be reduced. For this purpose, a salicide process for forming silicide with low resistivity selectively in the gate electrode and the source / drain regions is widely used.
특히 1G 이상의 DRAM 또는 로직(logic) 및 통합 메모리 로직(Merged Memory Logic; MML) 소자 등의 게이트 특성을 향상시키기 위해 살리사이드 게이트 공정이 많이 적용되고 있다.In particular, salicide gate processes have been widely applied to improve gate characteristics of 1G DRAM or more logic and integrated memory logic (MML) devices.
이하, 첨부된 도면을 참고하여 종래 기술의 게이트 전극 형성에 관하여 설명하면 다음과 같다.Hereinafter, the gate electrode formation according to the related art will be described with reference to the accompanying drawings.
도 1a내지 도 1d는 종래 기술의 게이트 전극 형성을 위한 공정 단면도이다.1A to 1D are cross-sectional views of a process for forming a gate electrode of the prior art.
도 1a에서와 같이, 반도체 기판(11)의 소자 격리 영역에 필드 산화막(12)을 성장시킨 후 반도체 기판(11)의 액티브 영역에 게이트 산화막(13)을 형성한다.As shown in FIG. 1A, the field oxide film 12 is grown in the device isolation region of the semiconductor substrate 11, and then the gate oxide film 13 is formed in the active region of the semiconductor substrate 11.
이어, 게이트 산화막(13) 상부에 폴리실리콘층을 형성한후 선택적으로 패터닝하여 게이트 전극(14)을 형성한다.Subsequently, a polysilicon layer is formed on the gate oxide layer 13 and then selectively patterned to form the gate electrode 14.
그리고 상기 게이트 전극(14)을 마스크로 하여 반도체 기판(11)의 표면내에 불순물 이온을 주입하여 LDD(Lightly Doped Drain)영역을 형성하기 위한 저농도 불순물 영역(15)을 형성한다.In addition, the impurity ions are implanted into the surface of the semiconductor substrate 11 using the gate electrode 14 as a mask to form a low concentration impurity region 15 for forming a lightly doped drain (LDD) region.
이어, 도 1b에서와 같이, 상기의 게이트 전극(14) 및 저농도 불순물 영역(15)을 포함하는 전면에 측벽 형성용 물질층을 증착하고 이방성 식각 공정으로게이트 전극(14)의 측면에 게이트 측벽(16)을 형성한다.Subsequently, as shown in FIG. 1B, a material layer for forming sidewalls is deposited on the entire surface including the gate electrode 14 and the low concentration impurity region 15, and an anisotropic etching process is performed on the sidewalls of the gate electrode 14. 16).
그리고 상기 게이트 측벽(16)을 포함하는 전면에 불순물 이온을 주입하여 게이트 전극(14) 양측의 액티브 표면내에 소오스/드레인 영역(17)을 형성한다.Impurity ions are implanted into the entire surface including the gate sidewall 16 to form source / drain regions 17 in active surfaces on both sides of the gate electrode 14.
이어, 도 1c에서와 같이, 전면에 고융점 금속 예를들면, Co, Ti등의 물질을 증착하여 실리사이드 형성용 물질층(18)을 형성한다.Subsequently, as illustrated in FIG. 1C, a material of high melting point metal such as Co and Ti is deposited on the entire surface to form a silicide forming material layer 18.
그리고 도 1d에서와 같이, 상기 실리사이드 형성용 물질층(18)을 열처리 공정으로 실리사이드화하여 액티브 표면 및 게이트 전극(14)의 상면에 살리사이드층(19)을 형성하고, 미반응의 실리사이드 형성용 물질층(18)을 제거한다.As shown in FIG. 1D, the silicide forming material layer 18 is silicided to form a salicide layer 19 on the active surface and the top surface of the gate electrode 14, thereby forming unreacted silicide. The material layer 18 is removed.
이와 같은 실리사이드 공정시에 열처리등의 공정 조건에 의해 살리사이드층이 불균일하게 형성되거나 뭉침 현상(agglomerate)이 발생될 수 있다.In the silicide process, the salicide layer may be unevenly formed or agglomerated due to process conditions such as heat treatment.
이와 같이 불균일하게 형성된 실리사이드는 소자 결함 또는 필드 산화막에서의 누설 전류 등의 문제를 야기한다.The non-uniformly formed silicide causes problems such as device defects or leakage currents in the field oxide film.
그러나 이와 같은 종래 기술의 반도체 소자의 게이트 전극 형성 공정에 있어서는 다음과 같은 문제점이 있다.However, in the gate electrode forming process of the semiconductor device of the prior art, there are the following problems.
살리사이드층의 뭉침 현상(agglomerate)을 제어하지 못하여 누설 전류 등의 문제를 야기하고, 접합 두께가 0.1㎛ 이하로 얇아지면 불균일한 실리사이드로 인해 접합층 자체에서의 누설 문제도 심각해진다.The control of agglomeration of the salicide layer (agglomerate) causes problems such as leakage current, and when the junction thickness becomes thinner than 0.1 µm, the problem of leakage in the junction layer itself is also serious due to uneven silicide.
또한, 게이트 살리사이드층의 저항에 대한 고려가 이루어지지 않아 소자의동작 속도에 영향을 주고, 열적 안정성이 충분히 확보되지 않아 소자의 신뢰성을 저하시킨다.In addition, the resistance of the gate salicide layer is not taken into consideration, which affects the operation speed of the device, and thermal stability is not sufficiently secured, thereby lowering the reliability of the device.
본 발명은 이와 같은 종래 기술의 게이트 전극 제조 공정의 문제를 해결하기 위한 것으로, 게이트의 살리사이드 형성 영역을 최대한 확보한후 공정을 진행하여 저저항 및 우수한 열적 안정성을 갖도록한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art gate electrode manufacturing process, the process for securing a salicide forming region of the gate as possible to proceed to the process to produce a semiconductor device having a low resistance and excellent thermal stability The purpose is to provide.
도 1a내지 도 1d는 종래 기술의 게이트 전극 형성을 위한 공정 단면도1A to 1D are cross-sectional views of a process for forming a gate electrode of the prior art.
도 2a내지 도 2l은 본 발명에 따른 게이트 전극 형성을 위한 공정 단면도2A to 2L are cross-sectional views of a process for forming a gate electrode according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21. 반도체 기판 22. 소자 격리층21. Semiconductor substrate 22. Device isolation layer
23a.23b. 게이트 전극 24. 저농도 불순물 영역23a.23b. Gate electrode 24. Low concentration impurity region
25. 제 1 절연층 26. 제 2 절연층25. First Insulation Layer 26. Second Insulation Layer
26a. 완전 평탄화된 제 2 절연층 26b. 언더 폴리싱된 제 2 절연층26a. Fully planarized second insulating layer 26b. Underpolished Second Insulation Layer
26c. 오버 에치된 제 2 절연층 27. 포토레지스트26c. Over-etched Second Insulation Layer 27. Photoresist
28. 제 3 절연층 28a. 측벽 마스크층28. Third insulating layer 28a. Sidewall mask layer
29. 제 2 게이트 측벽 30. 소오스/드레인 영역29. Second gate sidewalls 30. Source / drain regions
31. 제 1 게이트 측벽 32. 살리사이드층31. First gate sidewall 32. Salicide layer
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은 반도체 기판상에 게이트 전극들을 형성하는 단계;상기 게이트 전극들의 양측 기판 표면내에 저농도 불순물 영역을 형성하고, 게이트 전극을 포함하는 전면에 제 1,2 절연층을 형성하고 게이트 전극들의 상부 표면 및 상단 측면 일부를 노출시키는 단계;선택적으로 게이트 전극들을 마스킹하고 노출된 게이트 전극들내에 게이트 이온 주입 공정을 진행하는 단계;상기 게이트 전극의 상단 측면에 측벽 마스크층을 형성하고 이를 마스크로 제 1,2 절연층을 제거하여 제 1,2 게이트 측벽을 형성한후 측벽 마스크층을 제거하는 단계;상기 게이트의 양측 기판 표면내에 소오스/드레인 영역을 형성하고 노출된 기판 표면 및 게이트 전극 상부 표면 및 상단 측면 일부에 살리사이드층을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: forming gate electrodes on a semiconductor substrate; forming a low concentration impurity region in a surface of both substrates of the gate electrodes, and forming a gate electrode on a front surface including the gate electrode; Forming a first and second insulating layers and exposing a portion of the top surface and the top side of the gate electrodes; optionally masking the gate electrodes and performing a gate ion implantation process in the exposed gate electrodes; top of the gate electrode Forming a sidewall mask layer on the side surface and removing the first and second gate sidewalls using a mask to form the first and second gate sidewalls, and then removing the sidewall mask layer; Forming a salicide layer on the exposed substrate surface and the gate electrode upper surface and a portion of the upper side. And in that it comprises the steps according to claim.
이하, 첨부된 도면을 참고하여 본 발명에 따른 반도체 소자의 제조 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a내지 도 2l은 본 발명에 따른 게이트 전극 형성을 위한 공정 단면도이다.2A to 2L are cross-sectional views of a process for forming a gate electrode according to the present invention.
본 발명은 게이트 살리사이드 공정을 진행하기 전에 게이트를 최대한 노출시킨후에 살리사이드 형성 공정을 진행하는 것이다.In the present invention, the salicide forming process is performed after exposing the gate as much as possible before proceeding with the gate salicide process.
본 발명은 고집적 CMOS 반도체 소자의 제조 공정시에 N+ 게이트의 프리 도핑에 의해 발생하는 NP 바이어스 및 액티브 데미지 문제를 해결하고, 게이트 실리사이드의 저항을 낮추고 열적 안정성을 높이기 위한 것이다.The present invention is to solve the NP bias and active damage caused by the pre-doping of the N + gate during the manufacturing process of the highly integrated CMOS semiconductor device, to lower the resistance of the gate silicide and to improve the thermal stability.
고집적 CMOS 반도체 소자의 제조에 있어서, 폴리 게이트 살리사이드(salicide)의 저항은 소자의 성능에 큰 영향을 준다.In the fabrication of highly integrated CMOS semiconductor devices, the resistance of poly gate salicides has a great effect on the performance of the devices.
따라서, 폴리 게이트 살리사이드 저항을 낮추기 위하여 많은 연구가 진행되고 있고, 특히 후속되는 열처리에 의한 열화를 막기 위한 연구가 많이 진행되고 있다.Accordingly, many studies have been conducted to lower the poly gate salicide resistance, and many studies have been conducted to prevent deterioration due to subsequent heat treatment.
먼저, 도 2a에서와 같이, 반도체 기판(21)에 소자 격리층(12)을 형성하여 서로 다른 도전형의 채널을 갖는 트랜지스터들의 형성 영역을 정의한다.First, as shown in FIG. 2A, the device isolation layer 12 is formed on the semiconductor substrate 21 to define regions in which transistors having channels of different conductivity types are formed.
이어, 전면에 게이트 형성용 물질층을 증착하고 포토리소그래피 공정으로 선택적으로 패터닝하여 게이트 전극(23a)(23b)들을 형성한다.Subsequently, a gate forming material layer is deposited on the entire surface and selectively patterned by a photolithography process to form gate electrodes 23a and 23b.
그리고 상기 게이트 전극(23a)(23b)을 마스크로 사용하여 LDD(Lightly Doped Drain) 이온 주입 공정을 진행하여 저농도 불순물 영역(24)을 형성한다.Lightly doped drain (LDD) ion implantation is performed using the gate electrodes 23a and 23b as a mask to form the low concentration impurity region 24.
이어, 도 2b에서와 같이, 상기 게이트 전극(23a)(23b)을 포함하는 전면에 HLD(High temperature Low pressure Deposition)산화막 또는 TEOS(Tetra-Ethyl-Ortho-Silicate)를 100 ~ 400Å의 두께로 증착하여 버퍼층 역할을 하는 제 1 절연층(25)을 형성한다.Subsequently, as shown in FIG. 2B, a high temperature low pressure deposition (HLD) oxide film or TEOS (Tetra-Ethyl-Ortho-Silicate) is deposited on the entire surface including the gate electrodes 23a and 23b to a thickness of 100 to 400 kPa. As a result, a first insulating layer 25 serving as a buffer layer is formed.
그리고 상기 제 1 절연층(25)상에 나이트라이드(nitride)를 2800 ~ 3200Å의 두께로 증착하여 제 2 절연층(26)을 형성한다.In addition, nitride is deposited on the first insulating layer 25 to a thickness of 2800 to 3200 Å to form a second insulating layer 26.
이어, 상기 제 2 절연층(26)을 CMP(Chemical Mechanical Polishing) 공정으로 평탄화하는데, 평탄화의 정도에 따라 두 가지의 경우가 있다.Subsequently, the second insulating layer 26 is planarized by a chemical mechanical polishing (CMP) process. There are two cases depending on the degree of planarization.
먼저, 도 2c에서와 같이, 게이트 전극(23a)(23b)의 상부 표면이 노출되도록 완전 평탄화된 제 2 절연층(26a)을 형성하는 방법과, 도 2d에서와 같이, 게이트 전극(23a)(23b)의 상부에 (가)부분에서와 같이 200 ~ 800Å의 두께의 제 2 절연층을 남겨 언더 폴리싱된 제 2 절연층(26b)을 형성하는 방법이 있다.First, as shown in FIG. 2C, a method of forming a second planarized insulating layer 26a so that the top surfaces of the gate electrodes 23a and 23b are exposed, and as shown in FIG. 2D, the gate electrode 23a ( There is a method of forming the underpolished second insulating layer 26b by leaving a second insulating layer having a thickness of 200 to 800 kPa as in (a) in the upper part of 23b).
이는 도 2c에서와 같이 완전 폴리싱을 하는 경우에는 게이트 전극(23a)(23b)의 상부 표면이 CMP 공정의 마진에 따라 손상될 우려가 있는 경우에는 도 2d에서와 같이 공정을 진행하고, CMP 공정이 안정화된 경우에는 도 2c에서와 같이 공정을 진행한다.In the case of complete polishing as shown in FIG. 2C, when the upper surfaces of the gate electrodes 23a and 23b may be damaged according to the margin of the CMP process, the process proceeds as shown in FIG. 2D. In the case of stabilization, the process proceeds as shown in FIG. 2C.
본 발명의 실시예에서는 도 2d에서와 같이 공정을 진행하는 것을 예로 설명한다.In the exemplary embodiment of the present invention, the process is performed as shown in FIG. 2D by way of example.
그리고 도 2e에서와 같이, 건식 식각 또는 습식 식각 공정으로 게이트 전극(23a)(23b)상부의 언더 폴리싱된 제 2 절연층(26b)을 제거하여 오버 에치된(게이트 상부 높이보다 더 낮은 상태의) 제 2 절연층(26c)을 형성하여 게이트 전극(13a)(13b)의 상부 표면을 노출시킨다.2E, the under-polished second insulating layer 26b over the gate electrodes 23a and 23b is removed by a dry etching or a wet etching process (below the gate upper height). A second insulating layer 26c is formed to expose the top surface of the gate electrodes 13a and 13b.
여기서, 오버 에치되는 두께는 50 ~ 500Å이다.(도 2e의 (나)부분)Here, the thickness to be over-etched is 50 to 500 mm (part (B) of Figure 2e).
이어, 도 2f에서와 같이, 전면에 포토레지스트(27)를 도포하고 선택적으로 패터닝하여 n형 불순물 이온이 주입될 부분만 오픈시킨후 n형의 불순물을 사용하여 게이트 이온 주입을 진행한다.Subsequently, as shown in FIG. 2F, the photoresist 27 is applied to the entire surface and selectively patterned to open only the portion where the n-type impurity ions are to be implanted, and then gate ion implantation is performed using the n-type impurity.
그리고 도 2g에서와 같이, 상기 포토레지스트(27)를 제거하고 전면에 600 ~ 800Å의 HLD(High temperature Low pressure Deposition) 산화막을 증착하여 제 3 절연층(28)을 형성한다.As shown in FIG. 2G, the photoresist 27 is removed and a third insulating layer 28 is formed by depositing a high temperature low pressure deposition (HLD) oxide film of 600 to 800 kPa on the entire surface.
이어, 도 2h에서와 같이, 이방성 식각 공정으로 상기 제 3 절연층(28)을 식각하여 오버 에치된 제 2 절연층(26c)의 리세스 부분의 게이트 전극(23a)(23b)의 측면에 측벽 마스크층(28a)을 형성한다.Subsequently, as shown in FIG. 2H, sidewalls of sidewalls of the gate electrodes 23a and 23b of the recessed portions of the second insulating layer 26c which are etched by the third insulating layer 28 by an anisotropic etching process are etched. The mask layer 28a is formed.
그리고 도 2i에서와 같이, 상기 측벽 마스크층(28a)을 마스크로 하여 노출된 오버 에치된 제 2 절연층(26c)을 제거하여 측벽 마스크층(28a)의 하측으로 게이트 전극(23a)(23b)의 양측에 위치하는 제 2 게이트 측벽(29)을 형성한다.As shown in FIG. 2I, the over-etched second insulating layer 26c exposed using the sidewall mask layer 28a as a mask is removed to remove the gate electrodes 23a and 23b below the sidewall mask layer 28a. The second gate sidewall 29 is formed at both sides of the second gate sidewall 29.
이어, 도 2j에서와 같이, 전면에 불순물 이온 주입 공정을 진행하여 게이트 전극(23a)(23b)의 양측 기판 표면내에 소오스/드레인 영역(30)을 형성한다.Next, as shown in FIG. 2J, an impurity ion implantation process is performed on the entire surface to form the source / drain regions 30 in both substrate surfaces of the gate electrodes 23a and 23b.
그리고 도 2k에서와 같이, 습식 또는 건식 식각 공정으로 측벽 마스크층(28a)을 제거한다.As shown in FIG. 2K, the sidewall mask layer 28a is removed by a wet or dry etching process.
이어, 도 2l에서와 같이, 전면에 실리사이드 형성용 금속층을 형성하고 열처리 공정으로 실리사이드 공정을 진행하여 게이트 전극(23a)(23b)의 상부 표면 및 상단 측면 일부 그리고 노출된 액티브 영역의 표면에 살리사이드층(32)을 형성한다.Subsequently, as shown in FIG. 2L, a silicide-forming metal layer is formed on the entire surface, and a silicide process is performed by a heat treatment process, so that the salicide is formed on the upper surface and a part of the upper surface of the gate electrodes 23a and 23b and the exposed active region. Layer 32 is formed.
이와 같은 본 발명은 게이트 전극의 살리사이드 형성 면적이 확대되는 것에 의해 살리사이드층의 저항을 낮출 수 있다.The present invention can reduce the resistance of the salicide layer by increasing the salicide formation area of the gate electrode.
또한, 본 발명은 게이트 패터닝후에 추가적인 이온 주입 공정을 진행하여 소오스/드레인 이온 주입 공정이 독립적으로 이루어지는데, 이와 같은 공정은 N 게이트 뿐만 아니라 P 게이트 제조 공정에도 적용될 수 있음은 당연하다.In addition, in the present invention, an additional ion implantation process is performed after the gate patterning, so that the source / drain ion implantation process is performed independently, and it is natural that such a process may be applied to not only the N gate but also the P gate manufacturing process.
이와 같은 본 발명에 따른 반도체 소자의 제조 방법은 다음과 같은 효과가 있다.Such a method of manufacturing a semiconductor device according to the present invention has the following effects.
본 발명은 살리사이드 공정을 진행하기 전에 게이트 전극의 노출 면적을 확대시켜 살리사이드층의 저항을 낮출 수 있고, 이는 후속되는 열공정시에 살리사이드 응집(Salicide agglomeration)을 억제하여 열적 안정성을 확보하는 효과가 있다.The present invention can reduce the resistance of the salicide layer by enlarging the exposed area of the gate electrode before proceeding to the salicide process, which is effective in securing thermal stability by inhibiting salicide agglomeration during subsequent thermal processes. There is.
또한, 본 발명은 게이트 패터닝후에 추가적인 이온 주입 공정을 진행하여 소오스/드레인 이온 주입 공정이 독립적으로 이루어질 수 있어 도핑 프로파일의 조절이 용이하다.In addition, according to the present invention, an additional ion implantation process may be performed after the gate patterning so that source / drain ion implantation processes may be independently performed, thereby easily adjusting the doping profile.
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