KR20030053201A - Method for forming conductor line in semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a conductive line of a semiconductor device is provided to define even a fine gate line, by performing a mask process using conventional development equipment, gate material and development technology, by forming polymer on a photoresist layer pattern after defining a photoresist layer and by performing an etch process using the polymer as a barrier after the photoresist layer is removed. CONSTITUTION: After a gate oxide layer(12) is formed on a semiconductor substrate(11), the first conductive material layer is formed on the resultant structure. After the first photoresist layer is deposited on the first conductive material layer, the first mask pattern is simultaneously formed in a cell region and a peri region. A predetermined thickness of the polymer is formed on both sidewalls of the first mask pattern in the cell region and the peri region. The second photoresist layer is deposited in the peri region except the cell region to form the second mask pattern. In the cell region, the first photoresist layer is removed and the polymer is left by using the second mask pattern as a barrier. In the peri region, the first mask pattern is left and only the second mask pattern is eliminated. The conductive material layer is etched to simultaneously form a gate line in the cell region and the peri region by using the polymer as a barrier in the cell region and by using the first mask pattern and the polymer as a barrier in the peri region.

Description

METHODS FOR FORMING CONDUCTOR LINE IN SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a conductive line of a semiconductor device, and more particularly, to a method of forming a conductive line of a semiconductor device capable of defining fine gate lines using photoresist film (P / R) and a polymer will be.

1A to 1D are cross-sectional views illustrating a conventional method of forming a gate electrode.

Referring to FIG. 1A, a well region and a field stop region are formed on the semiconductor substrate 2 on which the field oxide film 1 is formed, and ions are implanted to adjust the threshold voltage Vt (3). Next, a gate oxide film 4 having a predetermined thickness is formed on the resultant.

Referring to FIG. 1B, a buffer gate insulating layer, a polysilicon layer, and a hard mask layer are sequentially stacked on the gate oxide layer 4. Next, the hard mask layer is patterned in the form of a gate electrode, and then, in the form of the hard mask layer, the polysilicon layer and the buffer gate insulating film are patterned to form the gate 5.

Thereafter, in order to compensate for the damaged part during the etching process, oxidation is performed at a thickness of 50 mm 3 and then LDD (Lightly Doped Drain) ion implantation (6) is performed.

Referring to FIG. 1C, after the gate spacers are deposited on both sides of the gate 5 by a known method, an etching process is performed to form the first and second spacers 7 and 8.

Referring to FIG. 1D, an ion implantation process is performed on the semiconductor substrate 2 outside the first and second spacers 7 and 8 to form a source / drain 9. Next, an annealing process is performed to activate impurities, followed by a wet cleaning process before salicide deposition. At this time, under-cuts are generated in the edge region under the gate spacers 7 and 8.

Referring to FIG. 1E, after depositing a salicide 10 on the resultant, an annealing process is performed.

The conventional method for forming the gate line (poly 1) has relied on the development of photo equipment, the development of gate line materials, or the development of development techniques. Therefore, it has not been possible to form a gate line even finer than these limits, which has emerged as the most important problem in the development of the next generation high density device.

The formation of gate lines for equipment, materials, and development techniques can be difficult to follow, as well as increase the size of the product, resulting in lower production yields and lower competitiveness.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a method for forming a conductive line of a semiconductor device which can define fine gate lines using a photosensitive film (P / R) and a polymer. It is.

1A to 1E are cross-sectional views of a manufacturing process for explaining a conventional method of forming a gate electrode.

2A to 2F are cross-sectional views of a manufacturing process for explaining the gate line forming method according to the present invention.

(Explanation of symbols for the main parts of the drawing)

11: semiconductor substrate 12: gate oxide film

13: conductive electrode or gate electrode

14: first photosensitive film or first mask pattern

15: polymer

16: second photosensitive film or second mask pattern

The conductive line forming method of the semiconductor device of the present invention for achieving the above object,

Forming a gate oxide film on the semiconductor substrate and then forming a first conductive material layer thereon;

Depositing a first photoresist layer on the first conductive material layer to simultaneously form a first mask pattern for forming a conductive electrode in a cell region and a ferry region;

Forming a polymer with a predetermined thickness on both sidewalls of the first mask pattern formed in the cell region and the ferry region;

Forming a second mask pattern by depositing a second photoresist layer on the ferry region except for the cell region;

Removing the first photoresist film of the cell region using only the second mask pattern as a barrier and leaving only the polymer;

Removing only the second mask pattern leaving the first mask pattern of the ferry region;

Etching the conductive material layer by using the polymer as a barrier and the ferry region as the barrier and forming the gate line in the cell region and the ferry region at the same time. Characterized in that.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views of the manufacturing process for explaining the gate line forming method according to the present invention.

First, in the process illustrated in FIG. 2A, after the gate oxide film 12 is formed on the semiconductor substrate 11, the buffer gate insulating film 13a, the polysilicon layer 13b, and the hard mask layer may be formed on the gate oxide film 12. 13c) are sequentially stacked. Next, a first mask pattern 14 for forming a gate electrode by depositing a first photoresist layer on the hard mask layer 13c is simultaneously formed in the cell region A and the peri region B. One step.

Subsequently, in the process illustrated in FIG. 2B, the polymer 15 is generated on both sidewalls of the first mask pattern 14 formed in the cell region A and the Peri region B, thereby providing a predetermined thickness. It is a step formed by.

Subsequently, the process illustrated in FIG. 2C is a step of forming a second mask pattern 16 by depositing a second photosensitive film on the Peri region B except for the cell region A. FIG.

Subsequently, the process illustrated in FIG. 2D removes the first photosensitive film 15 between the polymers 15 of the cell region A by using the second mask pattern 16 as a barrier. It is a step.

Subsequently, the process illustrated in FIG. 2E is a step in which only the second mask pattern 16 is removed while leaving the first mask pattern 15 of the ferry region B.

Finally, in the process shown in FIG. 2F, in FIG. 2E, the cell region A is the polymer 15 as a barrier, and the ferry region B is the first mask pattern 15 and the polymer 14. ) To form a gate line in the cell region (A) and the ferry region (B) by etching as a barrier.

As described above, in the gate line forming method according to the present invention, the thickness of the polymer may be generated in the cell region A and the ferry region B of FIG. 2B to finely form a gate line having a desired thickness. .

In addition, the present invention can be similarly applied to the formation of bit lines (poly 2) as another embodiment.

After the gate line is formed, the planarization is performed with the IPO1 layer, and then a conductive layer to be a bit line (poly 2) layer is deposited. Next, as described above, the first mask pattern may be formed, the polymer may be generated, and the second bit pattern may be limited to a minute bit line above a limit using a second mask pattern.

In addition, the same applies to the formation of a metal 1 line.

In other words, a poly 4 layer is formed to form a capacitor, and then a planarization is performed on the IPO 3 layer, and then a conductive layer to be a metal 1 line layer is deposited. Next, as described above, the first mask pattern may be formed, the polymer may be generated, and then the fine metal 1 line having a limit or more may be limited as desired using the second mask pattern.

In addition, the same applies to the formation of a metal 2 line.

That is, a metal 1 line is formed, a planarization is formed using an IMO layer, and a conductive layer to be a metal 2 line layer is deposited. Next, as described above, the first mask pattern may be formed, the polymer may be generated, and the second metal pattern may be limited to the desired fine metal 2 line using the second mask pattern.

As described above, by forming the metal line of the semiconductor device using the first mask pattern, the polymer generation, and the second mask pattern, fine conductive lines beyond the limits of equipment, materials, and technology can be formed. As a result, sufficient process margin can be secured for subsequent processes, the process can be stabilized, and manufacturing costs can be lowered by using existing equipment as it is. Therefore, using the metal line forming method of the present invention can increase the competitiveness of the product.

As described in detail above, the method for forming a conductive line of a semiconductor device according to the present invention uses a conventional developing equipment, a gate material, and a developing technique to perform a mask operation and to define a photoresist film (P / R). By forming a polymer on the formed photoresist pattern and removing the photoresist, the polymer is etched with a barrier to form a final gate line, thereby forming even fine gate lines that are difficult to form patterns due to limitations of existing equipment, gate materials, and development techniques. It can work.

In addition, if the method of forming a conductive line according to the present invention is applied, first, the existing equipment may be used as it is, and the existing processes may be applied, thereby achieving stabilization without any problem in the process, and also, a conductor line. Can be finely defined at will without restriction of equipment or technology, so it is easier to design. In addition, sufficient process margins can be secured for subsequent processes, so there is no difficulty in stabilizing new processes or raising costs due to equipment purchase. This facilitates the process and increases the competitiveness of the product.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (1)

Forming a gate oxide film on the semiconductor substrate and then forming a first conductive material layer thereon; Depositing a first photoresist layer on the first conductive material layer to simultaneously form a first mask pattern for forming a conductive electrode in a cell region and a ferry region; Forming a polymer with a predetermined thickness on both sidewalls of the first mask pattern formed in the cell region and the ferry region; Forming a second mask pattern by depositing a second photoresist layer on the ferry region except for the cell region; Removing the first photoresist film of the cell region using only the second mask pattern as a barrier and leaving only the polymer; Removing only the second mask pattern leaving the first mask pattern of the ferry region; Etching the conductive material layer by using the polymer as a barrier and the ferry region as the barrier and forming the gate line in the cell region and the ferry region at the same time. A conductive line forming method of a semiconductor device, characterized in that.