KR20030050681A - Method for fabricating dual gate oxide - Google Patents
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- KR20030050681A KR20030050681A KR1020010081185A KR20010081185A KR20030050681A KR 20030050681 A KR20030050681 A KR 20030050681A KR 1020010081185 A KR1020010081185 A KR 1020010081185A KR 20010081185 A KR20010081185 A KR 20010081185A KR 20030050681 A KR20030050681 A KR 20030050681A
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 230000009977 dual effect Effects 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 230000003647 oxidation Effects 0.000 claims abstract description 31
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 31
- 150000002500 ions Chemical class 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 47
- 238000005468 ion implantation Methods 0.000 claims description 36
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 239000002019 doping agent Substances 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 38
- 229910052757 nitrogen Inorganic materials 0.000 description 18
- 230000002093 peripheral effect Effects 0.000 description 14
- 239000010410 layer Substances 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- -1 nitrogen ion Chemical class 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
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Abstract
Description
본 발명은 반도체장치의 제조 방법에 관한 것으로, 특히 듀얼 게이트산화막 (Dual gate oxide)의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a dual gate oxide film.
일반적으로 반도체장치의 게이트산화막으로 열(Thermally) 또는 급속열처리(Rapid thermally)에 의해 성장된 SiO2를 사용하고 있다. 최근에 반도체소자의 디자인룰이 감소함에 따라 게이트산화막의 두께는 SiO2의 터널링한계가 되는 25∼30Å이하로 줄어드는 추세에 있으며, 0.1㎛급 소자에서의 게이트산화막으로는 25∼30Å두께가 예상된다.In general, SiO 2 grown by thermally or rapid thermally is used as a gate oxide film of a semiconductor device. As the design rules of semiconductor devices decrease in recent years, the thickness of gate oxide films has tended to decrease below 25-30 kHz, which is the tunneling limit of SiO 2 , and a thickness of 25-30 kHz is expected as a gate oxide film in 0.1 占 퐉 devices. .
그러나, 셀트랜지스터(Cell transistor)의 경우 리프레쉬(refresh) 등의 문제로 인하여 주변회로영역(peri)의 트랜지스터보다 높은 문턱전압(threshold voltage; Vt)이 요구됨에 따라 높은 게이트 전압이 가해지고 결과적으로 주변회로영역의 트랜지스터보다는 전기적 특성이 열화되는 단점이 나타난다.However, in the case of a cell transistor, a higher gate voltage is applied as a higher threshold voltage (Vt) than a transistor in the peripheral circuit region (peri) due to a problem such as refreshing, resulting in a peripheral voltage. The disadvantage is that the electrical characteristics deteriorate rather than the transistors in the circuit area.
셀영역의 트랜지스터 특성을 향상시키기 위해서는 셀영역의 트랜지스터의 게이트산화막의 두께를 증가시킬 필요가 있는데 이를 위해 제안된 것이 CMOS 공정에 의한 듀얼 게이트산화막(Dual gate dielectric)의 제조 방법이다.In order to improve the transistor characteristics of the cell region, it is necessary to increase the thickness of the gate oxide layer of the transistor of the cell region. A proposed method for manufacturing the dual gate dielectric layer by a CMOS process is proposed.
이러한 듀얼 게이트산화막의 종래기술로는 여러 가지가 있는데 최근에 많이 연구되는 방법은 일정 부분만 게이트산화막을 제거하고 다시 산화시켜 듀얼 게이트산화막을 형성시키는 제1방법과 일정 부분만 질소(nitrogen)와 같은 원소를 이온주입(implant)하여 게이트산화막의 성장을 느리게 하여 듀얼 게이트산화막을 형성시키는 제2방법 등이 있다.There are a number of conventional techniques for such a dual gate oxide film. Recently, many researches have been made on the first method of forming a dual gate oxide film by removing only a portion of the gate oxide film and oxidizing it, and only a portion of nitrogen, such as nitrogen. And a second method of forming a dual gate oxide film by slowing the growth of the gate oxide film by implanting elements.
그러나, 상술한 종래기술 중 제1방법은 듀얼 게이트산화막을 형성시키기 위해 두 번의 높은 열공정을 실시하기 때문에 반도체기판의 표면이 손상되는 문제점이 있고, 제2방법은 질소, Si, Ge의 이온주입으로 인해 반도체기판이 손상되는 문제점이 있다.However, since the first method of the related art performs two high thermal processes to form a dual gate oxide film, the surface of the semiconductor substrate is damaged, and the second method is ion implantation of nitrogen, Si, and Ge. Due to this, there is a problem that the semiconductor substrate is damaged.
도 1a 내지 도 1b는 종래기술에 따른 듀얼 게이트산화막의 형성 방법을 도시한 공정 단면도이다.1A to 1B are cross-sectional views illustrating a method of forming a dual gate oxide film according to the prior art.
도 1a에 도시된 바와 같이, 반도체기판(11)에 소자간 격리를 위한 필드산화막(12)을 형성한 후, 반도체기판(11)상에 희생산화막(13)을 성장시킨다. 계속해서, 희생산화막(13)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 반도체기판(11)의 일측을 노출시키는 마스크(14)를 형성한다.As shown in FIG. 1A, after forming the field oxide film 12 for isolation between devices on the semiconductor substrate 11, the sacrificial oxide film 13 is grown on the semiconductor substrate 11. Subsequently, a photosensitive film is coated on the sacrificial oxide film 13 and patterned by exposure and development to form a mask 14 exposing one side of the semiconductor substrate 11.
다음으로, 마스크(14)에 의해 노출된 반도체기판(11)의 일측에 질소(N2)를 이온주입한다. 이 때, 질소는 반도체기판(11) 표면내의 실리콘에 포함되며, 희생산화막(13)은 질소의 이온주입시 반도체기판(11)이 손상받는 것을 방지하기 위한 막이다.Next, nitrogen (N 2 ) is ion implanted into one side of the semiconductor substrate 11 exposed by the mask 14. At this time, nitrogen is contained in silicon in the surface of the semiconductor substrate 11, and the sacrificial oxide film 13 is a film for preventing the semiconductor substrate 11 from being damaged when ion is injected into the nitrogen.
도 1b에 도시된 바와 같이, 마스크(14) 및 희생산화막(13)을 제거한 후, 게이트산화(gate oxidation) 공정을 실시하여 반도체기판(11)상에 서로 다른 두께를 갖는 제1,2게이트산화막(15a,15b)을 성장시킨다. 이 때, 질소의 이온주입이 이루어진 반도체기판(11)의 일측표면상에 성장되는 제1게이트산화막(15a)은 이온주입이 이루어지지 않은 타측 표면상에 성장되는 제2게이트산화막(15b)에 비해 상대적으로 그 두께가 얇다. 이상, 듀얼 게이트산화막이라 일컫는다.As shown in FIG. 1B, after the mask 14 and the sacrificial oxide film 13 are removed, a gate oxidation process is performed to form first and second gate oxide films having different thicknesses on the semiconductor substrate 11. (15a, 15b) is grown. At this time, the first gate oxide film 15a grown on one surface of the semiconductor substrate 11 where nitrogen is implanted is compared with the second gate oxide film 15b grown on the other surface where ion implantation is not performed. Relatively thin in thickness. This is referred to as a dual gate oxide film.
여기서, 두께가 두꺼운 제2게이트산화막(15b)은 셀영역에 포함되고, 제2게이트산화막(15b)보다 두께가 얇은 제1게이트산화막(15a)은 주변회로영역에 포함된다.Here, the thick second gate oxide film 15b is included in the cell region, and the first gate oxide film 15a thinner than the second gate oxide film 15b is included in the peripheral circuit region.
도 2a는 질소의 이온주입도즈량에 따른 두께 변화를 도시한 그래프로서, 두꺼운 제1게이트산화막(15a)이 67Å, 얇은 제2게이트산화막(15b)이 35Å인 타겟을 맞추기 위해서 질소(N2)의 도즈량에 따른 산화막 두께 변화(67Å 타겟 산화공정)를 실험한 결과이다.FIG. 2A is a graph showing a change in thickness according to the ion implantation dose of nitrogen. In order to target a target having a thick first gate oxide film 15a of 67 kPa and a thin second gate oxide film 15b of 35 kPa, nitrogen (N 2 ) is shown. This is the result of experiment of change of oxide thickness (67Å target oxidation process) according to the dose.
도 2a에 도시된 바와 같이, 약 10Å이상의 상이한 두께를 갖는 듀얼 게이트산화막 공정에서는 질소 이온주입의 도즈량이 약 5×E14cm-2이상이 되어야 하는 것을 보여주고 있다.As shown in FIG. 2A, the dual gate oxide film process having a different thickness of about 10 GPa or more shows that the dose of nitrogen ion implantation should be about 5 × E 14 cm −2 or more.
그러나, 이러한 과도한 도즈량은 게이트산화막의 신뢰성을 매우 저하시키는 문제점을 갖는다.However, such an excessive dose has a problem of significantly lowering the reliability of the gate oxide film.
도 2b는 질소의 이온주입도즈량에 따른 게이트산화막의 신뢰성(TDDB) 변화를 도시한 그래프이다.FIG. 2B is a graph showing the change in reliability (TDDB) of the gate oxide film according to the ion implantation dose of nitrogen.
도 2b에 도시된 것처럼, 일정한 스트레스하에서 각각의 질소 도즈량에 따른 신뢰성 실험결과 질소 도즈량이 약 5×E14cm-2이상에서는 산화막의 신뢰성이 급격히 열화됨을 알 수 있다. 즉, 10Å이상의 상이한 두께를 갖는 듀얼 게이트 산화막 제조에 있어서 질소 이온주입법에 의한 종래기술은 신뢰성이 나쁜 문제점이 있다.As shown in FIG. 2B, it can be seen that the reliability of the oxide film is rapidly deteriorated when the nitrogen dose is about 5 × E 14 cm −2 or more as a result of the reliability of the nitrogen dose under a certain stress. That is, the prior art by the nitrogen ion implantation method in the production of a dual gate oxide film having a different thickness of 10Å or more has a problem of poor reliability.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 높은 도즈량의 이온주입에 따른 신뢰성 열화를 방지하도록 하는데 적합한 듀얼 게이트산화막의 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and an object of the present invention is to provide a method of forming a dual gate oxide film suitable for preventing reliability deterioration due to high dose amount of ion implantation.
도 1a 내지 도 1b는 종래기술에 따른 듀얼 게이트산화막의 형성 방법을 도시한 공정 단면도,1A to 1B are cross-sectional views illustrating a method of forming a dual gate oxide film according to the prior art;
도 2a는 종래 질소의 이온주입도즈량에 따른 두께 변화를 도시한 그래프,Figure 2a is a graph showing the change in thickness according to the ion implantation dose of conventional nitrogen,
도 2b는 종래 질소의 이온주입도즈량에 따른 게이트산화막의 신뢰성 변화를 도시한 그래프,2b is a graph showing a change in reliability of a gate oxide film according to a conventional ion implantation dose of nitrogen;
도 3a 내지 도 3d는 본 발명의 실시예에 따른 듀얼게이트산화막의 형성 방법을 도시한 공정 단면도.3A to 3D are cross-sectional views illustrating a method of forming a dual gate oxide film according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 필드산화막21 semiconductor substrate 22 field oxide film
23 : 희생산화막 24 : 제1마스크23: sacrificial oxide film 24: the first mask
25 : 제1불순물이온주입층 26 : 제2마스크25: the first impurity ion implantation layer 26: the second mask
27 : 제2불순물이온주입층 28a, 28b : 제1,2 게이트산화막27: second impurity ion implantation layer 28a, 28b: first and second gate oxide films
상기 목적을 달성하기 위한 본 발명의 듀얼 게이트산화막의 형성 방법은 반도체기판상에 희생산화막을 형성하는 단계, 상기 반도체기판의 일측 표면에 산화속도감소용 제1불순물을 이온주입하는 단계, 상기 반도체기판의 타측 표면에 산화속도증가용 제2불순물을 이온주입하는 단계, 및 상기 반도체기판 표면을 산화시켜 서로 다른 두께를 갖는 게이트산화막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The method of forming a dual gate oxide film of the present invention for achieving the above object comprises the steps of forming a sacrificial oxide film on a semiconductor substrate, ion implanting a first impurity for reducing the oxidation rate on one surface of the semiconductor substrate, Ion implanting a second impurity for increasing the oxidation rate on the other surface, and oxidizing the surface of the semiconductor substrate to form a gate oxide film having different thicknesses.
또한, 본 발명의 듀얼 게이트산화막의 형성 방법은 반도체기판상에 희생산화막을 형성하는 단계, 상기 반도체기판의 일측 표면에 산화속도감소용 제1불순물을 이온주입하는 단계, 상기 반도체기판의 타측 표면에 산화속도증가용 제2불순물을 이온주입하는 단계, 상기 반도체기판을 열처리하는 단계, 및 상기 열처리된 반도체기판의 표면을 산화시켜 서로 다른 두께를 갖는 게이트산화막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In addition, the method of forming a dual gate oxide film of the present invention comprises the steps of forming a sacrificial oxide film on a semiconductor substrate, ion implantation of the first impurity for reducing the oxidation rate on one surface of the semiconductor substrate, the oxidation on the other surface of the semiconductor substrate Ion implanting a second impurity for increasing speed, heat treating the semiconductor substrate, and oxidizing a surface of the heat treated semiconductor substrate to form gate oxide films having different thicknesses. .
바람직하게, 상기 제2불순물은 O2, Si, Ge 및 Ar로 이루어진 그룹중에서 선택되고, 상기 제1불순물은 N2이며, 상기 제1 및 제2불순물은 각각 1×E13cm-2∼5×E14cm-2의 도즈량과 1keV∼20keV 의 이온주입에너지로 이온주입되는 것을 특징으로 한다.Preferably, the second impurity is O 2, Si, and Ge is selected from the group consisting of Ar, said first impurity is N 2, the first and second impurity is 1 × E 13 cm -2 ~5 each It is characterized by being implanted with a dose of XE 14 cm -2 and an ion implantation energy of 1 keV to 20 keV.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3d는 본 발명의 실시예에 따른 듀얼 게이트산화막을 구비한 반도체장치의 제조 방법을 도시한 공정 단면도이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual gate oxide film according to an embodiment of the present invention.
도 3a에 도시된 바와 같이, 셀영역(A)과 주변회로영역(B)이 정의된 반도체기판(21)의 소정 부분에 소자의 활성영역과 필드영역을 한정하고 셀영역(A)과 주변회로영역(B)을 격리시키는 필드산화막(22)을 형성한다. 이때, 필드산화막(22)은 반도체기판(21)을 소정 깊이로 식각하여 트렌치를 형성하고, 이 트렌치에 절연막을 채우므로써 형성된다. 한편, 필드산화막(22)을 STI(Shallow Trench Isolation) 방법으로 형성하는 것을 보였으나, LOCOS(Local Oxidation of Silicon) 방법으로도 형성할 수 있다.As shown in FIG. 3A, the active region and the field region of the device are defined in a predetermined portion of the semiconductor substrate 21 in which the cell region A and the peripheral circuit region B are defined, and the cell region A and the peripheral circuit are defined. A field oxide film 22 is formed to isolate the region B. At this time, the field oxide film 22 is formed by etching the semiconductor substrate 21 to a predetermined depth to form a trench, and filling the trench with an insulating film. On the other hand, although the field oxide film 22 has been shown to be formed by a shallow trench isolation (STI) method, it may also be formed by a local oxide of silicon (LOCOS) method.
계속해서, 반도체기판(21)의 활성영역상에 희생산화막(23)을 20Å∼500Å 두께로 성장시킨 후, 희생산화막(23)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 반도체기판(21)의 주변회로영역(B)을 노출시키는 제1마스크(24)를 형성한다.Subsequently, the sacrificial oxide film 23 is grown to a thickness of 20 kV to 500 kPa on the active region of the semiconductor substrate 21, and then the photosensitive film is coated on the sacrificial oxide film 23, and patterned by exposure and development to form the semiconductor substrate 21. A first mask 24 is formed to expose the peripheral circuit region B of the substrate.
여기서, 희생산화막(23)은 후속 질소 이온주입으로 반도체기판(21)이 손상받는 것을 방지하기 위한 막으로서, 희생산화막(23)의 두께를 20Å 미만으로 하면 후속 이온주입에 의해 반도체기판(21) 표면이 손상받는 문제가 있고, 두께가 500Å보다 두꺼우면 후속 이온주입시 불순물들이 반도체기판(21)으로 확산불가능한 문제가 있으므로 바람직하게 희생산화막(23)의 두께는 20Å∼500Å를 유지한다.Here, the sacrificial oxide film 23 is a film for preventing the semiconductor substrate 21 from being damaged by subsequent nitrogen ion implantation. When the thickness of the sacrificial oxide film 23 is less than 20 GPa, the semiconductor substrate 21 is formed by subsequent ion implantation. If the surface is damaged and the thickness is larger than 500 GPa, since the impurities cannot be diffused into the semiconductor substrate 21 during subsequent ion implantation, the sacrificial oxide film 23 preferably maintains the thickness of 20 GPa to 500 GPa.
다음으로, 제1마스크(24)에 의해 노출된 반도체기판(21)의 주변회로영역(B)에 산화속도감소용 제1불순물(I1)을 이온주입하는데, 이러한 산화속도감소용 제1불순물(I1)로는 질소(N2)를 이용한다. 이때, 질소의 도즈량은 1×E13cm-2∼5×E14cm-2로 하고, 이온주입에너지는 1keV∼20keV 범위이다.Next, the first impurity (I 1 ) for reducing the oxidation rate is ion-implanted into the peripheral circuit region (B) of the semiconductor substrate 21 exposed by the first mask (24). 1 ) nitrogen (N 2 ) is used. At this time, the dose of nitrogen is 1 × E 13 cm −2 to 5 × E 14 cm −2 , and the ion implantation energy is in the range of 1 keV to 20 keV.
전술한 질소와 같은 제1불순물(I1)의 이온주입을 통해 반도체기판(21)의 주변회로영역(B) 표면내에 소정 깊이분포를 갖는 제1불순물이온주입층(25)이 형성된다.The first impurity ion implantation layer 25 having a predetermined depth distribution is formed in the peripheral circuit region B surface of the semiconductor substrate 21 through the ion implantation of the first impurity I 1 such as nitrogen.
도 3b에 도시된 바와 같이, 제1마스크(24)를 제거한 후, 전면에 감광막을 다시 도포하고 노광 및 현상으로 패터닝하여 반도체기판(21)의 셀영역(A)을 노출시키는 제2마스크(26)를 형성한다.As shown in FIG. 3B, after removing the first mask 24, the second mask 26 exposing the cell region A of the semiconductor substrate 21 by applying a photoresist film on the entire surface and patterning the photoresist film and exposure and development. ).
다음으로, 제2마스크(26)에 의해 노출된 반도체기판(21)의 셀영역(A)에 산화 속도를 증가시킬 목적으로 제2불순물(I2)을 이온주입하는데, 이러한 산화속도 증가용 제2불순물(I2)로는 O2, Si, Ge, Ar를 이용한다. 여기서, Si, Ge의 소스는 SiH4, SiF4, GeH4, GeF4이며, 이들 제2불순물(I2)들의 도즈량은 1×E13cm-2∼5×E14cm-2로 하고, 이온주입에너지는 1keV∼20keV 범위이다.Next, the second impurity (I 2 ) is ion implanted into the cell region A of the semiconductor substrate 21 exposed by the second mask 26 to increase the oxidation rate. As the impurity (I 2 ), O 2 , Si, Ge, Ar is used. Here, the source of Si and Ge is SiH 4 , SiF 4 , GeH 4 , GeF 4 , and the dose of these second impurities (I 2 ) is 1 × E 13 cm −2 to 5 × E 14 cm −2 . The ion implantation energy ranges from 1 keV to 20 keV.
전술한 제2불순물(I2)의 이온주입을 통해 반도체기판(21)의 셀영역(A) 표면내에 소정 깊이분포를 갖는 제2불순물이온주입층(27)이 형성된다.The second impurity ion implantation layer 27 having a predetermined depth distribution is formed in the surface of the cell region A of the semiconductor substrate 21 through the ion implantation of the second impurity I 2 described above.
도 3c에 도시된 바와 같이, 제2마스크(26)을 제거한 후, 열처리공정(500℃∼1100℃)을 실시하여 제1 및 제2불순물들(I1,I2)의 이온주입에 의해 입은 반도체기판(21)의 손상을 제거한다. 이러한 열공정은 생략할수 도 있다.As shown in FIG. 3C, after the second mask 26 is removed, heat treatment is performed by ion implantation of the first and second impurities I 1 and I 2 by performing a heat treatment process (500 ° C. to 1100 ° C.). The damage of the semiconductor substrate 21 is removed. This thermal process may be omitted.
계속해서, 희생산화막(23)을 희석된 HF 및 SC1 용액을 이용하여 제거한 후, 동일한 조건하에서 반도체기판(21)을 게이트산화시켜 셀영역(A)에 두꺼운 제1게이트산화막(28a)을 성장시키고, 주변회로영역(B)에 제1게이트산화막(28a)에 비해 상대적으로 두께가 얇은 제2게이트산화막(28b)을 성장시킨다.Subsequently, after the sacrificial oxide film 23 is removed using dilute HF and SC1 solutions, the semiconductor substrate 21 is gate-oxidized under the same conditions to grow a thick first gate oxide film 28a in the cell region A. In the peripheral circuit region B, a second gate oxide film 28b having a relatively smaller thickness than that of the first gate oxide film 28a is grown.
이 때, 제1,2불순물이온주입층(25,27)내 불순물들은 제1,2 게이트산화막(28a,28b) 성장시 그 고유한 작용(산화속도증가, 산화속도감소)을 하면서 소모된다.At this time, impurities in the first and second impurity ion implantation layers 25 and 27 are consumed as they grow in the first and second gate oxide films 28a and 28b (increase in oxidation rate and decrease in oxidation rate).
이와 같이, 서로 다른 두께로 제1,2 게이트산화막(28a,28b)이 성장되는 이유는, 산화속도감소용 불순물(I1)이 주입된 제1불순물이온주입층(25)상에서는 게이트산화시 산화속도가 감소하여 산화막 성장이 억제되고, 산화속도증가용 불순물(I2)이주입된 제2불순물이온주입층(27)상에서는 게이트산화시 산화속도가 증가하여 제1불순물이온주입층(25)상에 비해 상대적으로 산화막 성장이 빠르기 때문이다.As such, the reason why the first and second gate oxide films 28a and 28b are grown at different thicknesses is that the oxidation rate at the time of gate oxidation on the first impurity ion implantation layer 25 into which the impurity (I 1 ) for reducing oxidation rate is implanted. The oxide film growth is suppressed and the oxidation rate is increased on the second impurity ion implantation layer 27 containing the impurity (I 2 ) for increasing the oxidation rate. This is because oxide film growth is relatively fast.
도 3d에 도시된 바와 같이, 제1,2게이트산화막(28a,28b)상에 폴리실리콘(29), 텅스텐(30)을 차례로 증착한 후, 텅스텐(30)상에 게이트패터닝을 위한 감광막패턴(도시 생략)을 형성한다. 계속해서, 감광막패턴을 식각마스크로 텅스텐(29)과 폴리실리콘(30)을 차례로 식각하여 셀영역(A)과 주변회로영역(B)상에 각각 폴리실리콘/텅스텐(29/30)의 순서로 적층된 이중 구조를 갖는 게이트전극을 형성한다.As shown in FIG. 3D, the polysilicon 29 and the tungsten 30 are sequentially deposited on the first and second gate oxide films 28a and 28b, and then the photoresist pattern for gate patterning on the tungsten 30 is formed. (Not shown). Subsequently, tungsten (29) and polysilicon (30) are sequentially etched using the photoresist pattern as an etch mask, and then in the order of polysilicon / tungsten (29/30) on the cell region (A) and the peripheral circuit region (B), respectively. A gate electrode having a stacked double structure is formed.
여기서, 게이트전극은 폴리실리콘의 단독구조, 폴리실리콘/실리사이드(W-silicide, Ti-silicide, Ni-silicide)의 이중구조, 폴리실리콘/금속(W/WN, W/TiN, W/TiAlN)의 이중구조, 금속(W/WN, W/TiN, W/TiAlN, W/TaN, W/WC)의 단독구조도 적용 가능하다.Here, the gate electrode may be formed of a single structure of polysilicon, a double structure of polysilicon / silicide (W-silicide, Ti-silicide, Ni-silicide), and polysilicon / metal (W / WN, W / TiN, W / TiAlN). It is also possible to apply a dual structure and a single structure of metal (W / WN, W / TiN, W / TiAlN, W / TaN, W / WC).
다음으로, LDD 영역(31)을 형성하기 위한 저농도 불순물 이온주입을 하고, 게이트전극의 양측벽에 접하는 스페이서(32)를 형성한 후 소스/드레인영역(33)을 형성하기 위한 고농도 불순물 이온주입을 실시하여 CMOS 트랜지스터를 형성한다.Next, a low concentration of impurity ions are implanted to form the LDD region 31, a spacer 32 is formed in contact with both side walls of the gate electrode, and a high concentration of impurity ions is implanted to form the source / drain region 33. To form a CMOS transistor.
도면에 도시되지 않았지만, 각각의 트랜지스터들을 절연시켜주기 위한 층간절연막을 형성하고, 소스, 드레인 및 게이트전극을 외부단자와 연결시켜주기 위한 금속화 공정을 실시한다.Although not shown in the drawings, an interlayer insulating film is formed to insulate each transistor, and a metallization process is performed to connect the source, drain, and gate electrodes to external terminals.
상술한 실시예에서는 주변회로영역(B)에 먼저 산화속도감소용 불순물을 이온주입하고 셀영역(A)에 산화속도증가용 불순물을 이온주입하였으나, 불순물 이온주입공정은 그 순서를 바꿔서 실시하여도 동일한 효과를 구현할 수 있다.In the above-described embodiment, ion-implanted impurities for reducing the oxidation rate are first implanted into the peripheral circuit region B and ion-implanted impurities for increasing the oxidation rate into the cell region A. However, the impurity ion implantation process may be performed in a different order. You can implement the effect.
위에서 살펴본 바와 같이, 서로 상이한 산화속도를 갖도록 얇은 산화막이 형성될 부분에는 질소이온주입을 두꺼운 산화막이 형성될 부분에는 O2, Si, Ge, Ar 등을 이온주입하는 더블(double) 이온주입을 실시하므로써, 각각의 두께 차이가 크더라도 낮은 도즈량의 이온주입 공정을 적용할 수 있다.As described above, double ion implantation is performed to inject nitrogen ion into a portion where a thin oxide film is to be formed so as to have a different oxidation rate, and ion implantation of O 2 , Si, Ge, Ar, etc. into a portion where a thick oxide film is to be formed. Thus, a low dose amount ion implantation process can be applied even if the thickness difference is large.
따라서, 두께 차이가 크게 나는 듀얼 게이트산화막일지라도 낮은 도즈량의 이온주입이 가능하므로 듀얼 게이트산화막의 신뢰성 열화를 방지하고, 또한 상이한 두께 차이가 크더라도 쉽게 목적하는 듀얼 게이트산화막의 두께를 맞출 수 있다.Therefore, even a dual gate oxide film having a large difference in thickness can be implanted with a low dose, thereby preventing deterioration of reliability of the dual gate oxide film, and easily matching the desired thickness of the dual gate oxide film even with a large difference in thickness.
상술한 실시예에서는 소자의 동작속도보다는 누설전류 및 신뢰성이 중요시되는 셀영역(A)에는 산화속도를 증가시키는 불순물을 이온주입하고, 소자의 동작속도가 중요시되는 주변회로영역(B)에는 산화속도를 감소시키는 불순물을 이온주입하여 듀얼 게이트산화막을 성장시켰으나, 본 발명은 임베디드형(embedded type)의 메모리소자(DRAM, SRAM, FLASH)와 로직소자를 결합한 시스템온칩(System On Chip;SOC)과 같은 소자에서 로직소자영역과 메모리소자의 주변회로영역에서는 얇은게이트산화막을 형성하고, 메모리소자의 셀영역에서는 두꺼운 게이트산화막을 형성하는 방법에도 적용 가능하다.In the above-described embodiment, impurities are implanted to increase the oxidation rate in the cell region A, where leakage current and reliability are more important than the operation speed of the device, and the oxidation rate in the peripheral circuit area B, where the operation speed of the device is important. The dual gate oxide film was grown by implanting impurities that reduce the amount of impurities, but the present invention provides a system on chip (SOC) that combines embedded memory devices (DRAM, SRAM, FLASH) and logic devices. In the device, a thin gate oxide film is formed in a logic device region and a peripheral circuit region of a memory device, and a thick gate oxide film is formed in a cell region of a memory device.
즉, 로직소자영역과 주변회로영역에는 낮은 도즈량으로 산화속도를 감소시키는 불순물을 이온주입하고, 메모리소자의 셀영역에는 낮은 도즈량으로 산화속도를 증가시키는 불순물을 이온주입하여 서로 다른 두께를 갖는 듀얼 게이트산화막을 성장시킨다.That is, ion implantation of impurities that reduce the oxidation rate with a low dose amount in the logic element region and the peripheral circuit region, and ion implantation of impurities that increase the oxidation rate with a low dose amount in the cell region of the memory device have different thicknesses. The dual gate oxide film is grown.
이상에서 설명한 바와 같이 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.
상술한 본 발명은 낮은 도즈량으로 산화속도감소용 불순물과 산화속도증가용 불순물의 이온주입공정을 적용할 수 있으므로, 듀얼 게이트산화막의 신뢰성을 개선시킬 수 있는 효과가 있다.The present invention described above can apply the ion implantation process of the oxidation rate reducing impurity and the oxidation rate increasing impurity at a low dose amount, thereby improving the reliability of the dual gate oxide film.
또한, 더블 이온주입공정을 실시하므로써 두께 차이가 크더라도 듀얼 게이트산화막의 목적하는 두께를 맞출 수 있는 효과가 있다.In addition, by performing the double ion implantation process, even if the thickness difference is large, there is an effect of matching the desired thickness of the dual gate oxide film.
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