KR100723001B1 - Method for fabricating the same of semiconductor device with dual poly gate - Google Patents

Method for fabricating the same of semiconductor device with dual poly gate Download PDF

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KR100723001B1
KR100723001B1 KR1020060060393A KR20060060393A KR100723001B1 KR 100723001 B1 KR100723001 B1 KR 100723001B1 KR 1020060060393 A KR1020060060393 A KR 1020060060393A KR 20060060393 A KR20060060393 A KR 20060060393A KR 100723001 B1 KR100723001 B1 KR 100723001B1
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type polysilicon
polysilicon layer
type
protective layer
semiconductor device
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Korean (ko)
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양홍선
김용수
조흥재
임관용
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Abstract

본 발명은 플라즈마도핑공정에 의한 감광막의 경화에 의한 잔류물 또는 언스트립과 도펀트손실을 방지할 수 있는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법을 제공하기 위한 것으로, 본 발명은 NMOS와 PMOS가 정의된 반도체 기판 상에 게이트절연막을 형성하는 단계, 상기 게이트절연막 상에 N형 폴리실리콘층을 형성하는 단계, 상기 N형 폴리실리콘층의 표면에 P형 불순물을 도핑하여 P형 폴리실리콘층으로 바꾸는 단계, 상기 PMOS의 P형 폴리실리콘층 상에 보호층을 형성하는 단계, 상기 오픈된 NMOS의 P형 폴리실리콘층의 표면에 도핑된 P형 불순물을 제거하여 N형 폴리실리콘층으로 바꾸는 단계, 상기 PMOS의 보호층을 제거하는 단계를 포함하고, 상기한 본 발명은 플라즈마도핑공정을 통한 듀얼폴리게이트 형성시 감광막의 경화에 의한 잔류물 또는 언스트립과 도펀트손실을 방지함과 동시에 공정마진을 확보할 수 있는 효과가 있다.The present invention is to provide a method for manufacturing a semiconductor device having a dual poly gate capable of preventing residue or unstrip and dopant loss due to curing of the photosensitive film by the plasma doping process, the present invention is defined by NMOS and PMOS Forming a gate insulating film on the semiconductor substrate, forming an N-type polysilicon layer on the gate insulating film, and doping a P-type impurity on the surface of the N-type polysilicon layer to form a P-type polysilicon layer Forming a protective layer on the P-type polysilicon layer of the PMOS, removing the P-type impurities doped on the surface of the P-type polysilicon layer of the open NMOS, and converting the P-type impurities into an N-type polysilicon layer; Removing the protective layer of the present invention, wherein the present invention is a residue or frozen due to curing of the photosensitive film during the formation of the dual polygate through the plasma doping process There is an effect that can be and at the same time prevent trip and dopant loss securing process margins.

플라즈마도핑, 듀얼폴리게이트, 보론손실 Plasma Doping, Dual Polygate, Boron Loss

Description

듀얼폴리게이트를 갖는 반도체 소자의 제조방법{METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE WITH DUAL POLY GATE}Method for manufacturing a semiconductor device having a dual poly gate {METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE WITH DUAL POLY GATE}

도 1은 플라즈마도핑방법을 이용한 이온주입의 깊이에 따른 보론의 농도를 나타내는 그래프,1 is a graph showing the concentration of boron according to the depth of ion implantation using the plasma doping method,

도 2a 내지 도 2g는 본 발명의 바람직한 실시예에 따른 듀얼폴리게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도,2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a preferred embodiment of the present invention;

도 3은 보론도핑에 의한 NMOS의 C-V특성의 변화를 나타내는 그래프.3 is a graph showing a change in the C-V characteristics of the NMOS by boron doping.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

11 : 반도체 기판 12 : 소자분리막11 semiconductor substrate 12 device isolation film

13 : 리세스패턴 14 : 게이트절연막13 recess pattern 14 gate insulating film

15B : P형 폴리실리콘전극 15B : N형 폴리실리콘전극15B: P-type polysilicon electrode 15B: N-type polysilicon electrode

16 : 보호층 17 : 감광막패턴16: protective layer 17: photosensitive film pattern

본 발명은 반도체 제조 기술에 관한 것으로, 특히 듀얼폴리게이트를 갖는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a semiconductor device having a dual polygate.

반도체 소자의 고집적화에 따라 고성능(High Performance) 트랜지스터를 구현하기 위해 듀얼폴리게이트를 형성하는 기술이 제안되었다. In accordance with the high integration of semiconductor devices, a technique for forming a dual poly gate has been proposed to implement a high performance transistor.

한편, 100nm이하의 디자인 룰(Design Rule)을 갖는 디램(DRAM)에서 리프레시(Refresh)특성을 확보하기 위해 플라나게이트(Planar Gate) 대신 셀영역의 반도체 기판을 일정깊이로 식각하여 채널길이(Channel Length)를 늘리는 리세스게이트(Recess Gate)공정이 진행되고 있다. Meanwhile, in order to secure refresh characteristics in a DRAM having a design rule of 100 nm or less, a channel length is etched by etching a semiconductor substrate in a cell region at a predetermined depth instead of a planar gate. Recess Gate (Recess Gate) process to increase the () is in progress.

그러나, 리세스게이트공정이 적용되면서 셀영역과 N형과 P형게이트가 있는 주변영역의 트랜지스터를 동시에 형성하기가 어려워졌다. 따라서, 인(Phosphorous)이 도핑된 N형 폴리실리콘을 리세스패턴이 형성된 셀영역 및 주변영역까지 동시에 형성한 후, 주변영역의 PMOS지역에 카운터도핑(Counter Doping)의 개념으로 보론(Boron)을 추가도핑하여 P형 폴리실리콘으로 바꾸는 기술이 진행되고 있다.However, as the recess gate process is applied, it is difficult to simultaneously form transistors in the cell region and in the peripheral region having the N-type and P-type gates. Therefore, N-type polysilicon doped with phosphorous is formed simultaneously to the cell region and the peripheral region where the recess pattern is formed, and then boron is used as a concept of counter doping in the PMOS region of the peripheral region. The technology of changing to P-type polysilicon by further doping is progressing.

그러나, 카운터도핑의 경우 높은 도즈의 보론을 이온주입(Implantation)하는 경우 사용되는 도즈는 1.5E16/㎠이상이 요구되지만 8㎃의 전류(Current), 웨이퍼 25장 조건에서 150분이상의 시간이 소요되어 양산성 측면에 취약점을 가지고 있다.However, in the case of counter doping, the dose used when implanting boron of high dose requires 1.5E16 / cm2 or more, but it takes 150 minutes or longer at 8mA current and 25 wafers. It has a weak point in mass productivity.

카운터도핑의 양산성(Throughpur) 개선을 위해 플라즈마도핑(Plasma Doping)방법이 제안되었다. 플라즈마도핑방법의 경우 카운터도핑과 같은 도즈 또는 도즈의 양에 관계없이 웨이퍼 25장의 조건에서 30분의 시간이 소요되어 양산성개선에 큰 효과가 있다.Plasma Doping has been proposed to improve the throughput of counter doping. In the case of plasma doping, 30 minutes is required under the conditions of 25 wafers regardless of the dose or the amount of dose such as counter-doping, thereby greatly improving productivity.

도 1은 플라즈마도핑방법을 이용한 이온주입의 깊이에 따른 보론의 농도를 나타내는 그래프이다.1 is a graph showing the concentration of boron according to the depth of ion implantation using the plasma doping method.

도 1에 도시된 바와 같이, 플라즈마도핑방법을 이용하여 이온주입을 실시할 경우 깊이(Depth)에 따른 보론의 농도는 표면에서 가까운 깊이 즉, 표면으로부터 400Å까지는 보론의 농도가 1E22로 비슷하지만 400Å∼600Å으로 가면서 급격이 농도가 떨어지고 600Å이상이 되면 보론의 농도가 1E17로 400Å까지 보론의 농도가 1E22인 것에 비하여 현저한 차이를 나타내는 것을 알 수 있다.As shown in FIG. 1, when ion implantation is performed using the plasma doping method, the concentration of boron according to the depth is close to the surface, that is, the concentration of boron is similar to 1E22 from 400 kPa to 400 kPa from the surface. If the concentration suddenly drops to 600 고 and it exceeds 600 Å, the concentration of boron is 1E17 and 400 Å, which shows a significant difference compared to the concentration of boron 1E22.

즉, 플라즈마도핑방법의 경우 이온주입방식과 달리 폴리실리콘(Poly Silicon)의 표면에만 도펀트(Dopant)들이 집중하기 때문에 후속 공정에 의해 도펀트의 손실이 발생하여, 이를 보상하기 위해서는 추가 도즈가 필요하다. 또한, 플라즈마도핑에서 마스크로 사용되는 감광막이 높은 도즈의 도펀트들에 의해 경화(Hardening)되어 감광막의 잔류물(Residue) 또는 스트립되지 않는 언스트립(Unstrip)이 발생하는 문제점이 있다.That is, in the case of the plasma doping method, unlike the ion implantation method, the dopants are concentrated only on the surface of the polysilicon, so that the dopant is lost by the subsequent process, and additional dose is necessary to compensate for this. In addition, there is a problem in that the photoresist used as a mask in plasma doping is hardened by high dose dopants to cause residue or unstrip of the photoresist.

감광막의 잔류물 또는 언스트립의 문제를 해결하기 위해 감광막 스트립공정 전에 고온의 탈이온수 또는 오존처리를 통해 감광막의 표면을 전처리 한 후 감광막을 스트립하면 감광막이 쉽게 스트립이 된다. 그러나, 감광막의 스트립과 동시에 드러난 폴리실리콘의 표면에 있던 보론의 손실이 커져서 P형 폴리실리콘이 N형 폴리실리콘으로 바뀔만큼 감광막스트립 후속 공정에 의한 도펀트 손실(Dopant loss)이 많이 일어나는 문제점이 있다.In order to solve the problem of the residue or unstrip of the photoresist film, if the surface of the photoresist film is pretreated by hot deionized water or ozone treatment before the photoresist strip process, the photoresist film is easily stripped. However, the loss of boron on the surface of the polysilicon at the same time as the strip of the photoresist film is increased so that the P-type polysilicon is changed to the N-type polysilicon so that the dopant loss due to the subsequent photoresist strip strip process occurs.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 플라즈마도핑공정에 의한 감광막의 경화에 의한 잔류물 또는 언스트립과 도펀트손실을 방지할 수 있는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and a method of manufacturing a semiconductor device having a dual polygate capable of preventing residue or unstrip and dopant loss due to curing of the photosensitive film by the plasma doping process. The purpose is to provide.

본 발명에 의한 듀얼폴리게이트를 갖는 반도체 소자의 제조방법은 NMOS와 PMOS가 정의된 반도체 기판 상에 게이트절연막을 형성하는 단계, 상기 게이트절연막 상에 N형 폴리실리콘층을 형성하는 단계, 상기 N형 폴리실리콘층의 표면에 P형 불순물을 도핑하여 P형 폴리실리콘층으로 바꾸는 단계, 상기 PMOS의 P형 폴리실리콘층 상에 보호층을 형성하는 단계, 상기 오픈된 NMOS의 P형 폴리실리콘층의 표면에 도핑된 P형 불순물을 제거하여 N형 폴리실리콘층으로 바꾸는 단계, 상기 PMOS의 보호층을 제거하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor device having a dual poly gate according to the present invention includes forming a gate insulating film on a semiconductor substrate on which NMOS and PMOS are defined, forming an N-type polysilicon layer on the gate insulating film, and the N-type. Converting the surface of the polysilicon layer into a P-type polysilicon layer by doping a P-type impurity, forming a protective layer on the P-type polysilicon layer of the PMOS, the surface of the P-type polysilicon layer of the open NMOS Removing the P-type impurities doped into the N-type polysilicon layer, and removing the protective layer of the PMOS.

특히, 보호층은 산화막, 비정질카본막 또는 산화막과 비정질카본막의 적층구조 중에서 어느 하나로 형성하되, 산화막은 80℃∼300℃의 저온에서 화학기상증착법으로 형성하고, 100Å∼1000Å의 두께로 형성한다.In particular, the protective layer is formed of any one of an oxide film, an amorphous carbon film, or a laminated structure of an oxide film and an amorphous carbon film. The oxide film is formed by a chemical vapor deposition method at a low temperature of 80 ° C to 300 ° C and is formed to a thickness of 100 kPa to 1000 kPa.

또한, 오픈된 NMOS의 P형 폴리실리콘층의 표면에 도핑된 P형 불순물을 제거하는 단계는 60℃∼100℃의 고온에서 SC-1공정으로 50Å∼100Å의 폴리실리콘을 식 각하거나, 60℃∼100℃의 고온탈이온수, 플라즈마 O2 및 불산처리로 50Å∼100Å의 폴리실리콘을 식각한다.In addition, the step of removing the P-type impurities doped on the surface of the P-type polysilicon layer of the open NMOS is etched 50 ~ 100Å polysilicon by the SC-1 process at 60 ℃ ~ 100 ℃, or 60 ℃ The polysilicon of 50 kPa to 100 kPa is etched by high temperature deionized water at -100 ° C, plasma O 2 and hydrofluoric acid treatment.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2g는 본 발명의 바람직한 실시에에 따른 듀얼폴리게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device having a dual poly gate according to a preferred embodiment of the present invention.

도 2a에 도시된 바와 같이, 셀영역과 주변영역이 정의되고 주변영역은 NMOS와 PMOS가 정의된 반도체 기판(11)의 셀영역에 소자분리막(12)을 형성한다. 여기서, 소자분리막(12)은 활성영역을 정의하기 위한 것으로 STI공정을 통해 형성한다.As shown in FIG. 2A, the device isolation layer 12 is formed in the cell region of the semiconductor substrate 11 in which the cell region and the peripheral region are defined and the NMOS and the PMOS are defined. In this case, the device isolation layer 12 is formed to define an active region through an STI process.

이어서, 셀영역의 반도체 기판(11)을 국부적으로 소정식각하여 리세스패턴(13)을 형성한다. 여기서, 리세스패턴(13)은 채널길이(Channel Length)를 증가시키기 위한 것으로, 소자분리막(12)보다 깊지 않게 형성한다.Next, the recess pattern 13 is formed by locally etching the semiconductor substrate 11 in the cell region. Here, the recess pattern 13 is for increasing the channel length, and is not formed deeper than the device isolation layer 12.

이어서, 리세스패턴(13)을 포함하는 반도체 기판(11)의 전면에 게이트절연막(14)을 형성한다. 여기서, 게이트절연막(14)은 후속 게이트패턴과 채널간의 절연을 위한 것으로, SiON(Silicon Oxynitride), SiN(Silicon Nitride), 금속산화물 또는 금속실리케이트 중에서 선택된 어느 하나의 절연성물질로 형성한다.Subsequently, a gate insulating film 14 is formed on the entire surface of the semiconductor substrate 11 including the recess pattern 13. Here, the gate insulating layer 14 is for insulation between the subsequent gate pattern and the channel, and is formed of any one insulating material selected from silicon oxide (SiON), silicon nitride (SiN), metal oxide, or metal silicate.

이어서, 게이트절연막(14) 상에 리세스패턴(13)을 모두 매립하면서 반도체 기판(11) 상부로 일정높이를 갖도록 인(Phousphorous)이 도핑된 N형 폴리실리콘층(15)을 형성한다. 여기서, N형 폴리실리콘층(15)은 인이 적어도 2×1021/㎠이상의 농도로 도핑되도록 형성하고, 800Å∼2000Å의 두께로 형성한다.Subsequently, an N-type polysilicon layer 15 doped with phosphorous is formed on the gate insulating layer 14 so as to have a predetermined height over the semiconductor substrate 11. Here, the N-type polysilicon layer 15 is formed so that phosphorus is doped at a concentration of at least 2 x 10 21 / cm 2 or more, and is formed to a thickness of 800 kPa to 2000 kPa.

도 2b에 도시된 바와 같이, N형 폴리실리콘층(15)의 표면에 플라즈마도핑방법으로 보론(Boron)을 도핑하여 P형 폴리실리콘층(15A)으로 바꾼다. 여기서, 보론은 블랭킷(Blanket)방식으로 즉, N형 폴리실리콘층(15)의 전면에 도핑한다. 이때, 보론은 1×10/㎠∼3×10/㎠의 농도로, 3KeV∼5KeV의 에너지로 도핑한다.As shown in FIG. 2B, boron (Doron) is doped to the surface of the N-type polysilicon layer 15 by a plasma doping method to be changed into a P-type polysilicon layer 15A. Here, the boron is doped in a blanket manner, that is, the entire surface of the N-type polysilicon layer 15. At this time, boron is doped with an energy of 3KeV to 5KeV at a concentration of 1 × 10 / cm 2 to 3 × 10 / cm 2.

따라서, 셀영역 및 주변영역의 NMOS와 PMOS 상부의 N형 폴리실리콘층(15)은 모두 P형 폴리실리콘층(15A)으로 바뀐다.Accordingly, the N-type polysilicon layer 15 on the NMOS in the cell region and the peripheral region and the PMOS upper portion are all changed to the P-type polysilicon layer 15A.

N형 폴리실리콘층(15)이 P형 폴리실리콘층(15A)으로 바뀌면서 형성되는 특성은 도 3에서 자세히 볼 수 있다.The characteristics formed by changing the N-type polysilicon layer 15 to the P-type polysilicon layer 15A can be seen in detail in FIG. 3.

도 3은 보론도핑에 의한 NMOS의 C-V특성의 변화를 나타내는 그래프이다.3 is a graph showing a change in the C-V characteristics of the NMOS by boron doping.

도 3에 도시된 바와 같이, 'B' 그래프는 NMOS의 C-V(Capacitance-Volatge)특성을 나타내고, 'A' 그래프는 NMOS에서 N형 폴리실리콘층이 이온주입에 의해 P형 폴리실리콘층으로 바꼈을때의 특성을 나타난다.As shown in FIG. 3, the 'B' graph shows the capacitance-volatge (CV) characteristics of the NMOS, and the 'A' graph shows that the N-type polysilicon layer is changed to a P-type polysilicon layer by ion implantation in the NMOS. The characteristics of when.

NMOS의 C-V특성은 'B' 그래프와 같이 전압이 낮을 수록 저장용량이 커진다. 그러나, 도 2b와 같이 NMOS에 형성되어야할 N형 폴리실리콘층(15)이 보론주입에 의해 P형 폴리실리콘층(15A)으로 변환될 경우는 'A' 그래프에서 볼 수 있듯이 'B' 그래프에 비해 낮은 전압에서 갖는 저장용량이 줄어들고, 동일한 저장용량을 갖는 전 압이 다른 것을 알 수 있다. 그래프에서 전압이 -2인 지점에서 'B' 그래프의 저장용량는 1.0, 'A' 그래프의 저장용량은 0.7이고, 저장용량이 0.4로 동일할때 'B' 그래프의 전압은 1, 'A' 그래프의 전압은 0이 된 것을 알 수 있다.The C-V characteristics of the NMOS, as shown in the 'B' graph, the lower the voltage, the larger the storage capacity. However, when the N-type polysilicon layer 15 to be formed in the NMOS is converted to the P-type polysilicon layer 15A by boron injection as shown in FIG. 2B, as shown in the 'A' graph, Compared with the lower storage voltage, the storage capacity is reduced, and the voltage having the same storage capacity is different. At the point where the voltage is -2, the storage capacity of graph 'B' is 1.0, the storage capacity of 'A' graph is 0.7, and the storage capacity is equal to 0.4, the voltage of graph 'B' is 1, 'A' graph. It can be seen that the voltage of becomes zero.

도 2c에 도시된 바와 같이, P형 폴리실리콘층(15A) 상에 보호층(16)을 형성한다. 여기서, 보호층(16)은 후속 감광막스트립공정에서 산소플라즈마 또는 실리콘식각물(Silicon Etchant, 예컨대 SC-1)에 의한 PMOS의 P형 폴리실리콘층(15A)을 보호하기 위한 것으로, 저온에서 화학기상증착법으로 형성한 산화막, 저온에서 형성한 비정질카본막 또는 산화막과 비정질카본막의 적층구조로 형성한다. 이때, 산화막은 80℃∼300℃의 저온에서 100Å∼1000Å의 두께로 형성한다. 또한, 비정질카본막도 산화막과 동일하게 80℃∼300℃의 저온에서 형성한다.As shown in FIG. 2C, the protective layer 16 is formed on the P-type polysilicon layer 15A. Here, the protective layer 16 is to protect the P-type polysilicon layer 15A of the PMOS by oxygen plasma or silicon etchant (Silicon Etchant, for example SC-1) in the subsequent photoresist film strip process, the chemical vapor at low temperature An oxide film formed by a vapor deposition method, an amorphous carbon film formed at a low temperature, or a laminated structure of an oxide film and an amorphous carbon film is formed. At this time, the oxide film is formed at a thickness of 100 Pa to 1000 Pa at a low temperature of 80 ° C to 300 ° C. The amorphous carbon film is also formed at a low temperature of 80 ° C to 300 ° C similarly to the oxide film.

위와 같이, 80℃∼300℃의 저온에서 보호층(16)을 형성하기 때문에 P형 폴리실리콘층(15A)의 산화방지 및 P형 폴리실리콘층(15A)의 표면에 도핑된 보론이 열공정에 의해 활성화(Activation)되는 것을 방지할 수 있다.As described above, since the protective layer 16 is formed at a low temperature of 80 ° C to 300 ° C, boron doped on the surface of the P-type polysilicon layer 15A and the oxidation prevention of the P-type polysilicon layer 15A are applied to the thermal process. Activation can be prevented.

도 2d에 도시된 바와 같이, 보호층(16) 상에 셀영역 및 주변영역의 NMOS를 오픈시키는 감광막패턴(17)을 형성한다. 여기서, 감광막패턴(17)은 보호층(16) 상에 감광막을 도포하고, 노광 및 현상으로 셀영역 및 주변영역의 NMOS가 오픈되도록 패터닝하여 형성한다. 또한, 감광막패턴(17)을 형성한 후 감광막의 하드베이킹(Hardbaking)을 100℃∼250℃의 온도에서 30분간 실시하여 감광막패턴(17)의 강도를 높여준다.As shown in FIG. 2D, a photoresist pattern 17 is formed on the protective layer 16 to open the NMOS in the cell region and the peripheral region. Here, the photoresist pattern 17 is formed by applying a photoresist on the protective layer 16 and patterning the NMOS in the cell region and the peripheral region to be opened by exposure and development. In addition, after the photoresist pattern 17 is formed, hard baking of the photoresist is performed at a temperature of 100 ° C. to 250 ° C. for 30 minutes to increase the strength of the photoresist pattern 17.

이어서, 감광막패턴(17)에 의해 오픈된 셀영역 및 주변영역의 NMOS의 보호 층(16)을 식각하여 주변영역의 PMOS에만 보호층(16A)을 잔류시킨다. 여기서, 보호층(16)이 산화막으로 형성된 경우 습식식각으로 제거하고, 비정질카본막으로 형성된 경우 산소스트립을 통해 제거한다.Subsequently, the NMOS protective layer 16 of the cell region and the peripheral region opened by the photoresist pattern 17 is etched to leave the protective layer 16A only in the PMOS of the peripheral region. In this case, when the protective layer 16 is formed of an oxide film, the protective layer 16 is removed by wet etching, and when the protective layer 16 is formed of an amorphous carbon film, the protective layer 16 is removed through an oxygen strip.

도 2e에 도시된 바와 같이, 감광막패턴(17)에 의해 오픈된 셀영역 및 주변영역의 NMOS에 P형 폴리실리콘층(15A)의 표면을 산화식각처리를 통해 보론(Boron)의 손실(Loss)을 발생시켜 N형 폴리실리콘층으로 바꾼다. As shown in FIG. 2E, the loss of boron is caused by oxidative etching the surface of the P-type polysilicon layer 15A in the NMOS of the cell region and the peripheral region opened by the photoresist pattern 17. To form an N-type polysilicon layer.

여기서, 산화식각처리는 60℃∼100℃의 고온에서 SC-1(Standard Cleaning-1)을 통해 P형 폴리실리콘층(15A)을 50Å∼100Å두께만큼 식각한다. 또한, 60℃∼100℃의 고온탈이온수(Hot DI), 플라즈마 O2와 불산(HF) 처리를 차례로 실시하여 P형 폴리실리콘층(15A)을 50Å∼100Å두께만큼 식각한다.Here, in the oxidation etching process, the P-type polysilicon layer 15A is etched by 50 kPa to 100 kPa through SC-1 (Standard Cleaning-1) at a high temperature of 60 ° C to 100 ° C. Further, hot deionized water (Hot DI) at 60 ° C to 100 ° C, plasma O 2 and hydrofluoric acid (HF) treatment are sequentially performed to etch the P-type polysilicon layer 15A by 50 kPa to 100 kPa thickness.

따라서, 셀영역 및 주변영역의 NMOS에 P형 폴리실리콘층(15A)의 표면에 분포된 보론이 60℃∼100℃의 고온으로 산화처리하여 손실됨과 동시에 보론이 분포되어 있는 두께(H) 즉, 50Å∼100Å두께만큼 식각함으로써 보론의 손실을 최대화시킨다.Therefore, the boron distributed on the surface of the P-type polysilicon layer 15A in the NMOS in the cell region and the peripheral region is oxidized and lost at a high temperature of 60 ° C to 100 ° C, and at the same time, the thickness H in which the boron is distributed, Maximize the loss of boron by etching 50 to 100 mm thick.

상기한 산화식각처리시 산소 플라즈마처리에 의해 PMOS지역에서 감광막패턴(17)이 일부 소실(17A)된다. 그러나, 감광막패턴(17A) 하부에 보호층(16A)이 PMOS의 P형 폴리실리콘층(15B)을 보호함으로써 보론의 손실에 의한 추가적인 보론 손실을 방지할 수 있다.The photoresist pattern 17 is partially lost 17A in the PMOS region by the oxygen plasma treatment during the oxidation etching process. However, since the protective layer 16A protects the P-type polysilicon layer 15B of the PMOS under the photoresist pattern 17A, additional boron loss due to loss of boron can be prevented.

위와 같이, 산화식각처리에 따른 보론의 손실로 인해 NMOS에는 N형 폴리실리콘전극(15C)이, PMOS에는 P형 폴리실리콘전극(15B)이 형성된다.As described above, the N-type polysilicon electrode 15C is formed in the NMOS, and the P-type polysilicon electrode 15B is formed in the PMOS due to the loss of boron due to the oxidation etching process.

도 2f에 도시된 바와 같이, PMOS의 P형 폴리실리콘전극(15B) 상에 감광막패턴(17A)과 보호층(16A)을 제거한다. 여기서, 감광막패턴(17A)은 산소스트립 및 H2SO5 를 메인가스로 하는 후세정(Post Cleaning)공정으로 제거하고, 보호층(16A)은 산화막의 경우 희석된 불산(Diluted HF)으로 제거하거나, 비정질카본막의 경우 감광막패턴(17A)과 동일하게 산소스트립으로 제거한다.As shown in FIG. 2F, the photosensitive film pattern 17A and the protective layer 16A are removed on the P-type polysilicon electrode 15B of the PMOS. Here, the photoresist pattern 17A is removed by a post cleaning process using oxygen strip and H 2 SO 5 as the main gas, and the protective layer 16A is removed by diluted hydrofluoric acid (Diluted HF) in the case of an oxide film. In the case of the amorphous carbon film, the oxygen strip is removed in the same manner as the photosensitive film pattern 17A.

도 2g에 도시된 바와 같이, 이온주입후 열처리(Post Implant Anneal)공정 즉, 활성화어닐을 실시한다. 활성화어닐은 도펀트(Dopant)의 활성화 및 열적안정성을 부여할 수 있다.As shown in FIG. 2G, a post-implant annealing process, that is, activation annealing is performed. Activation annealing can impart activation and thermal stability of the dopant.

상술한 본 발명은, N형 폴리실리콘층(15)을 P형 폴리실리콘층(15A)으로 변환하는데 플라즈마도핑공정을 적용할 때 N형 폴리실리콘층(15)의 표면에 보론을 도핑하고, P형 폴리실리콘층(15A)을 보호하는 보호층(16A) 및 감광막패턴(17)을 형성한 후 NMOS의 P형 폴리실리콘층(15B)을 산화식각처리를 실시하여 보론의 손실을 유발함으로써 플라즈마도핑공정 후에 후속공정에 의해 발생하는 P형 폴리실리콘층에서 보론의 손실을 방지하여 폴리공핍효과(Poly Silicon Depletion Effect)의 개선 및 셀전류(Cell Current)를 확보할 수 있는 장점이 있다.In the present invention described above, when the plasma doping process is applied to convert the N-type polysilicon layer 15 to the P-type polysilicon layer 15A, boron is doped on the surface of the N-type polysilicon layer 15, and After forming the protective layer 16A and the photoresist pattern 17 to protect the type polysilicon layer 15A, the PMOS polysilicon layer 15B of the NMOS is subjected to oxidative etching to cause loss of boron by causing boron loss. After the process, it is possible to prevent the loss of boron in the P-type polysilicon layer generated by a subsequent process, thereby improving the poly silicon depletion effect and securing cell current.

또한, 이온주입마스크로 사용되는 감광막패턴을 형성하지 않기 때문에 플라즈마도핑공정시 이온주입에 의해 발생하는 감광막경화 현상을 근본적으로 방지할 수 있어서, 감광막 잔류물 및 언스트립을 방지하기 위한 후속 감광막 스트립공정과 후세정공정을 단순화 시킬 수 있는 장점이 있다.In addition, since the photoresist pattern used as the ion implantation mask is not formed, the photoresist hardening phenomenon caused by ion implantation during the plasma doping process can be fundamentally prevented, so that the subsequent photoresist strip process for preventing photoresist residue and unstripe There is an advantage to simplify the after-cleaning process.

또한, N형 폴리실리콘층(15)을 전체구조에 형성한 후 보론을 도핑하고, NMOS지역의 폴리실리콘층 표면에 도핑된 보론을 제거하는 공정(Scheme)을 실시함으로써 듀얼폴리게이트 형성을 위해 마스크공정을 한번만 진행하기 때문에 공정마진을 확보할 수 있는 장점이 있다.In addition, after forming the N-type polysilicon layer 15 in the entire structure, doping the boron, and the step (Scheme) to remove the doped boron on the surface of the polysilicon layer in the NMOS region (mask) to form a dual polygate Since the process is performed only once, there is an advantage of securing a process margin.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상기한 본 발명은 플라즈마도핑공정을 통한 듀얼폴리게이트 형성시 감광막의 경화에 의한 잔류물 또는 언스트립과 도펀트손실을 방지함과 동시에 공정마진을 확보할 수 있는 효과가 있다.The present invention has the effect of preventing the residue or unstrip and dopant loss due to the curing of the photosensitive film when forming the dual polygate through the plasma doping process and at the same time secure a process margin.

Claims (10)

NMOS와 PMOS가 정의된 반도체 기판 상에 게이트절연막을 형성하는 단계;Forming a gate insulating film on a semiconductor substrate in which NMOS and PMOS are defined; 상기 게이트절연막 상에 N형 폴리실리콘층을 형성하는 단계;Forming an N-type polysilicon layer on the gate insulating film; 상기 N형 폴리실리콘층의 표면에 P형 불순물을 도핑하여 P형 폴리실리콘층으로 바꾸는 단계;Doping the surface of the N-type polysilicon layer with a P-type impurity to convert the P-type polysilicon layer; 상기 PMOS의 P형 폴리실리콘층 상에 보호층을 형성하는 단계;Forming a protective layer on the P-type polysilicon layer of the PMOS; 상기 보호층에 의해 오픈된 NMOS의 P형 폴리실리콘층의 표면에 도핑된 P형 불순물을 제거하는 단계; Removing the P-type impurities doped on the surface of the P-type polysilicon layer of the NMOS opened by the protective layer; 상기 보호층을 제거하는 단계; 및Removing the protective layer; And 상기 N형 및 P형 폴리실리콘층에 활성화어닐을 실시하는 단계Activating annealing on the N-type and P-type polysilicon layers 를 포함하는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device having a dual poly gate comprising a. 제1항에 있어서,The method of claim 1, 상기 보호층을 형성하는 단계는,Forming the protective layer, 상기 P형 폴리실리콘층 상에 보호층을 형성하는 단계;Forming a protective layer on the P-type polysilicon layer; 상기 보호층 상에 감광막패턴을 형성하는 단계; 및Forming a photoresist pattern on the protective layer; And 상기 감광막패턴을 식각마스크로 상기 NMOS의 P형 폴리실리콘층은 오픈되고 PMOS의 P형 폴리실리콘층 상에는 보호층이 잔류시키는 단계Etching the P-type polysilicon layer of the NMOS with the photoresist pattern as an etch mask and leaving a protective layer on the P-type polysilicon layer of the PMOS; 를 포함하는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device having a dual poly gate comprising a. 제1항에 있어서,The method of claim 1, 상기 보호층은 산화막, 비정질카본막 또는 산화막과 비정질카본막의 적층구조 중에서 어느 하나로 형성하는 것을 특징으로 하는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법.The protective layer may be formed of any one of an oxide film, an amorphous carbon film, or a laminated structure of an oxide film and an amorphous carbon film. 제3항에 있어서,The method of claim 3, 상기 산화막은 80℃∼300℃의 저온에서 화학기상증착법으로 형성하는 것을 특징으로 하는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법.The oxide film is a method of manufacturing a semiconductor device having a dual poly gate, characterized in that formed by chemical vapor deposition at a low temperature of 80 ℃ to 300 ℃. 제3항에 있어서, The method of claim 3, 상기 보호층은 100Å∼1000Å의 두께로 형성하는 것을 특징으로 하는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법.The protective layer is a semiconductor device manufacturing method having a dual poly gate, characterized in that formed to a thickness of 100 ~ 1000Å. 제1항에 있어서,The method of claim 1, 상기 P형 불순물은 보론을 사용하는 것을 특징으로 하는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법.The P-type impurity is a manufacturing method of a semiconductor device having a dual poly gate, characterized in that using the boron. 제1항 또는 제6항에 있어서,The method according to claim 1 or 6, 상기 N형 폴리실리콘층의 표면에 P형 불순물을 도핑하는 단계는,Doping the P-type impurities on the surface of the N-type polysilicon layer, 플라즈마도핑방법으로 진행하되 3keV∼5keV의 에너지로 실시하는 것을 특징으로 하는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device having a dual polygate, characterized in that the plasma doping method is carried out with an energy of 3keV to 5keV. 제1항에 있어서,The method of claim 1, 상기 오픈된 NMOS의 P형 폴리실리콘층의 표면에 도핑된 P형 불순물을 제거하는 단계는,Removing the P-type impurities doped on the surface of the P-type polysilicon layer of the open NMOS, 60℃∼100℃의 고온에서 SC-1공정으로 50Å∼100Å의 폴리실리콘을 식각하는 것을 특징으로 하는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법.A method for manufacturing a semiconductor device having a dual polygate, wherein the polysilicon is etched from 50 kPa to 100 kPa in a SC-1 step at a high temperature of 60 ° C to 100 ° C. 제1항에 있어서,The method of claim 1, 상기 오픈된 NMOS의 P형 폴리실리콘층의 표면에 도핑된 P형 불순물을 제거하는 단계는,Removing the P-type impurities doped on the surface of the P-type polysilicon layer of the open NMOS, 60℃∼100℃의 고온탈이온수, 플라즈마 O2와 불산처리를 차례로 진행하여 50Å∼100Å의 폴리실리콘을 식각하는 것을 특징으로 하는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법.A method for manufacturing a semiconductor device having a dual polygate, wherein the high temperature deionized water at 60 ° C. to 100 ° C., plasma O 2 and hydrofluoric acid treatment are sequentially performed to etch 50 μs to 100 μs of polysilicon. 제1항에 있어서,The method of claim 1, 상기 PMOS의 보호층을 제거하는 단계는,Removing the protective layer of the PMOS, 희석된 불산 또는 산소스트립으로 제거하는 것을 특징으로 하는 듀얼폴리게이트를 갖는 반도체 소자의 제조방법.A method for manufacturing a semiconductor device having a dual polygate, characterized in that the removal with dilute hydrofluoric acid or oxygen strip.
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