KR20030049594A - Method for forming the gate electrode in semiconductor device - Google Patents
Method for forming the gate electrode in semiconductor device Download PDFInfo
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- KR20030049594A KR20030049594A KR1020010079836A KR20010079836A KR20030049594A KR 20030049594 A KR20030049594 A KR 20030049594A KR 1020010079836 A KR1020010079836 A KR 1020010079836A KR 20010079836 A KR20010079836 A KR 20010079836A KR 20030049594 A KR20030049594 A KR 20030049594A
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- gate electrode
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 230000003647 oxidation Effects 0.000 claims abstract description 18
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims description 14
- -1 spacer nitride Chemical class 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 보다 상세하게는 실리콘기판 상에 금속 게이트전극 패턴을 형성하고, 결과물 전체에 실리콘막을 증착한 후, 그 막에 선택적 산화공정을 진행하여 버퍼 산화막을 형성함으로써, 금속 게이트전극 이 산화되는 것을 방지할 수 있을 뿐만 아니라 후속 질화막으로 형성된 스페이서가 실리콘기판에 접촉되는 것을 방지하여 게이트전극과 드레인 사이의 누설전류 증가를 억제하고 반도체소자의 리프레쉬(refresh) 특성 및 수율을 향상시킬 수 있는 반도체소자의 게이트전극 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, by forming a metal gate electrode pattern on a silicon substrate, depositing a silicon film on the entire product, and then performing a selective oxidation process on the film to form a buffer oxide film. In addition, the metal gate electrode can be prevented from being oxidized, and the spacer formed by the subsequent nitride film is prevented from contacting the silicon substrate, thereby suppressing the increase of leakage current between the gate electrode and the drain, and the refresh characteristics and yield of the semiconductor device. A method of forming a gate electrode of a semiconductor device can be improved.
최근 게이트전극 물질로서 폴리실리콘 상부에 비저항이 낮으면서도 고온에서 텅스텐(W), 티타늄(Ti), 탄탈륨(Ta) 등의 고융점 금속을 추가한 금속 게이트전극을 형성하고 있으며, 그 중에서도 텅스텐을 사용한 금속 게이트는 소자의 고집적화에 따른 신호처리 속도 개선의 측면에서 기존 폴리사이드 게이트전극을 대체하고 있는 실정에 있다.Recently, as gate electrode materials, metal gate electrodes have been formed on top of polysilicon with high melting point metals such as tungsten (W), titanium (Ti), and tantalum (Ta) at a high temperature, with tungsten being used. Metal gates are replacing existing polyside gate electrodes in terms of improving signal processing speed due to high integration of devices.
도 1a 내지 도 1b는 종래 반도체소자의 게이트전극 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A through 1B are cross-sectional views sequentially illustrating a method of forming a gate electrode of a conventional semiconductor device.
도 1a에 도시된 바와 같이, 실리콘기판(200) 상에 게이트산화막(212), 폴리실리콘막(214), 텅스텐층(216) 및 질화마스크(218)를 순차적으로 적층한 후, 식각 공정에 의해 금속 게이트전극이 패터닝되어 금속 게이트전극 패턴(210)이 형성된다.As shown in FIG. 1A, the gate oxide film 212, the polysilicon film 214, the tungsten layer 216, and the nitride mask 218 are sequentially stacked on the silicon substrate 200, and then etched. The metal gate electrode is patterned to form a metal gate electrode pattern 210.
이때, 상기 금속 게이트전극 패터닝 시, 하부 게이트산화막(112)의 측벽에 손실이 유발되며, 이 손실을 복원하기 위해 게이트산화막(112)과 폴리실리콘막 (114) 측벽에 선택적 산화(oxidation)공정을 진행되어 버퍼 산화막(120)이 형성된다.In this case, when the metal gate electrode is patterned, a loss is caused on the sidewall of the lower gate oxide film 112, and a selective oxidation process is performed on the sidewalls of the gate oxide film 112 and the polysilicon film 114 to restore the loss. Proceeding to form the buffer oxide film 120.
그리고, 상기 도 1b에 도시된 바와 같이, 상기 금속 게이트전극 패턴(110) 중 텅스텐층(116)의 산화를 방지하기 위해 버퍼 산화막(120)이 형성된 금속 게이트전극 패턴 측벽에 질화물을 이용하여 베리어막(130)을 형성하였다.As shown in FIG. 1B, a barrier layer is formed using nitride on the sidewall of the metal gate electrode pattern on which the buffer oxide layer 120 is formed to prevent oxidation of the tungsten layer 116 of the metal gate electrode pattern 110. 130 was formed.
이어서, 상기 결과물 상에 질화물 또는 산화물을 증착한 후, 식각공정을 진행하여 베리어막(130)이 형성된 금속 게이트전극 패턴 측벽에 스페이서(140)를 형성하였다.Subsequently, after depositing nitride or oxide on the resultant, an etching process was performed to form spacers 140 on sidewalls of the metal gate electrode pattern on which the barrier layer 130 was formed.
그러나, 상기 종래와 같은 반도체소자의 게이트전극 형성공정을 이용하게 되면, 금속 게이트전극 패턴 중 텅스텐층의 산화를 방지하기 위해 질화물을 이용하여 형성된 베리어막과 질화막으로 구성된 스페이서가 실리콘기판에 "A"와 같이 직접 접촉됨에 따라 실리콘기판에 스트레스를 가하여 전기적인 특성에 영향을 줌으로써 게이트전극과 드레인 사이의 누설전류 증가되는 문제점이 있었다.However, according to the conventional gate electrode forming process of the semiconductor device, a spacer composed of a barrier film and a nitride film formed by using nitride to prevent oxidation of the tungsten layer of the metal gate electrode pattern is formed on the silicon substrate. As a direct contact, such as the stress on the silicon substrate affects the electrical characteristics there was a problem that the leakage current between the gate electrode and the drain increases.
또한, 상기 누설전류의 증가로 인해 반도체소자의 리프레쉬(refresh) 특성을 열화되는 문제점이 있었다.In addition, there is a problem in that the refresh characteristics of the semiconductor device is degraded due to the increase of the leakage current.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 실리콘기판 상에 게이트산화막, 폴리실리콘막과 금속막 및 하드마스크를 순차적으로 적층하여 금속 게이트전극 패턴을 형성하고, 결과물 전체에 실리콘막을 증착한 후, 그 막에 선택적 산화공정을 진행하여 버퍼산화막을 형성함으로써, 금속막이 산화되는 것을 방지할 수 있을 뿐만 아니라 후속 질화막으로 형성되는 스페이서가 실리콘기판에 접촉되어 스트레스를 가하는 것을 방지하여 게이트전극과 드레인 사이의 누설전류 증가를 억제하고, 반도체소자의 리프레쉬(refresh) 특성을 열화시키는 방지하는 것이 목적이다.The present invention has been made to solve the above problems, an object of the present invention is to sequentially form a gate oxide film, a polysilicon film and a metal film and a hard mask on a silicon substrate to form a metal gate electrode pattern, the result By depositing a silicon film on the whole, and then performing a selective oxidation process on the film to form a buffer oxide film, not only can the metal film be prevented from being oxidized, but the spacer formed by the subsequent nitride film is brought into contact with the silicon substrate to apply stress. The purpose of the present invention is to prevent an increase in leakage current between the gate electrode and the drain, and to prevent deterioration of the refresh characteristics of the semiconductor device.
도 1a 내지 도 1b는 종래 반도체소자의 게이트전극 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A through 1B are cross-sectional views sequentially illustrating a method of forming a gate electrode of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 게이트전극 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2D are cross-sectional views sequentially illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.
도 3은 본 발명에 따른 반도체소자의 게이트전극 형성방법에 의해 형성된 게이트전극을 나타내는 TEM 사진이다.3 is a TEM photograph showing a gate electrode formed by a method of forming a gate electrode of a semiconductor device according to the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
200 : 실리콘기판 210 : 금속 게이트전극 패턴200: silicon substrate 210: metal gate electrode pattern
212 : 게이트산화막 214 : 폴리실리콘막212: gate oxide film 214: polysilicon film
216 : 금속층 218 : 하드마스크216: metal layer 218: hard mask
220 : 제 1 버퍼 산화막 230 : 실리콘막220: first buffer oxide film 230: silicon film
240 : 제 2 버퍼 산화막 250 : 스페이서 질화막240: second buffer oxide film 250: spacer nitride film
상기 목적을 달성하기 위하여, 본 발명은 실리콘기판 상에 게이트산화막, 폴리실리콘막과 금속막 및 하드마스크를 순차적으로 적층하여 금속 게이트전극 패턴을 형성하는 단계와, 상기 금속 게이트전극 패턴 전체에 실리콘막을 증착한 후, 선택적 산화공정을 진행하여 버퍼 옥사이드막을 형성하는 단계와, 상기 결과물 상에 질화막을 증착한 후, 식각하여 금속 게이트전극 패턴 측벽에 스페이서 질화막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 게이트전극 형성방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of sequentially forming a gate oxide film, a polysilicon film, a metal film and a hard mask on a silicon substrate to form a metal gate electrode pattern, and a silicon film over the entire metal gate electrode pattern After the deposition, a selective oxidation process is performed to form a buffer oxide film, and a nitride film is deposited on the resultant, and then etched to form a spacer nitride film on the metal gate electrode pattern sidewall. A method of forming a gate electrode of a semiconductor device is provided.
바람직하게, 본 발명은 상기 실리콘막을 단결정실리콘과 다결정 실리콘 중 어느 하나를 선택하여 증착하는 것을 특징으로 한다.Preferably, the present invention is characterized in that the deposition of the silicon film by selecting any one of monocrystalline silicon and polycrystalline silicon.
바람직하게, 본 발명은 상기 실리콘막을 도핑된 실리콘막과 도핑되지 않은실리콘막 중 어느 하나를 선택하여 증착하는 것을 특징으로 한다.Preferably, the present invention is characterized by depositing any one of the doped silicon film and the undoped silicon film.
바람직하게, 본 발명은 상기 금속 게이트전극 패턴을 형성한 후, 금속 게이트전극 패턴 중 게이트산화막과 폴리실리콘막 측벽에 선택적 산화 공정을 진행하여 버퍼 산화막을 형성하는 단계를 더 포함하는 것을 특징으로 한다.Preferably, the present invention may further include forming a buffer oxide layer by performing a selective oxidation process on the sidewalls of the gate oxide layer and the polysilicon layer of the metal gate electrode pattern after forming the metal gate electrode pattern.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 게이트전극 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이며, 도 3은 본 발명에 따른 반도체소자의 게이트전극 형성방법에 의해 형성된 게이트전극을 나타내는 TEM 사진이다.2A to 2D are cross-sectional views sequentially illustrating a method of forming a gate electrode of a semiconductor device according to the present invention, and FIG. 3 is a TEM photograph showing a gate electrode formed by a method of forming a gate electrode of a semiconductor device according to the present invention. to be.
도 2a에 도시된 바와 같이, 실리콘기판(200) 상에 게이트산화막(212), 폴리실리콘막(214), 금속층(216) 및 질화마스크(218)를 순차적으로 적층한 후, 식각 공정에 의해 금속 게이트전극이 패터닝되어 금속 게이트전극 패턴(210)이 형성하며, 이때, 상기 금속층(216)은 텅스텐을 사용하여 증착한다.As shown in FIG. 2A, the gate oxide film 212, the polysilicon film 214, the metal layer 216, and the nitride mask 218 are sequentially stacked on the silicon substrate 200, and then the metal is etched by an etching process. The gate electrode is patterned to form a metal gate electrode pattern 210. In this case, the metal layer 216 is deposited using tungsten.
또한, 상기 금속 게이트전극 패터닝 시, 하부 게이트산화막(212)의 측벽에 손실이 유발되어 게이트산화막(212)과 폴리실리콘막(214) 측벽에 선택적 산화 (oxidation)공정을 진행되어 제 1버퍼 산화막(220)을 형성하여 손실을 복원한다.In addition, when the metal gate electrode is patterned, loss occurs on the sidewalls of the lower gate oxide layer 212, and a selective oxidation process is performed on the sidewalls of the gate oxide layer 212 and the polysilicon layer 214 to form a first buffer oxide layer ( 220) to restore the loss.
그러나, 상기 제 1버퍼 산화막(220)은 후속 실리콘막의 선택적 산화공정에 의해 형성되는 실리콘산화막(미도시함)으로 대체하는 것이 가능함으로써 생략할 수 있다.However, since the first buffer oxide film 220 can be replaced by a silicon oxide film (not shown) formed by a selective oxidation process of a subsequent silicon film, it can be omitted.
그리고, 도 2b에 도시된 바와 같이, 상기 금속 게이트전극 패턴(210) 전체에 단결정실리콘과 다결정 실리콘 중 어느 하나를 선택하여 실리콘막(230)을 증착한다.As shown in FIG. 2B, one of single crystal silicon and polycrystalline silicon is selected on the metal gate electrode pattern 210 to deposit the silicon film 230.
이때, 상기 실리콘막(230)은 도핑된 실리콘막과 도핑되지 않은 실리콘막 중 어느 하나를 선택하여 증착한다.In this case, the silicon film 230 selects and deposits any one of a doped silicon film and an undoped silicon film.
이어서, 도 2c에 도시된 바와 같이, 상기 금속 게이트전극 패턴(210) 전체에 증착된 실리콘막(미도시함)만 산화되도록 선택적 산화공정을 진행함으로써, "A"와 같은 제 2버퍼 산화막(240)을 형성하여 금속층(216)인 텅스텐이 산화되는 것을 방지한다.Subsequently, as shown in FIG. 2C, the second buffer oxide layer 240 such as “A” is subjected to a selective oxidation process so that only a silicon film (not shown) deposited on the entire metal gate electrode pattern 210 is oxidized. ) To prevent the tungsten, which is the metal layer 216, from being oxidized.
이때, 상기 제 2버퍼 산화막(240)에 의해 후속 스페이서 질화막이 실리콘기판에 접촉되는 것이 방지되어 질화물에 의한 스트레스가 제거된다.At this time, the subsequent spacer nitride film is prevented from contacting the silicon substrate by the second buffer oxide film 240, and the stress caused by the nitride is removed.
또한, 상기 제 2버퍼 산화막(240)은 도 3의 TEM 사진에서 "A"와 같이 구체화 하여 나타내고 있다.In addition, the second buffer oxide film 240 is embodied as "A" in the TEM photograph of FIG. 3.
계속하여, 도 2d에 도시된 바와 같이, 상기 결과물 상에 질화물 또는 산화물을 증착한 후, 식각공정을 진행하여 제2버퍼 산화막(240)이 형성된 금속 게이트전극 패턴 측벽에 스페이서 질화막(250)을 형성하여 후속 공정 시, 금속 게이트전극 패턴이 손상되는 것을 막는다.Subsequently, as illustrated in FIG. 2D, after the nitride or the oxide is deposited on the resultant, the etching process is performed to form the spacer nitride layer 250 on the sidewall of the metal gate electrode pattern on which the second buffer oxide layer 240 is formed. This prevents the metal gate electrode pattern from being damaged during the subsequent process.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 게이트전극 형성방법을 이용하게 되면, 실리콘기판 상에 금속 게이트전극 패턴을 형성하고, 결과물 전체에 실리콘막을 증착한 후, 그 막에 선택적 산화공정을 진행하여 버퍼산화막을 형성함으로써, 금속막이 산화되는 것을 방지할 수 있을 뿐만 아니라 후속 질화막으로 형성되는 스페이서가 실리콘기판에 접촉되어 스트레스를 가하는 것을 방지하여 게이트전극과 드레인 사이의 누설전류 증가를 억제하고, 반도체소자의 리프레쉬(refresh) 특성을 열화시키는 방지하여, 반도체소자의 리프레쉬(refresh) 특성 및 수율을 향상시킬 수 있는 효과가 있다.Therefore, as described above, when the gate electrode forming method of the semiconductor device according to the present invention is used, a metal gate electrode pattern is formed on a silicon substrate, a silicon film is deposited on the entire product, and then a selective oxidation process is performed on the film. By forming the buffer oxide film, the metal oxide film can be prevented from being oxidized, and the spacer formed by the subsequent nitride film can be prevented from contacting the silicon substrate to apply stress to thereby suppress an increase in leakage current between the gate electrode and the drain. In addition, it is possible to prevent the deterioration of the refresh characteristics of the semiconductor device, thereby improving the refresh characteristics and the yield of the semiconductor device.
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| US7521316B2 (en) | 2004-09-09 | 2009-04-21 | Samsung Electronics Co., Ltd. | Methods of forming gate structures for semiconductor devices |
| US9831240B2 (en) | 2013-07-12 | 2017-11-28 | Samsung Electronics Co., Ltd. | Elevated source drain semiconductor device with L-shaped spacers and fabricating method thereof |
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| KR100608340B1 (en) * | 1999-10-25 | 2006-08-09 | 주식회사 하이닉스반도체 | Gate formation method of semiconductor device |
| KR100340867B1 (en) * | 1999-12-22 | 2002-06-20 | 박종섭 | Method for forming gate electrode of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7521316B2 (en) | 2004-09-09 | 2009-04-21 | Samsung Electronics Co., Ltd. | Methods of forming gate structures for semiconductor devices |
| US7772637B2 (en) | 2004-09-09 | 2010-08-10 | Samsung Electronics Co., Ltd. | Semiconductor devices including gate structures and leakage barrier oxides |
| US9831240B2 (en) | 2013-07-12 | 2017-11-28 | Samsung Electronics Co., Ltd. | Elevated source drain semiconductor device with L-shaped spacers and fabricating method thereof |
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