KR100244577B1 - Manufacturing method for silicide of semiconductor memory cell - Google Patents
Manufacturing method for silicide of semiconductor memory cell Download PDFInfo
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- KR100244577B1 KR100244577B1 KR1019920010628A KR920010628A KR100244577B1 KR 100244577 B1 KR100244577 B1 KR 100244577B1 KR 1019920010628 A KR1019920010628 A KR 1019920010628A KR 920010628 A KR920010628 A KR 920010628A KR 100244577 B1 KR100244577 B1 KR 100244577B1
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- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 35
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000151 deposition Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000001039 wet etching Methods 0.000 claims abstract description 12
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 238000000206 photolithography Methods 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 게이트와 실리콘기판과의 수직거리를 증가시켜 미세한 누설전류를 억제토록 하는 반도체 메모리셋의 실리사이드 제조방법에 관한 것으로서 실리콘기판에 필드산화막을 형성한 후 게이트산화막과 게이트폴리실리콘을 차례로 데포지션하는 단계와, 상기 게이트폴리실리콘 전면에 나이트라이드를 데포지션하는 단계와, 상기 단계 후 사진식각 공정으로 게이트를 정의하고 나이트라이드, 게이트폴리실리콘, 게이트산화막을 에치하여 게이트를 형성하는 단계와, 상기 단계 후 산화막을 전면에 데포지션하고 상기 산화막을 에치백하여 상기 게이트의 측면에 사이드월을 형성하는 단계와, 상기 게이트폴리실리콘 상의 나이트라이드를 습식식각으로 제거하는 단계와, 상기 단계 후 메탈을 증착하고 어닐링하여 상기 게이트폴리실리콘과 실리콘기판에 실리사이드를 형성하고 상기 측벽 및 필드산화막 상에 잔류하는 메탈을 습식식각으로 제거하는 단계를 구비한다. 따라서, 나이트라이드가 데포지션되는 두께만큼 수직방향으로 게이트의 길이를 증가시킨 후 실리사이드를 사이드얼 내부에 형성되도록 하여 게이트폴리실리콘과 실리콘기판간의 거리를 최대로 확보함으로써 상기 게이트폴리실리콘과 실리콘기판에 흐르는 미세누설전류를 억제할 수 있는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a silicide of a semiconductor memory set that increases a vertical distance between a gate and a silicon substrate to suppress minute leakage current. After forming a field oxide film on a silicon substrate, the gate oxide film and the gate polysilicon are sequentially deposited. And depositing nitride on the entire surface of the gate polysilicon; defining a gate by a photolithography process after the step; forming a gate by etching the nitride, gate polysilicon, and gate oxide layer; Depositing an oxide film on the entire surface after the step and etching back the oxide film to form a sidewall on the side of the gate, wet removing the nitride on the gate polysilicon, and depositing a metal after the step And annealing to form the gate polysilicon and silicon group Forming silicide on the plate and wet etching the metal remaining on the sidewall and the field oxide layer. Therefore, after increasing the length of the gate in the vertical direction by the thickness at which the nitride is deposited, the silicide is formed inside the sidewall to maximize the distance between the gate polysilicon and the silicon substrate, thereby increasing the gate polysilicon and the silicon substrate. It is possible to suppress the flowing micro leakage current.
Description
제1도는 종래 반도체소자의 실리사이드 형성공정도1 is a process diagram of silicide formation of a conventional semiconductor device
제2도는 본 발명에 따른 반도체소자의 실리사이드 형성공정도2 is a process diagram of silicide formation of a semiconductor device according to the present invention.
제3도는 본 발명에 따른 실시예를 나타낸 반도체소자의 실리사이드 형성공정도3 is a process diagram of silicide formation of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 필드산화막1: silicon substrate 2: field oxide film
3 : 게이트산화막 4 : 게이트폴리실리콘3: gate oxide film 4: gate polysilicon
5 : 게이트 6 : 산화막5 gate 6 oxide film
7, 17 : 사이드월 8 : 메탈7, 17: sidewall 8: metal
9 : 실리사이드 10, 12 : 나이트라이드9: silicide 10, 12: nitride
본 발명은 반도체 메모리셋의 실리사이드 제조방법에 관한 것으로서, 특히 게이트와 실리콘기판과의 수직거리를 증가시켜 미세한 누설전류를 억제토록 하는 반도체 메모리셋의 실리사이드 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicide manufacturing method of a semiconductor memory set, and more particularly, to a silicide manufacturing method of a semiconductor memory set which increases a vertical distance between a gate and a silicon substrate to suppress minute leakage current.
일반적으로 반도체 메모리셋의 실리사이드(SILICIDE) 제조공정 중에 문제점의 하나가 격리되어야 할 실리사이드(SILICIDE) 간에 존재하는 미세한 누설전류인데 이러한 미세전류를 억제하는 방법으로 공정자체의 개선을 통해 실리콘 이외의 지역에서는 메탈과 실리콘기판간에 반응이 일어나지 않도록 하는 방법과, 또한 메탈과 실리콘기판과의 거리를 길게하여 누설전류를 개선하는 방법이 있다.In general, one of the problems during the manufacturing process of silicides of semiconductor memory sets is a minute leakage current between silicides to be isolated. In the non-silicon region by improving the process itself by suppressing such a microcurrent, There is a method of preventing a reaction between the metal and the silicon substrate, and a method of improving the leakage current by lengthening the distance between the metal and the silicon substrate.
즉, 종래 반도체 메모리셋의 누설전류방법은 제1도에 도시된 바와 같이 실리콘기판(1)에 각 소자간의 격리를 위해 필드산화막(2)을 형성시킨 다음((a)도), 상기 필드산화막(2)과 실리콘기판(1) 위에 게이트산화막(3)을 데포지션한 후 ((b)도), 상기 게이트산화막(3) 전면에 게이트폴리실리콘(40을 증착한다((c)도).That is, in the conventional leakage memory method of the semiconductor memory set, as shown in FIG. 1, the field oxide film 2 is formed on the silicon substrate 1 for isolation between the elements ((a)), and then the field oxide film is formed. After the gate oxide film 3 is deposited on (2) and the silicon substrate 1 ((b)), the gate polysilicon 40 is deposited on the entire surface of the gate oxide film 3 ((c)).
그 다음 (d)도에서와 같이 포토레지스터로서 게이트산화막(3)과 게이트폴리실리콘(4)을 에치하여 게이트(5)를 형성한다.Next, as shown in (d), the gate oxide film 3 and the gate polysilicon 4 are etched as a photoresist to form the gate 5.
상기 공정이 완료되면 (e)도와 같이 산화막(6)을 데포지션한 다음 상기 산화막(6)을 에치백하여 게이트측벽에 경사를 형성시킬 목적으로 사이드월(7)을 형성시킨 후 (f)도와 같이 CO, Ti등과 같은 메탈(8)을 증착한 다음 어닐링과 습식식각을 통해 게이트와 실리콘기판(1)에만 선택적으로 실리사이드(9)를 형성하게 된다.After the process is completed, as shown in (e), the oxide film 6 is deposited, and the sidewall 7 is formed to etch back the oxide film 6 to form a slope on the gate side wall. As described above, the silicide 9 is selectively formed only on the gate and the silicon substrate 1 through the deposition of a metal 8 such as CO, Ti, etc., followed by annealing and wet etching.
이러한 종래의 실리사이드 형성방법은 실리콘기판 위에 실리사이드를 형성하는 과정에서 산화막에도 약간의 실리사이드가 형성되어 인접한 두 영역 즉, 게이트와 실리콘기판 사이에 누설전류가 발생되므오써 반도체소자의 신뢰성이 저하되는 문제점이 발생하게 된다.In the conventional silicide forming method, a slight silicide is formed in the oxide film during the formation of silicide on the silicon substrate, so that leakage current is generated between two adjacent regions, that is, the gate and the silicon substrate, thereby deteriorating the reliability of the semiconductor device. Will occur.
따라서, 본 발명은 상기와 같은 문제점을 해소하기 위하여 게이트와 실리콘기판 간에 수평방향길이에는 변화를 주지않고 수직방향의 길이를 증가시켜 최종적으로 격리될 두 지역간의 거리를 증가시켜 미세누설전류를 억제할 수 있는 반도체 메모리셀의 실리사이드 제조방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention can suppress the micro-leakage current by increasing the distance between the two areas to be finally isolated by increasing the length in the vertical direction without changing the horizontal length between the gate and the silicon substrate to solve the above problems. It is an object of the present invention to provide a method for producing silicide of a semiconductor memory cell.
상기 목적을 달성하기 위한 본 발명의 일 실시에 따른 반도체 메모리셀의 실리사이드 제조방법은 실리콘기판에 필드산화막을 형성한 후 게이트산화막과 게이트폴리실리콘을 차례로 데포지션하는 단계와, 상기 게이트폴리실리콘 전면에 나이트라이드를 데포지션하는 단계와, 상기 단계 후 사진식각 공정으로 게이트를 정의하고 나이트라이드, 게이트폴리실리콘, 게이트산화막을 에치하여 게이트를 형성하는 단계와, 상기 단계 후 산화막을 전면에 데포지션하고 상기 산화막을 에치백하여 상기 게이트의 측면에 사이드월을 형성하는 단계와, 상기 게이트폴리실리콘 상의 나이트 라이드를 습식식각으로 제거하는 단계와, 상기 단계 후 메탈을 증착하고 어닐링하여 상기 게이트폴리실리콘과 실리콘기판에 실리사이드를 형성하고 상기 측벽 및 필드산화막 상에 잔류하는 메탈을 습식식각으로 제거하는 단계를 구비한다.According to one or more exemplary embodiments, a method of manufacturing a silicide of a semiconductor memory cell according to an embodiment of the present invention may include forming a field oxide film on a silicon substrate, and then depositing a gate oxide film and a gate polysilicon on the front surface of the gate polysilicon. Depositing a nitride, defining a gate by a photolithography process after the step, and etching the nitride, gate polysilicon, and gate oxide layer to form a gate; and depositing the oxide layer on the entire surface after the step; Etching back an oxide film to form a sidewall on the side of the gate, wet etching the nitride on the gate polysilicon, and depositing and annealing the metal after the step to deposit the metal and the gate polysilicon substrate. Form silicide on the sidewalls and field oxidation The metal remaining on and a step of removing by wet etching.
상기 목적을 달성하기 위한 본 발명의 다른 실시에 따른 반도체 메모리셀의 실리사이드 제조방법은 실리콘기판에 필드산화막을 형성한 후 게이트산화막과 게이트폴리실리콘을 차례로 데포지션하는 단계와, 상기 게이트폴리실리콘 전면에 산화막을 데포지션하는 단계와, 상기 단계 후 사진식각 공정으로 게이트를 정의하고 산화막, 게이트폴리실리콘, 게이트산화막을 에치하여 게이트를 형성하는 단계와, 상기 단계후 나이트라이드를 전면에 데포지션하고 상기 나이트라이드를 에칙백하여 상기 게이트의 측면에 사이드월을 형성하는 단계와, 상기 게이트폴리실리콘 상의 산화막을 제거하는 단계와, 상기 단계 후 메탈을 증착하고 어닐링하여 상기 게이트폴리실리콘과 실리콘기판에 실리사이드를 형성하고 상기 측벽 및 필드산화막 상에 잔류하는 메탈을 습식식각으로 제거하는 단계를 구비한다.According to another aspect of the present invention, there is provided a method of manufacturing a silicide of a semiconductor memory cell, after forming a field oxide film on a silicon substrate, depositing a gate oxide film and a gate polysilicon in turn, and depositing a gate oxide film on the entire surface of the gate polysilicon. Depositing an oxide film, defining a gate by a photolithography process after the step, and etching the oxide film, the gate polysilicon, and the gate oxide film to form a gate, and depositing a nitride on the entire surface after the step; Forming a sidewall on the side surface of the gate by back-riding the rod; removing an oxide film on the gate polysilicon; and depositing and annealing a metal after the step to form silicide on the gate polysilicon and the silicon substrate. And remaining on the sidewalls and the field oxide layer. A and a step of removing by wet etching.
이하 첨부된 도면에 의해 상세히 설명하면 다음과 같다.Hereinafter, described in detail by the accompanying drawings as follows.
제 2 도는 본 발명에 따른 반도체 메모리셀의 실리사이드 제조공정을 도시한 것으로서, 먼저 실리콘기판(1)에 필드산화막(2)을 형성한 다음 ((a)도) 상기 실리콘 기판(1)과 필드산화막(2) 전면에 게이트산화막(3)을 증착한 후(cb)도), 상기 게이트산화막(3) 위에 게이트폴리실리콘(4)을 데포지션한다.((c)도). 상기 공정이 완료되면 (d)도에서와 같이 게이트폴리실리콘(4)전면에 나이트라이드(10)을 소정두께를 갖도록 데포지션한 후 (e)도에서와 같이 에치공정을 통해 나이트라이드(10)와 게이트폴리실리콘(4) 및 게이트옥사이드(3)을 필요치 않는 부분을 제거하여 게이트(5)를 형성한다.2 shows a silicide manufacturing process of a semiconductor memory cell according to the present invention. First, a field oxide film 2 is formed on a silicon substrate 1 ((a)) and then the silicon substrate 1 and a field oxide film are formed. (2) After the gate oxide film 3 is deposited on the front surface (cb), the gate polysilicon 4 is deposited on the gate oxide film 3 ((c)). After the process is completed, the nitride 10 is deposited to have a predetermined thickness on the entire surface of the gate polysilicon 4 as shown in (d), and then the nitride 10 is etched through the etch process as shown in (e). And the gate polysilicon 4 and the gate oxide 3 are removed to form the gate 5.
그 다음 (f)도와 같이 산화막(6)을 게이트(5) 전면에 데포지션한 후 상기 산화막(6)을 에치백하여 사이드월(7)을 형성한다.Next, as shown in (f), the oxide film 6 is deposited on the entire surface of the gate 5, and then the oxide film 6 is etched back to form a sidewall 7.
상기 공정 후 (g)도에서와 같이 산화막(6)과 실리콘기판(1)에 손상을 주지 않도록 나이트라이드(10)를 제거할 목적으로 인산에 담구어 습식식각을 실시한 다음 (h)도와 같이 전면에 걸쳐 메탈(8)을 증착한 후 습식식각공정을 실시하여 게이트폴리실리콘(4)과 실리콘기판(1)에 형성된 실리사이드(9)만을 남기고 나머지 메탈을 제거함으로써 실리사이드를 형성하는 공정으로 완료하게 된다.After the above process, as shown in (g), immersion in phosphoric acid and wet etching for the purpose of removing the nitride 10 so as not to damage the oxide film 6 and the silicon substrate 1 are performed. After depositing the metal (8) over the wet etching process is carried out to leave only the silicide (9) formed on the gate polysilicon (4) and the silicon substrate (1) to complete the process of forming the silicide by removing the remaining metal. .
제 3 도는 본 발명에 따른 실시예를 나타낸 반도체소자의 실리사이 드 형성 공정도로서, 반도체 메모리셀의 실리사이드 제조방법에 있어서, 실리콘기판에 필드산화막을 형성한 후 게이트산화막과 게이트폴리실리콘을 차례로 데포지션하는 단계와, 상기 게이트폴리실리콘 전면에 산화막을 데포지션하는 단계와, 상기 단계후 사진식각 공정으로 게이트를 정의하고 나이트라이드, 게이트폴리실리콘, 게이트산화막을 에치하여 게이트를 형성하는 단계와, 싱기 단계 후 나이트라이드를 전면에 데포지션하고 상기 나이트라이드를 에치백하여 나이트라이드사이드월을 형성하는 단계와, 상기 단계 후 게이트폴리실리콘위의 산화막을 제거하는 단계와, 상기 단계 후 메탈을 증착하고 어닐링한 후 습식식각으로 메탈을 식각하여 실리사이드를 형성하는 단계로 이루어진다.3 is a process diagram for forming a silicide of a semiconductor device according to an embodiment of the present invention. In the method for manufacturing a silicide of a semiconductor memory cell, after forming a field oxide film on a silicon substrate, the gate oxide film and the gate polysilicon are sequentially deposited. And depositing an oxide film on the entire surface of the gate polysilicon; defining a gate by a photolithography process after the step; forming a gate by etching nitride, gate polysilicon, and gate oxide film; Depositing a nitride on the front surface and etching back the nitride to form a nitride sidewall, removing the oxide film on the gate polysilicon after the step, and depositing and annealing the metal after the step. After etching the metal by wet etching to form a silicide Is done.
즉, 실리콘기판(1)에 필드산화막(2)을 형성한 다음 ((a)도) 상기 실리콘기판(1)과 필드산화막(2) 전면에 게이트산화막(3)을 증착한 후((b)도), 상기 게이트산화막(3) 위에 게이트폴리실리콘(4)을 데포지션한다.((c)도). 상기 공정이 완료되면 (d)도에서와 같이 게이트폴리실리콘(4)전면에 산화막(11)을 소정두께를 갖도록 데포지션한 후 (e)도에서와 같이 에치공정을 통해 산화막(11)과 게이트폴리실리콘(4) 및 게이트옥사이드(3)을 필요치 않는 부분을 제거하여 게이트(5)를 형성한다.That is, after forming the field oxide film 2 on the silicon substrate 1 ((a)) and then depositing a gate oxide film 3 on the silicon substrate 1 and the field oxide film 2 (b) Fig. 6) deposits a gate polysilicon 4 on the gate oxide film 3 (Fig. (C)). After the process is completed, the oxide film 11 is deposited on the entire surface of the gate polysilicon 4 as shown in (d) to have a predetermined thickness, and then, as shown in (e), the oxide film 11 and the gate are etched. A portion of the polysilicon 4 and the gate oxide 3 that is not needed is removed to form the gate 5.
그 다음 (f)도와 같이 나이트라이드(12)를 게이트(5) 전면에 데포지션한 후 상기 나이트라이드(12)를 에치백하여 나이트라이드사이드월(17)을 형성한다.Next, as shown in (f), the nitride 12 is deposited on the entire surface of the gate 5, and then the nitride 12 is etched back to form the nitride sidewall 17.
상기 공정 후 (g)도에서와 같이 나이트라이드(12)와 실리콘기판(1)에 손상을 주지 않도록 하면서 게이트폴리실리콘(4)위의 산화막(11)을 식각 하여제거 한 다음 (h)도와 같이 전면에 걸쳐 메탈(8)을 증착한 후 습식식각공정을 실시하여 게이트폴리실리콘(4)과 실리콘기판(1)에 형성된 실리사이드(9)만을 남기고 나머지 메탈을 제거함으로써 실리사이드를 형성하는 공정으로 완료하게 된다.After the process, as shown in (g), the oxide film 11 on the gate polysilicon 4 is etched and removed while not damaging the nitride 12 and the silicon substrate 1, as shown in (h). After depositing the metal 8 over the entire surface, the wet etching process is performed to leave only the silicide 9 formed on the gate polysilicon 4 and the silicon substrate 1 and to remove the remaining metal to complete the silicide formation process. do.
이상에서 상술한 바와 같이 본 발명은 나이트라이드 또는 산화막이 데포지션되는 두께만큼 수직방향으로 게이트의 길이를 증가시킨 후 실리사이드를 사이드월 내부에 형성되도록 하여 게이트폴리실리콘과 실리콘기판간의 거리를 최대로 확보함으로써 상기 게이트폴리실리콘과 실리콘기판에 흐르는 미세누설전류를 억제할 수 있는 효과를 제공할 수 있는 것이다.As described above, the present invention increases the length of the gate in the vertical direction by the thickness at which the nitride or oxide film is deposited, and then forms silicide inside the sidewall to secure the maximum distance between the gate polysilicon and the silicon substrate. By doing so, it is possible to provide an effect of suppressing a micro leakage current flowing in the gate polysilicon and the silicon substrate.
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| KR1019920010628A KR100244577B1 (en) | 1992-06-19 | 1992-06-19 | Manufacturing method for silicide of semiconductor memory cell |
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| KR19990007327A (en) * | 1997-06-26 | 1999-01-25 | 이데이 노부유키 | Manufacturing Method of Semiconductor Device |
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| JPS6489467A (en) * | 1987-09-30 | 1989-04-03 | Toshiba Corp | Manufacture of field-effect transistor |
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| JPS6489467A (en) * | 1987-09-30 | 1989-04-03 | Toshiba Corp | Manufacture of field-effect transistor |
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| KR19990007327A (en) * | 1997-06-26 | 1999-01-25 | 이데이 노부유키 | Manufacturing Method of Semiconductor Device |
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