KR100755054B1 - Method for forming the gate electrode in semiconductor device - Google Patents
Method for forming the gate electrode in semiconductor device Download PDFInfo
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- KR100755054B1 KR100755054B1 KR1020010079591A KR20010079591A KR100755054B1 KR 100755054 B1 KR100755054 B1 KR 100755054B1 KR 1020010079591 A KR1020010079591 A KR 1020010079591A KR 20010079591 A KR20010079591 A KR 20010079591A KR 100755054 B1 KR100755054 B1 KR 100755054B1
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 239000010703 silicon Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- -1 spacer nitride Chemical class 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000002245 particle Substances 0.000 abstract description 2
- 230000001629 suppression Effects 0.000 abstract 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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Abstract
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 실리콘기판 상에 금속 게이트전극 패턴을 형성하고, 그 패턴을 마스크로 하여 실리콘기판 표면에 이온을 주입하여 인위적으로 실리콘기판 표면에 데미지를 주어 비정질을 형성함으로써, 선택적 옥시데이션 공정 시, 실리콘기판 표면의 산화막 성장속도를 증가되어 실리콘기판 표면에 버퍼산화막을 형성하여 후속 질화막으로 형성된 스페이서가 실리콘기판에 접촉되는 것을 방지하여 게이트전극과 드레인 사이의 누설전류 증가를 억제하고 반도체소자의 리프레쉬(refresh) 특성 및 수율을 향상시킬 수 있게 하는 기술이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a metal gate electrode pattern is formed on a silicon substrate, and ion is implanted into the surface of the silicon substrate using the pattern as a mask to artificially damage the surface of the silicon substrate to form amorphous particles. By increasing the oxide film growth rate on the surface of the silicon substrate during the selective oxidization process, a buffer oxide film is formed on the surface of the silicon substrate to prevent the spacer formed of the subsequent nitride film from contacting the silicon substrate, thereby increasing the leakage current between the gate electrode and the drain. It is a technology that can suppress the suppression and improve the refresh characteristics and yield of the semiconductor device.
게이트전극, 버퍼 산화막, 선택적 옥시데이션, 이온주입Gate electrode, buffer oxide, selective oxidation, ion implantation
Description
도 1a 내지 도 1b는 종래 반도체소자의 게이트전극 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A through 1B are cross-sectional views sequentially illustrating a method of forming a gate electrode of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 게이트전극 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.
2A through 2D are cross-sectional views sequentially illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.
-- 도면의 주요부분에 대한 부호의 설명 -- -Explanation of symbols for the main parts of the drawing-
200 : 실리콘기판 210 : 금속 게이트전극 패턴200: silicon substrate 210: metal gate electrode pattern
212 : 게이트산화막 214 : 폴리실리콘막212: gate oxide film 214: polysilicon film
216 : 금속층 218 : 하드마스크216: metal layer 218: hard mask
219 : 반사방지막 220 : 감광막219: antireflection film 220: photosensitive film
230 : 이온 235 : 비정질화230: ion 235: amorphous
240 : 버퍼 산화막 250 : 스페이서 질화막
240: buffer oxide film 250: spacer nitride film
본 발명은 반도체소자 제조방법에 관한 것으로, 보다 상세하게는 실리콘기판 상에 금속 게이트전극 패턴을 형성하고, 실리콘기판 표면에 이온을 주입한 후, 선택적 옥시데이션 공정을 진행하여 실리콘기판 표면에 버퍼산화막을 형성함으로써, 후속 질화막으로 형성된 스페이서가 실리콘기판에 접촉되는 것을 방지하여 게이트전극과 드레인 사이의 누설전류 증가를 억제하고 반도체소자의 리프레쉬(refresh) 특성 및 수율을 향상시킬 수 있는 반도체소자의 게이트전극 형성방법에 관한 것이다. 수율을 향상시킬 수 있게 하는 기술이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to form a metal gate electrode pattern on a silicon substrate, implant ions into the surface of the silicon substrate, and then perform a selective oxidation process to perform a buffer oxide film on the surface of the silicon substrate. Gate electrode of the semiconductor device which can prevent the spacer formed by the subsequent nitride film from contacting the silicon substrate to suppress the leakage current increase between the gate electrode and the drain, and improve the refresh characteristics and the yield of the semiconductor device. It relates to a formation method. It is a technique that can improve the yield.
최근 게이트전극 물질로서 폴리실리콘 상부에 비저항이 낮으면서도 고온에서 텅스텐(W), 티타늄(Ti), 탄탈륨(Ta) 등의 고융점 금속을 추가한 금속 게이트전극을 형성하고 있으며, 그 중에서도 텅스텐을 사용한 금속 게이트는 소자의 고집적화에 따른 신호처리 속도 개선의 측면에서 기존 폴리사이드 게이트전극을 대체하고 있는 실정에 있다.Recently, as gate electrode materials, metal gate electrodes have been formed on top of polysilicon with high melting point metals such as tungsten (W), titanium (Ti), and tantalum (Ta) at a high temperature, with tungsten being used. Metal gates are replacing existing polyside gate electrodes in terms of improving signal processing speed due to high integration of devices.
도 1a 내지 도 1b는 종래 반도체소자의 게이트전극 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A through 1B are cross-sectional views sequentially illustrating a method of forming a gate electrode of a conventional semiconductor device.
도 1a에 도시된 바와 같이, 실리콘기판(100) 상에 게이트산화막(112), 폴리실리콘막(114), 텅스텐층(116)과 질화마스크(118) 및 반사방지막(119)를 순차적으로 적층한 후, 식각 공정에 의해 금속 게이트전극이 패터닝되어 금속 게이트전극 패턴(110)이 형성된다.
As shown in FIG. 1A, a
이때, 상기 금속 게이트전극 패터닝 시, 하부 게이트산화막(112)의 측벽에 손실이 유발되며, 이 손실을 복원하기 위해 게이트산화막(112)과 폴리실리콘막 (114) 측벽에 선택적 산화(oxidation)공정을 진행되어 버퍼 산화막(120)이 형성된다.At this time, when the metal gate electrode is patterned, a loss is caused on the sidewall of the lower
그리고, 상기 도 1b에 도시된 바와 같이, 상기 금속 게이트전극 패턴(110) 중 텅스텐층(116)의 산화를 방지하기 위해 버퍼 산화막(120)이 형성된 금속 게이트전극 패턴 측벽에 질화물을 이용하여 스페이서(130)를 형성하였다.As illustrated in FIG. 1B, a spacer is formed on the sidewall of the metal gate electrode pattern on which the
그러나, 상기 종래와 같은 반도체소자의 게이트전극 형성공정을 이용하게 되면, 금속 게이트전극 패턴 중 텅스텐층의 산화를 방지하기 위해 질화막으로 구성된 스페이서가 실리콘기판에 "A"와 같이 직접 접촉됨에 따라 실리콘기판에 스트레스를 가하여 전기적인 특성에 영향을 줌으로써 게이트전극과 드레인 사이의 누설전류 증가되는 문제점이 있었다.However, if the conventional gate electrode forming process of the semiconductor device is used, the silicon substrate is directly contacted with a spacer formed of a nitride film in order to prevent oxidation of the tungsten layer in the metal gate electrode pattern, such as "A". There is a problem that the leakage current between the gate electrode and the drain increases by applying stress to the electrical properties.
또한, 상기 누설전류의 증가로 인해 반도체소자의 리프레쉬(refresh) 특성을 열화되는 문제점이 있었다.
In addition, there is a problem in that the refresh characteristics of the semiconductor device is degraded due to the increase of the leakage current.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 실리콘기판 상에 게이트산화막, 폴리실리콘막, 금속막과 하드마스크 및 반사방지막을 순차적으로 적층하여 금속 게이트전극 패턴을 형성하고, 그 패턴을 마스크로 하여 실리콘기판 표면에 이온을 주입하여 인위적으로 실리콘기판 표면에 데 미지를 주어 비정질을 형성함으로써, 선택적 옥시데이션 공정 시, 실리콘기판 표면의 산화막 성장속도를 증가되어 실리콘기판 표면에 버퍼산화막을 형성하여 후속 질화막으로 형성된 스페이서가 실리콘기판에 접촉되는 것을 방지하여 게이트전극과 드레인 사이의 누설전류 증가를 억제하고, 반도체소자의 리프레쉬(refresh) 특성을 열화시키는 것을 방지하는 것이 목적이다.
The present invention has been made to solve the above problems, an object of the present invention is to form a metal gate electrode pattern by sequentially stacking a gate oxide film, a polysilicon film, a metal film and a hard mask and an antireflection film on a silicon substrate In addition, by implanting ions into the surface of the silicon substrate using the pattern as a mask, artificially damaging the surface of the silicon substrate to form amorphous particles, the growth rate of the oxide film on the surface of the silicon substrate is increased during the selective oxidation process, thereby increasing the surface of the silicon substrate. It is an object to form a buffer oxide film on the substrate to prevent the spacer formed of the nitride film from coming into contact with the silicon substrate, thereby preventing an increase in leakage current between the gate electrode and the drain, and preventing the refresh characteristic of the semiconductor device from deteriorating. .
상기 목적을 달성하기 위하여, 본 발명은 실리콘기판 상에 게이트산화막, 폴리실리콘막, 금속막과 하드마스크 및 반사방지막을 순차적으로 적층하고, 감광막을 도포한 후, 노광 및 식각공정을 진행하여 금속 게이트전극 패턴을 형성하는 단계와; 상기 감광막을 마스크로 하여 실리콘기판 표면에 이온을 주입하여 실리콘기핀 표면을 비정질화 하는 단계와; 상기 결과물에 선택적 옥시데이션 공정을 진행하여 실리콘기판 표면부터 금속 게이트전극 패턴의 폴리실리콘막 측벽까지 버퍼 산화막을 형성하는 단계와; 상기 결과물 상에 질화막을 증착한 후, 식각하여 금속 게이트전극 패턴 측벽에 스페이서 질화막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 게이트전극 형성방법을 제공한다.In order to achieve the above object, the present invention sequentially deposits a gate oxide film, a polysilicon film, a metal film, a hard mask and an antireflection film on a silicon substrate, and after applying a photoresist, proceeds with the exposure and etching process to the metal gate Forming an electrode pattern; Amorphizing the surface of the silicon pin by implanting ions onto the surface of the silicon substrate using the photosensitive film as a mask; Performing a selective oxidization process on the resultant to form a buffer oxide film from the surface of the silicon substrate to the sidewall of the polysilicon film of the metal gate electrode pattern; After depositing a nitride film on the resultant, and etching to form a spacer nitride film on the sidewall of the metal gate electrode pattern provides a method for forming a gate electrode of a semiconductor device.
바람직하게, 본 발명은 상기 이온 주입 시, 감광막을 제거하고 금속 게이트전극 패턴을 마스크로 하여 이온주입하는 것을 특징으로 한다.Preferably, the present invention is characterized in that during the ion implantation, the photosensitive film is removed and ion implantation is performed using the metal gate electrode pattern as a mask.
바람직하게, 본 발명은 이온 주입 시, O2, Si, Ge, Ar 이온 중 어느 하나의 이온을 선택하여 수직으로 1×1010 ~ 1×1017의 도즈량을 0.5 ~ 100 keV의 에너지로 주입하는 것을 특징으로 한다.
Preferably, in the ion implantation, one of the ions of O 2 , Si, Ge, and Ar is selected to inject a dose of 1 × 10 10 to 1 × 10 17 vertically with energy of 0.5 to 100 keV. Characterized in that.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체소자의 게이트전극 형성방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2D are cross-sectional views sequentially illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.
도 2a에 도시된 바와 같이, 실리콘기판(200) 상에 게이트산화막(212), 폴리실리콘막(214), 금속층(216)과 질화마스크(218) 및 반사방지막(219)을 순차적으로 적층하고, 감광막(220)을 도포한 후, 노광 및 식각공정을 진행하여 금속 게이트전극 패턴(210)을 형성하며, 이때, 상기 금속층(216)은 텅스텐을 사용하여 증착한다.As shown in FIG. 2A, a
그리고, 도 2b에 도시된 바와 같이, 상기 감광막(219)을 마스크로 하여 실리콘기판(200) 표면에 이온(230)을 주입하여 후속 선택적 옥시데이션 공정 시, 실리콘기판 표면에 버퍼산화막의 잘 형성되도록 실리콘기판 표면(200)을 비정질화(235)한다.As shown in FIG. 2B,
이때, 상기 이온(230) 주입 시, 감광막(219)을 제거하고 금속 게이트전극 패턴(210)을 마스크로 하여 이온(230) 주입하는 것이 가능하다.In this case, when the
또한, 상기 이온 주입 시, 사용되는 이온은 O2, Si, Ge, Ar 중 적어도 어느 하나의 이온을 선택하며, 선택된 이온을 수직으로 1×1010 ~ 1×1017의 도즈량을 0.5 ~ 100 keV의 에너지로 주입한다.In the ion implantation, at least one ion of O 2 , Si, Ge, and Ar is selected as the ion to be used, and a dose of 1 × 10 10 to 1 × 10 17 is 0.5 to 100 Inject with energy of keV.
이어서, 도 2c에 도시된 바와 같이, 상기 게이트산화막(212)과 폴리실리콘막 (214) 측벽 및 비정질화된 실리콘기판(200)의 표면에 550 ~ 1150℃ 의 온도로 5 ~ 10초 동안 선택적 산화(oxidation)공정을 진행하여 버퍼 산화막(220)을 형성하여 금속 게이트전극 패터닝 시, 손상된 하부 게이트산화막(112)의 측벽을 복원한다.Subsequently, as illustrated in FIG. 2C, the
이때, 선택적 옥시데이션 공정 시, O2 가스 또는 O2 와 H, N, Ar, N2O, NH3 중 어느 하나 이상의 가스가 혼합된 혼합가스 중 적어도 어느 하나를 선택하여 1 ~ 20 slm 정도 사용하여 진행하며, 램프 상승/하강율은 25 ~ 100℃/sec 로 하여 진행한다.In this case, in the selective oxidization process, at least one selected from O 2 gas or a mixed gas in which at least one of O 2 and H, N, Ar, N 2 O, and NH 3 is mixed is used for about 1 to 20 slm. And ramp up / down rate is 25 to 100 ° C./sec.
계속하여, 도 2d에 도시된 바와 같이, 상기 결과물 상에 질화물을 증착한 후, 식각공정을 진행하여 금속 게이트전극 패턴(210) 측벽에 스페이서 질화막(250)을 형성한다.
Subsequently, as illustrated in FIG. 2D, after the nitride is deposited on the resultant, an etching process is performed to form a
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 게이트전극 형성방법을 이용하게 되면, 실리콘기판 상에 금속 게이트전극 패턴을 형성하고, 그 패턴을 마스크로 하여 실리콘기판 표면에 이온을 주입하여 인위적으로 실리콘기판 표면에 데미지를 주어 비정질을 형성함으로써, 선택적 옥시데이션 공정 시, 실리콘기판 표면의 산화막 성장속도를 증가되어 실리콘기판 표면에 버퍼산화막을 형성하여 후속 질화막으로 형성된 스페이서가 실리콘기판에 접촉되는 것을 방지하여 게이트전 극과 드레인 사이의 누설전류 증가를 억제하고 반도체소자의 리프레쉬 특성 및 수율을 향상시킬 수 있는 효과가 있다.Therefore, as described above, when the gate electrode forming method of the semiconductor device according to the present invention is used, a metal gate electrode pattern is formed on the silicon substrate, and ion is implanted into the surface of the silicon substrate using the pattern as a mask to artificially By forming amorphous by giving damage to the surface of the silicon substrate, the growth rate of the oxide film on the surface of the silicon substrate is increased during the selective oxidation process to form a buffer oxide film on the surface of the silicon substrate so that the spacer formed by the subsequent nitride film is in contact with the silicon substrate This prevents the increase in leakage current between the gate electrode and the drain, and improves the refresh characteristics and yield of the semiconductor device.
Claims (7)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH102001A (en) * | 1996-06-15 | 1998-01-06 | Okajima Kogyo Kk | Grating |
| KR20010065161A (en) * | 1999-12-29 | 2001-07-11 | 박종섭 | Method of manufacturing a semiconductor device utilizing a gate dielelctric |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH102001A (en) * | 1996-06-15 | 1998-01-06 | Okajima Kogyo Kk | Grating |
| KR20010065161A (en) * | 1999-12-29 | 2001-07-11 | 박종섭 | Method of manufacturing a semiconductor device utilizing a gate dielelctric |
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| 공개공보 10-2001-65161 |
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