KR20010004242A - A method for forming electrode in semiconductor device - Google Patents
A method for forming electrode in semiconductor device Download PDFInfo
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- KR20010004242A KR20010004242A KR1019990024865A KR19990024865A KR20010004242A KR 20010004242 A KR20010004242 A KR 20010004242A KR 1019990024865 A KR1019990024865 A KR 1019990024865A KR 19990024865 A KR19990024865 A KR 19990024865A KR 20010004242 A KR20010004242 A KR 20010004242A
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000000151 deposition Methods 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 description 24
- 239000010410 layer Substances 0.000 description 15
- 230000009467 reduction Effects 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly to a method of forming an electrode during a semiconductor device manufacturing process.
반도체 소자가 고집적화됨에 따라 소자를 이루는 전극의 선폭 및 간극이 작아지게 되어 포토레지스트만으로는 미세 전극 형성에 어려움이 있다. 또한, 이에 따라 후속 마스크 공정의 오버레이(Overlay)에도 어려움이 있다.As semiconductor devices are highly integrated, line widths and gaps of electrodes constituting the devices become smaller, and thus only fine photoresists have difficulty in forming fine electrodes. In addition, there is also a difficulty in overlay of a subsequent mask process.
위와 같은 어려움을 해소하기 위하여 게이트 전극(워드라인), 비트라인 전극 등을 형성하는데 있어서, 통상 하드 마스크를 사용한 식각 공정이 실시되고 있으며, 이와 함께 자기정열 콘택(SAC)을 사용하여 콘택을 형성하고 있다. 하드 마스크 물질로는 산화막과 질화막등이 있으나 자기정렬 콘택 공정을 위해서는 질화막이 사용 되어진다.In order to solve the above-mentioned difficulties, in forming a gate electrode (word line), a bit line electrode, etc., an etching process using a hard mask is usually performed, and together with the self-aligned contact (SAC), a contact is formed. have. The hard mask material includes an oxide film and a nitride film, but a nitride film is used for the self-aligned contact process.
그러나, 질화막은 막의 스트레스가 심하여 첨부된 도면 도 1a 내지 도 1d에 도시된 바와 같이 막의 들뜸 현상이 나타나 그 하부에 완충막의 도입이 필요하였으며, 또한 반사율이 높아 마스크 작업의 용이성을 위하여 저반사층의 도입이 필요하였다.However, since the nitride film has a high stress on the film, as shown in FIGS. 1A to 1D, the film is lifted up, and thus, a buffer film needs to be introduced at the bottom thereof, and a high reflectance is required to introduce a low reflection layer for ease of mask operation. Was needed.
현재 개발되고 있는 소자의 경우, 첨부된 도면 도 2에 도시된 바와 같이 종래의 게이트 전극을 형성하기 위해서는 폴리실리콘막(20)/실리사이드막(21) 구조 상에 완충막으로 산화막(SiO2)(22)이 적층되고, 그 상부에 하드 마스크용 질화막(23) 및 저반사층인 산화질화막(SiON)(24)이 적층되어 사용되고 있다. 즉, 하드 마스크로 질화막(23)을 사용하기 위하여 추가로 2개의 막(22, 24)을 증착하여야 하며, 이는 장비 투자 및 비용 증가와 공정수 증가에 따른 수율 감소 등의 결과로 나타난다.In the case of a device currently being developed, in order to form a conventional gate electrode as shown in FIG. 2 of the accompanying drawings, an oxide film (SiO 2 ) as a buffer film on the polysilicon film 20 / silicide film 21 structure ( 22) is laminated, and a hard mask nitride film 23 and a low reflection layer (SiON) 24 are laminated and used. In other words, in order to use the nitride film 23 as a hard mask, two additional films 22 and 24 must be deposited, which is the result of increased equipment investment and cost and a decrease in yield due to an increase in the number of processes.
이러한 문제점을 제거하기 위하여 실리콘-리치(Si-Rich) 산화질화막(SiON) 단일막의 하드 마스크 공정 도입을 추진하였으나, 전기적 특성(전극간 절연성 특성 열화)이 나쁘게 나타나 적용이 불가능한 것으로 판명되어 현재까지는 하드 마스크용 질화막의 사용이 불가피하다.In order to eliminate this problem, the introduction of a hard mask process of a Si-Rich oxynitride (SiON) single layer was carried out, but the electrical characteristics (deterioration of the insulating properties between electrodes) were poor and proved inapplicable. Use of a mask nitride film is inevitable.
본 발명은 하드 마스크용 질화막 사용에 따른 추가적인 물질막의 적용을 최소화할 수 있는 반도체 소자의 전극 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming an electrode of a semiconductor device that can minimize the application of additional material film according to the use of the nitride film for hard mask.
도 1a 내지 도 1d는 각각 마스크 질화막의 들뜸 현상을 나타낸 주사전자현미경(SEM) 사진.1A to 1D are scanning electron microscope (SEM) photographs showing the lifting phenomenon of the mask nitride film, respectively.
도 2는 종래기술에 따른 게이트 전극 형성을 위한 적층 구조도.2 is a laminated structure diagram for forming a gate electrode according to the prior art.
도 3은 본 발명의 일 실시예에 따른 게이트 전극 형성을 위한 적층 구조도.3 is a laminated structure diagram for forming a gate electrode according to an embodiment of the present invention.
도 4a는 본 발명의 일 실시예에 따라 마스크 작업을 수행한 후의 산화질화막/질화막 구조의 주사전자현미경 사진.4A is a scanning electron micrograph of an oxynitride film / nitride film structure after performing a mask operation according to an embodiment of the present invention.
도 4b는 종래기술에 따라 마스크 작업을 수행한 후의 완충 산화막/마스크 질화막/저반사용 산화질화막 구조의 주사전자현미경 사진.Figure 4b is a scanning electron micrograph of the structure of the buffer oxide film / mask nitride film / low reflection oxynitride film after performing the mask operation according to the prior art.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
30 : 폴리실리콘막 31 : 실리사이드막30 polysilicon film 31 silicide film
32 : 산화질화막 33 : 마스크 질화막32: oxynitride film 33: mask nitride film
상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 반도체 소자의 전극 형성방법은, 소정의 하부층 상에 전극용 전도막을 형성하는 단계; 상기 전극용 전도막 상에 실리콘산화질화막을 형성하는 단계; 상기 산화질화막 상에 마스크 실리콘질화막을 형성하는 단계; 상기 마스크 실리콘질화막 상에 전극 형성을 위한 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 식각 베리어로 사용하여 상기 마스크 실리콘질화막 및 상기 실리콘산화질화막을 패터닝하는 단계; 및 상기 마스크 실리콘질화막 및 상기 실리콘산화질화막을 식각 베리어로 사용하여 상기 전극용 전도막을 패터닝하는 단계를 포함하여 이루어진다.The electrode forming method of the characteristic semiconductor device of the present invention for solving the above technical problem, forming a conductive film for the electrode on a predetermined lower layer; Forming a silicon oxynitride film on the electrode conductive film; Forming a mask silicon nitride film on the oxynitride film; Forming a photoresist pattern for forming an electrode on the mask silicon nitride film; Patterning the mask silicon nitride layer and the silicon oxynitride layer using the photoresist pattern as an etching barrier; And patterning the conductive film for the electrode using the mask silicon nitride film and the silicon oxynitride film as an etching barrier.
즉, 본 발명은 하드 마스크용 질화막의 스트레스를 완화시키기 위한 완충막과 저반사층막을 실리콘질화막 하나로 단일화시켰다. 질화막의 스트레스 완화용 막으로 현재 산화막이 사용되고 있으나, 산화질화막(SiON)도 완충 효과를 충분히 얻을 수 있다. 산화질화막은 마스크 질화막 상부에 존재하여 저반사층으로 사용되었으나, 반사율(Reflective Index) 측정 실험 결과, 질화막 하부에 존재하더라도 저반사층의 역할을 충분히 수행할 수 있는 것으로 나타났으며, 마스크 작업 결과도 양호하게 나타났다. 산화질화막은 반사율이 1.9인데, 질화막과 산화질화막의 두께를 조절할 경우 산화질화막의 반사율과 거의 비슷한 1.9 부근의 값을 얻을 수 있어 산화질화막/질화막의 이중막이 저반사층의 역할을 할 수 있는 것으로 나타났다.That is, in the present invention, the buffer film and the low reflection layer film for alleviating the stress of the nitride film for hard mask are unified with one silicon nitride film. Although an oxide film is currently used as a stress relaxation film of a nitride film, an oxynitride film (SiON) can sufficiently obtain a buffering effect. Although the oxynitride film was used as a low reflection layer on the upper surface of the mask nitride film, the reflectance (Reflective Index) measurement experiments showed that even if it exists below the nitride film, it can perform the role of the low reflection layer sufficiently, and the mask work result is satisfactory. appear. The oxynitride film has a reflectance of 1.9. When the thickness of the nitride film and the oxynitride film is adjusted, a value near 1.9 can be obtained, which is almost similar to the reflectance of the oxynitride film, so that the double layer of the oxynitride film / nitride film can serve as a low reflection layer.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 3은 본 발명의 일 실시예에 따른 게이트 전극 형성을 위한 적층 구조를 나타낸 것으로, 이하 이를 참조하여 설명한다.3 is a cross-sectional view illustrating a stacked structure for forming a gate electrode according to an exemplary embodiment of the present invention.
본 실시예에 따른 게이트 전극 형성 공정은 우선, 게이트 산화막(도시되지 않음)이 형성된 기판(도시되지 않음) 전체구조 상부에 폴리실리콘막(30)/실리사이드막(31) 구조를 적층시킨다.In the gate electrode forming process according to the present embodiment, first, a polysilicon film 30 / silicide film 31 structure is stacked on top of an entire structure of a substrate (not shown) on which a gate oxide film (not shown) is formed.
다음으로, 실리사이드막(31) 상에 산화질화막(32)을 증착한다. 이때, 산화질화막(32)은 스트레스 완충 및 저반사막의 역할을 수행하기 위한 것으로, 10∼2000Å 두께로 증착한다.Next, an oxynitride film 32 is deposited on the silicide film 31. At this time, the oxynitride film 32 is to perform the role of stress buffer and low reflection film, and is deposited to a thickness of 10 ~ 2000Å.
계속하여, 산화질화막(32) 상에 마스크 질화막(33)을 10∼2000Å 두께로 증착한다.Subsequently, a mask nitride film 33 is deposited on the oxynitride film 32 to a thickness of 10 to 2000 GPa.
이후, 포토레지스트를 도포하고, 게이트 전극용 포토마스크를 사용하여 포토레지스트 패턴(도시되지 않음)을 형성하고, 이를 식각 베리어로 사용하여 마스크 질화막(33) 및 산화질화막(32)을 패터닝하고, 이후 패터닝된 마스크 질화막(33) 및 산화질화막(32)을 식각 베리어로 사용하여 실리사이드막(31) 및 폴리실리콘막(30)을 차례로 식각함으로써 게이트 전극 패턴을 형성하게 된다.Thereafter, a photoresist is applied, a photoresist pattern (not shown) is formed using a photomask for a gate electrode, and the mask nitride film 33 and the oxynitride film 32 are patterned using the photoresist as an etching barrier, and then A gate electrode pattern is formed by sequentially etching the silicide layer 31 and the polysilicon layer 30 by using the patterned mask nitride layer 33 and the oxynitride layer 32 as etch barriers.
첨부된 도면 도 4a는 본 발명의 일 실시예에 따라 마스크 작업을 수행한 후의 산화질화막/질화막 구조의 주사전자현미경(SEM) 사진으로, 도 4b에 도시된 종래기술(완충 산화막/마스크 질화막/저반사용 산화질화막)과 비교할 때, 그 프로파일에 별 차이점을 발견할 수 없다. 즉, 산화질화막과 마스크 질화막이 저반사층의 역할을 수행하여 마스크 작업에 별 문제가 없음을 알 수 있다.4A is a scanning electron microscope (SEM) photograph of an oxynitride film / nitride film structure after performing a mask operation according to an embodiment of the present invention, and the prior art shown in FIG. 4B (buffered oxide film / mask nitride film / base) Compared with the oxynitride film used, no difference can be found in the profile. That is, the oxynitride film and the mask nitride film play a role of the low reflection layer, so it can be seen that there is no problem in the mask operation.
상기와 같은 공정을 실시하여 반도체 소자의 전극을 형성하는 경우, 종래기술에 비해 완충 산화막 증착 공정을 줄일 수 있어 제조 시간의 단축, 증착 장비의 투자비 감소로 인하여 반도체 소자의 생산 단가를 줄일 수 있다. 또한 공정 하나를 단축시킴으로써 결함의 감소 효과도 나타나 수율 및 신뢰도를 향상시킬 수 있다.In the case of forming the electrode of the semiconductor device by performing the above process, it is possible to reduce the buffer oxide film deposition process compared to the prior art, it is possible to reduce the production cost of the semiconductor device due to shortening the manufacturing time, investment cost of the deposition equipment. In addition, the shortening of one process also shows the effect of reducing defects, thereby improving yield and reliability.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 게이트 전극 형성시를 일례로 들어 설명하였으나, 본 발명의 산화질화막/질화막 구조는 비트라인 형성시에도 적용될 수 있다.For example, in the above-described embodiment, the gate electrode is formed as an example, but the oxynitride / nitride structure of the present invention can be applied to the formation of the bit line.
전술한 본 발명은 기존에 비해 완충 산화막 증착 공정을 생략할 수 있으며, 이로 인하여 반도체 제조 시간의 단축, 증착 장비의 투자비 감소를 통한 생산성 향상 및 생산 단가 절감의 효과가 있다. 또한 공정 단축에 따른 결함 감소를 통해 반도체 소자의 수율 및 신뢰도 향상을 기대할 수 있다.The present invention described above can omit the buffer oxide film deposition process as compared to the conventional, thereby reducing the semiconductor manufacturing time, the productivity improvement through the reduction of the investment cost of the deposition equipment and the production cost reduction effect. In addition, yield reduction and reliability of semiconductor devices can be expected by reducing defects due to process shortening.
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