KR20010004591A - Method of etching hard mask layer in semiconductor device - Google Patents
Method of etching hard mask layer in semiconductor device Download PDFInfo
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- KR20010004591A KR20010004591A KR1019990025285A KR19990025285A KR20010004591A KR 20010004591 A KR20010004591 A KR 20010004591A KR 1019990025285 A KR1019990025285 A KR 1019990025285A KR 19990025285 A KR19990025285 A KR 19990025285A KR 20010004591 A KR20010004591 A KR 20010004591A
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- hard mask
- film
- layer
- mask layer
- photoresist pattern
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- 238000005530 etching Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 35
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 238000001020 plasma etching Methods 0.000 claims abstract description 24
- 229910021350 transition metal silicide Inorganic materials 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000007789 gas Substances 0.000 claims description 36
- 239000001257 hydrogen Substances 0.000 claims description 28
- 229910052739 hydrogen Inorganic materials 0.000 claims description 28
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 18
- 150000002431 hydrogen Chemical class 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 88
- 229910021341 titanium silicide Inorganic materials 0.000 description 8
- 229920000642 polymer Polymers 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
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- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 게이트 전극 제조방법에 관한 것으로, 보다 구체적으로는 반도체 소자의 게이트 전극을 제조하는데 사용되는 하드 마스크막의 식각 방법에 관한 것이다.The present invention relates to a method for manufacturing a gate electrode of a semiconductor device, and more particularly to an etching method of a hard mask film used to manufacture a gate electrode of a semiconductor device.
일반적으로, 게이트 전극은 모스 트랜지스터를 셀렉팅하는 전극으로서, 주로 불순물이 도핑된 폴리실리콘막으로 형성되거나 또는 불순물이 도핑된 폴리실리콘막과 텅스텐 실리사이드막(WSi2)의 적층막으로 형성된다.In general, the gate electrode is an electrode for selecting a MOS transistor, and is mainly formed of a polysilicon film doped with impurities or a laminated film of a polysilicon film and a tungsten silicide film WSi 2 doped with impurities.
그러나, 상기한 불순물이 도핑된 폴리실리콘막과 불순물이 도핑된 폴리실리콘막/텅스텐 실리사이드막은 낮은 집적도를 갖는 반도체 소자에는 용이하게 사용되나, 현재의 고집적 반도체 소자의 미세 게이트 전극으로는 낮은 저항값 특성을 만족시키지 못하여, 이를 사용하는데 어려움이 있다.However, the above-described impurity doped polysilicon film and impurity-doped polysilicon film / tungsten silicide film are easily used in semiconductor devices having low integration, but have low resistance value characteristics as the fine gate electrodes of the current highly integrated semiconductor devices. There is a difficulty in using it because it is not satisfied.
이에 종래에는 전도 특성이 우수한 티타늄 실리사이드막(TiSi2)을 폴리실리콘막 상부에 적층하여 게이트 전극을 형성하는 방법이 제안되었는데, 이에 대하여 첨부도면 도 1을 참조하여 설명한다.In the related art, a method of forming a gate electrode by stacking a titanium silicide layer (TiSi 2 ) having excellent conductive properties on a polysilicon layer has been proposed, which will be described with reference to FIG. 1.
도면을 참조하여, 반도체 기판(1) 상부에 게이트 산화막(2)을 열성장 또는 증착 방식에 의하여 형성한다음, 게이트 산화막(2) 상부에 불순물이 도핑된 폴리실리콘막(3)을 소정두께로 증착한다. 도핑된 폴리실리콘막(3) 상부에 물리적 증착 방식으로 티타늄 실리사이드막(4)을 형성한다. 티타늄 실리사이드막(4) 상부에 고집적 소자에서 하드 마스크막(5)이 형성된다. 이때, 하드 마스크막(5)은 공지된 바와 같이 난반사 방지의 역할과 자기 정렬 콘택의 역할을 동시에 수행하도록, 실리콘 질산화막(5a)과 실리콘 질화막(5b)이 적층되어 이루어진다.Referring to the drawings, the gate oxide film 2 is formed on the semiconductor substrate 1 by thermal growth or vapor deposition, and then the polysilicon film 3 doped with impurities on the gate oxide film 2 is formed to a predetermined thickness. Deposit. The titanium silicide film 4 is formed on the doped polysilicon film 3 by physical vapor deposition. A hard mask film 5 is formed on the titanium silicide film 4 in the highly integrated device. At this time, the hard mask film 5 is formed by stacking the silicon oxynitride film 5a and the silicon nitride film 5b so as to simultaneously perform the role of preventing diffuse reflection and self-aligning contact.
그후, 하드 마스크막(5) 상부에 공지의 포토리소그라피 공정을 이용하여, 게이트 전극을 한정하기 위한 레지스트 패턴(도시되지 않음)을 형성한다. 레지스트 패턴을 마스크로 하여 하드 마스크막(5)을 식각하고, 하드 마스크막(5)의 형태로, 티타늄 실리사이드막(4)과 폴리실리콘막(3)을 식각하여, 게이트 전극을 형성한다.Thereafter, a resist pattern (not shown) for defining the gate electrode is formed on the hard mask film 5 by using a known photolithography process. The hard mask film 5 is etched using the resist pattern as a mask, and the titanium silicide film 4 and the polysilicon film 3 are etched in the form of the hard mask film 5 to form a gate electrode.
종래의 하드 마스크막(5)은 대게 수소(hydrogen)가 포함된 플라즈마 식각 가스, 예를들어, Ar/CF4/CHF3등의 가스에 의하여 식각된다. 그러나, 이러한 수소가 포함된 플라즈마 식각 가스에 의하여 식각이 진행되면, 티타늄 실리사이드막의 식각시 발생되는 폴리머와 상기 수소 성분이 결합하게 된다. 이 폴리머 결합물은 쉽게 제거되지 않고, 기판에 고착되어, 패턴 결함을 유발하게 된다.The conventional hard mask film 5 is usually etched by a plasma etching gas containing hydrogen, for example, a gas such as Ar / CF 4 / CHF 3 . However, when etching is performed by the plasma etching gas containing hydrogen, the hydrogen component is bonded to the polymer generated during the etching of the titanium silicide layer. This polymer bond is not easily removed and sticks to the substrate, causing pattern defects.
이와같은 패턴 결함의 문제점을 해소하기 위하여, 종래의 다른 방법으로는 수소를 포함하지 않는 가스, 예를들어 Ar/CF4/O2식각 가스를 이용하여 하드 마스크막(5)을 식각하는 방법이 제안되었다. 그러나, 이와같이 수소를 포함하지 않는 플라즈마 식각 가스는 하드 마스크막(5)과 포토레지스트 패턴(도시되지 않음)과의 식각 선택비가 매우 낮으므로, 포토레지스트 패턴 및 하드 마스크막(5)이 쉽게 유실된다. 이로 인하여, 하드 마스크막(5)의 본래의 목적을 달성하기 어렵다.In order to solve the problem of such a pattern defect, another conventional method is to etch the hard mask film 5 using a gas that does not contain hydrogen, such as an Ar / CF 4 / O 2 etching gas. Proposed. However, the plasma etching gas containing no hydrogen has a very low etching selectivity between the hard mask film 5 and the photoresist pattern (not shown), so that the photoresist pattern and the hard mask film 5 are easily lost. . For this reason, it is difficult to achieve the original objective of the hard mask film 5.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 패턴 결함을 방지하면서, 하드 마스크막의 유실을 방지할 수 있는 반도체 소자의 하드 마스크막 식각방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a hard mask film etching method of a semiconductor device capable of preventing a loss of a hard mask film while preventing a pattern defect while preventing the above-mentioned conventional problem.
도 1은 종래의 반도체 소자의 게이트 전극을 나타낸 단면도.1 is a cross-sectional view showing a gate electrode of a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 하드 마스크막 식각 방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a hard mask film etching method of a semiconductor device according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 반도체 기판 12 : 게이트 산화막11 semiconductor substrate 12 gate oxide film
13 : 폴리실리콘층 14 : 티타늄 실리사이드막13: polysilicon layer 14: titanium silicide film
15a : 실리콘 질산화막 15b : 실리콘 질화막15a: silicon nitride film 15b: silicon nitride film
16 : 포토레지스트 패턴16: photoresist pattern
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 반도체 기판상에 게이트 산화막, 도전성의 폴리실리콘층, 전이 금속 실리사이드막을 순차적으로 증착하는 단계; 상기 전이 금속 실리사이드막 상부에 실리콘 질산화막으로 된 제 1 하드 마스크막을 형성하는 단계; 상기 제 1 하드 마스크막 상부에 실리콘 질화막으로 된 제 2 하드 마스크막을 형성하는 단계; 상기 제 2 하드 마스크막 상부에 게이트 전극용 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 마스크로 하여, 상기 제 1 하드 마스크막을 수소를 포함하는 플라즈마 식각 가스로 제거하는 단계; 및 상기 포토레지스트 패턴을 마스크로 하여, 상기 제 2 하드 마스크막을 수소가 포함되지 않은 플라즈마 식각 가스로 제거하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention comprises the steps of sequentially depositing a gate oxide film, a conductive polysilicon layer, a transition metal silicide film on a semiconductor substrate; Forming a first hard mask layer of a silicon nitride oxide layer on the transition metal silicide layer; Forming a second hard mask film made of a silicon nitride film on the first hard mask film; Forming a photoresist pattern for a gate electrode on the second hard mask layer; Removing the first hard mask layer with a plasma etching gas containing hydrogen using the photoresist pattern as a mask; And removing the second hard mask layer with a plasma etching gas containing no hydrogen, using the photoresist pattern as a mask.
이때, 상기 수소를 포함하는 플라즈마 식각 가스는 Ar/CF4/CHF3또는 Ar/CHF3가스이고, 상기 수소를 포함하지 않는 플라즈마 식각 가스는 Ar/CF4/O2또는 Ar/CF4가스인 것을 특징으로 한다.In this case, the plasma etching gas containing hydrogen is an Ar / CF 4 / CHF 3 or Ar / CHF 3 gas, the plasma etching gas containing no hydrogen is Ar / CF 4 / O 2 or Ar / CF 4 gas It is characterized by.
아울러, 상기 제 2 하드 마스크막을 형성하는 단계 이후에, 상기 포토레지스트 패턴의 형태로 전이 금속 실리사이드막, 폴리실리콘층 및 게이트 산화막을 식각하는 단계: 및 상기 포토레지스트 패턴을 제거하는 단계를 더 포함하는 것을 특징으로 한다.Further, after the forming of the second hard mask layer, etching the transition metal silicide layer, the polysilicon layer, and the gate oxide layer in the form of the photoresist pattern; and removing the photoresist pattern. It is characterized by.
본 발명에 의하면, 실리콘 질산화막, 실리콘 질화막으로 된 하드 마스크막 제거시, 실리콘 질화막은 포토레지스트 패턴과 식각 선택비가 우수한 수소를 포함하는 플라즈마 식각 가스로 제거하고, 실리콘 질산화막은 전이 금속 실리사이드막과의 반응이 최소화되도록 수소를 포함하지 않은 가스로 식각을 진행한다.According to the present invention, upon removal of the silicon nitride oxide film and the silicon nitride film, the silicon nitride film is removed with a plasma etching gas containing hydrogen having a good photoresist pattern and an etching selectivity, and the silicon nitride film is separated from the transition metal silicide film. Etch with a gas that does not contain hydrogen to minimize the reaction.
이에따라, 전이 금속 실리사이드막의 폴리머와 플라즈마 식각 가스의 수소 성분과의 반응이 방지되어, 패턴 결함을 일으키는 폴리머의 발생이 저지된다. 또한, 수소를 포함하지 않는 플라즈마 식각 가스로는 박막의 실리콘 질산화막만을 제거하므로, 실리콘 질화막 및 포토레지스트 패턴이 유실되지 않는다.As a result, the reaction between the polymer of the transition metal silicide film and the hydrogen component of the plasma etching gas is prevented, and generation of the polymer causing the pattern defect is prevented. In addition, since only the silicon nitride oxide film of the thin film is removed from the plasma etching gas containing no hydrogen, the silicon nitride film and the photoresist pattern are not lost.
(실시예)(Example)
이하 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
첨부된 도면 도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 하드 마스크막 식각 방법을 설명하기 위한 단면도이다.2A through 2C are cross-sectional views illustrating a hard mask film etching method of a semiconductor device according to the present invention.
먼저, 도 2a를 참조하여, 반도체 기판(11) 상부에 열산화 기법으로 게이트 산화막(12)를 형성한다. 그 다음, 게이트 산화막(12) 상부에 소정의 불순물이 첨가된 폴리실리콘층(13)을 증착하고, 폴리실리콘층(13) 상부에 공지의 방식으로 전이 금속 실리사이드막(14)을 형성한다. 본 실시예에서는 전이 금속 실리사이드막(14)으로 티타늄 실리사이드막을 이용한다. 티타늄 실리사이드막(14) 상부에는 자기 정렬 콘택을 용이하게 하고, 난반사를 방지하기 위하여 하드 마스크막(15)을 형성한다. 본 실시예에서의 하드 마스크막(15)은 실리콘 질산화막(15a)과 실리콘 질화막(15b)의 적층막으로 이루어진다. 여기서, 실리콘 질산화막(15a)은 이후 진행되는 포토리소그라피 공정시 난반사를 방지하는 역할을 하고, 실리콘 질화막(15b)은 이후 형성될 비트 라인과 워드 라인(게이트 전극)을 절연시키는 역할을 한다. 이어서, 실리콘 질화막(15b) 상부에 공지의 포토리소그라피 방식으로 게이트 전극 한정용 포토레지스트 패턴(16)을 형성한다.First, referring to FIG. 2A, a gate oxide film 12 is formed on the semiconductor substrate 11 by thermal oxidation. Then, the polysilicon layer 13 to which the predetermined impurity is added is deposited on the gate oxide film 12, and the transition metal silicide film 14 is formed on the polysilicon layer 13 in a known manner. In this embodiment, a titanium silicide film is used as the transition metal silicide film 14. A hard mask film 15 is formed on the titanium silicide film 14 to facilitate self-alignment contact and to prevent diffuse reflection. The hard mask film 15 in this embodiment consists of a laminated film of the silicon nitride oxide film 15a and the silicon nitride film 15b. Here, the silicon nitride oxide film 15a serves to prevent diffuse reflection in the subsequent photolithography process, and the silicon nitride film 15b insulates the bit line and the word line (gate electrode) to be formed later. Subsequently, a gate electrode defining photoresist pattern 16 is formed on the silicon nitride film 15b by a known photolithography method.
그리고나서, 포토레지스트 패턴(16)을 마스크로 하여, 우선적으로 하드 마스크막(15)을 제거한다. 이때, 상술한 하드 마스크막(15)의 식각시 발생되는 문제점을 방지하기 위하여, 본 실시예에서는 1차적으로, 노출된 실리콘 질화막(15b)만을 수소가 포함된 플라즈마 식각 가스, 예를들어 Ar/CF4/CHF3또는 Ar/CHF3가스로 식각한다. 여기서, 실리콘 질화막(15b)의 식각 종말점을 체크하여, 실리콘 질화막(15b)만이 선택적으로 제거되도록 한다. 여기서, 수소가 포함된 플라즈마 식각 가스로 상면의 실리콘 질화막(15b)만을 제거하므로, 전이 금속 실리사이드막(13)이 노출되지 않는다. 이에따라, 플라즈마 식각 가스의 수소 성분과 전이 금속 실리사이드막의 폴리머와 반응되지 않아, 패턴 결함이 발생되지 않는다.Then, using the photoresist pattern 16 as a mask, the hard mask film 15 is first removed. At this time, in order to prevent the above-described problem occurring during the etching of the hard mask layer 15, in the present embodiment, only the exposed silicon nitride layer 15b may include a plasma etching gas including hydrogen, for example, Ar / Etch with CF 4 / CHF 3 or Ar / CHF 3 gas. Here, the etching end point of the silicon nitride film 15b is checked so that only the silicon nitride film 15b is selectively removed. Here, since only the silicon nitride film 15b on the upper surface of the plasma etching gas containing hydrogen is removed, the transition metal silicide film 13 is not exposed. Accordingly, the hydrogen component of the plasma etching gas does not react with the polymer of the transition metal silicide film, so that no pattern defect occurs.
그 다음으로, 도 2b에 도시된 바와 같이, 실리콘 질화막(15b)의 제거로 노출된 실리콘 질산화막(15b)을 수소를 포함하지 않은 플라즈마 식각 가스, 예를들어, Ar/CF4/O2가스 또는 Ar/CF4가스로 식각한다. 이때, 실리콘 질산화막(15b)을 수소를 포함하지 않는 플라즈마 식각 가스로 제거하는 것은, 실리콘 질산화막(15b)이 전이 금속 실리사이드막(14)과 접촉되어 있으므로, 수소 성분과 전이 금속 실리사이드막(14)간의 반응을 최소화하기 위함이다. 여기서, 수소를 포함하지 않은 플라즈마 식각 가스를 사용할때, 포토레지스트 패턴과의 식각 선택비는 여전히 우수하지 않지만, 박막의 실리콘 질산화막(15b)을 단시간동안 식각하는 것이므로, 포토레지스트 패턴(16) 및 잔여 실리콘 질화막(15b)에 영향을 미치지 않는다.Subsequently, as shown in FIG. 2B, the silicon nitride oxide film 15b exposed by the removal of the silicon nitride film 15b is exposed to a plasma etching gas containing no hydrogen, for example, an Ar / CF 4 / O 2 gas. Or etched with Ar / CF 4 gas. At this time, the removal of the silicon nitride oxide film 15b with the plasma etching gas containing no hydrogen is because the silicon nitride oxide film 15b is in contact with the transition metal silicide film 14, and thus the hydrogen component and the transition metal silicide film 14 This is to minimize the reaction between). Here, when using the plasma etching gas containing no hydrogen, the etching selectivity with the photoresist pattern is still not excellent, but since the silicon nitride oxide film 15b of the thin film is etched for a short time, the photoresist pattern 16 and It does not affect the remaining silicon nitride film 15b.
그후, 도 2c에서와 같이, 전이 금속 실리사이드막(14), 폴리실리콘막(13) 및 게이트 산화막(12)을 공지의 방법으로 포토레지스트 패턴(16)을 이용하여 식각한다. 그리고나서, 포토레지스트 패턴(16)을 공지의 방식으로 제거한다.Thereafter, as shown in FIG. 2C, the transition metal silicide film 14, the polysilicon film 13, and the gate oxide film 12 are etched using the photoresist pattern 16 by a known method. The photoresist pattern 16 is then removed in a known manner.
이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 실리콘 질산화막(15a), 실리콘 질화막(15b)으로 된 하드 마스크막(15) 제거시, 실리콘 질화막(15b)은 포토레지스트 패턴(16)과 식각 선택비가 우수한 수소를 포함하는 플라즈마 식각 가스로 제거하고, 실리콘 질산화막(15a)은 전이 금속 실리사이드막(14)과의 반응이 최소화되도록 수소를 포함하지 않은 가스로 식각을 진행한다.As described above in detail, according to the present invention, when the hard mask film 15 made of the silicon nitride oxide film 15a and the silicon nitride film 15b is removed, the silicon nitride film 15b selects the photoresist pattern 16 and the etching. The plasma etch gas containing hydrogen having excellent rain ratio is removed, and the silicon oxynitride film 15a is etched with a gas not containing hydrogen so that the reaction with the transition metal silicide layer 14 is minimized.
이에따라, 전이 금속 실리사이드막(14)의 폴리머와 플라즈마 식각 가스의 수소 성분과의 반응이 방지되어, 패턴 결함을 일으키는 폴리머의 발생이 저지된다. 또한, 수소를 포함하지 않는 플라즈마 식각 가스로는 박막의 실리콘 질산화막(15a)만을 제거하므로, 실리콘 질화막(15b) 및 포토레지스트 패턴이 유실되지 않는다.As a result, the reaction between the polymer of the transition metal silicide film 14 and the hydrogen component of the plasma etching gas is prevented, and generation of the polymer causing the pattern defect is prevented. In addition, since only the silicon nitride oxide film 15a of the thin film is removed as the plasma etching gas containing no hydrogen, the silicon nitride film 15b and the photoresist pattern are not lost.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100452273B1 (en) * | 2002-10-22 | 2004-10-08 | 삼성전자주식회사 | Method of cleaning a processing chamber and method of manufacturing a semiconductor device |
| KR100739965B1 (en) * | 2005-12-28 | 2007-07-16 | 동부일렉트로닉스 주식회사 | Method of etching for semiconductor device fabrication |
| KR100782479B1 (en) * | 2001-12-17 | 2007-12-05 | 삼성전자주식회사 | Method for Forming Mask having SiN |
| KR101053990B1 (en) * | 2008-08-01 | 2011-08-04 | 주식회사 하이닉스반도체 | Pattern formation method of semiconductor device |
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| US5545588A (en) * | 1995-05-05 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of using disposable hard mask for gate critical dimension control |
| KR0139245B1 (en) * | 1995-06-05 | 1998-06-15 | 신재인 | Electrolyting method and apparatus by using the mercury pack electrode of vertical circulating capillary type |
| KR0163536B1 (en) * | 1995-10-25 | 1999-02-01 | 김광호 | Method of forming contact hole in semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100782479B1 (en) * | 2001-12-17 | 2007-12-05 | 삼성전자주식회사 | Method for Forming Mask having SiN |
| KR100452273B1 (en) * | 2002-10-22 | 2004-10-08 | 삼성전자주식회사 | Method of cleaning a processing chamber and method of manufacturing a semiconductor device |
| KR100739965B1 (en) * | 2005-12-28 | 2007-07-16 | 동부일렉트로닉스 주식회사 | Method of etching for semiconductor device fabrication |
| KR101053990B1 (en) * | 2008-08-01 | 2011-08-04 | 주식회사 하이닉스반도체 | Pattern formation method of semiconductor device |
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