JPH04219975A - Manufacture of static ram - Google Patents

Abstract

PURPOSE:To make the groove in a semiconductor substrate shallow even when it is formed due to the difference in a film thickness of a gate electrode between a buried contact part and a non-buried contact part by performing a selective etching operation in order to pattern the gate electrode of a mask polysilicon contact type static RAM. CONSTITUTION:A mask silicon film is formed to be amorphous by a low- temperature CVD operation. Since the mask silicon film is amorphous, it can display a mask effect against an etchant even when its film thickness is made thin. In addition, since the difference in the film thickness between a buried contact part and a non-buried contact part can be reduced, the groove in a semiconductor substrate can be made shallow.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a static RAM, and more particularly to a method of manufacturing a masked silicon buried contact type static RAM.

0002

[Prior Art] As a static SRAM, a semiconductor substrate is opened by etching a gate insulating film using a mask polysilicon film as a mask, and then a polysilicon film is formed on top of the polysilicon film. There is a method in which a gate electrode is formed by forming a contact with an electrode, that is, a buried contact, forming a refractory metal film on top of the two-layer polysilicon film, and selectively etching this film.

FIG. 2 is a sectional view showing a buried contact in the middle of manufacturing such a static SRAM. In the drawing, 1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a mask polysilicon film, 4 is a polysilicon film (1Poly) formed as the upper silicon film of the mask polysilicon film 3, and 5 is the polysilicon film. 4 and a buried contact portion with the semiconductor substrate 1; 6 is a refractory metal silicide (for example, tungsten silicide) film; the film 6 and the two layers of polysilicon films 3 and 4 constitute a polycide gate electrode. .

Reference numeral 7 denotes a groove formed in the surface of the semiconductor substrate 1 by etching for patterning a gate electrode. This groove 7 is inevitably generated as a side effect due to the difference in film thickness between the buried contact portion and the other portion of the silicon gate electrode integrated with the two layers 3 and 4. The film thickness difference is the film thickness of the mask silicon film 3, and the depth of the groove 7 is proportional to the film thickness difference, that is, the film thickness of the mask silicon film 3.

[0005]

[Problem to be Solved by the Invention] Incidentally, the groove 7, which inevitably occurs in a mask-buried contact type static SRAM, separates the source or drain region from the gate electrode diffusion region. This becomes a factor and also causes deterioration of flatness. Therefore, it is not desirable and it is necessary to make it as shallow as possible. However, in the past, it was difficult to make it shallow. This is because, as is clear from the above, in order to make the groove 7 shallower, it is necessary to make the mask silicon film 3 thinner.
This is because if the thickness of the gate insulating film 2 under the mask silicon film 3 is made thinner, the gate insulating film 2 under the mask silicon film 3 is more likely to be eroded by the pretreatment performed before forming the polysilicon film 4 by CVD. This point will be explained in detail as follows.

That is, the mask polysilicon film 3 is patterned, and the gate insulating film 2 is etched using the mask polysilicon film 3 as a mask (specifically, the field insulating film and the resist film also serve as masks) to form a buried contact. After forming the opening for polysilicon film (1Poly) 4
Before forming by CVD, it is necessary to remove the natural oxide film formed on the surface of the opening by wet etching. However, this etching solution is not suitable for the mask silicon film 3.
Therefore, if the mask silicon film 3 is thin, it will reach the gate insulating film 2 under the mask silicon film 3, causing a problem that the gate withstand voltage will decrease. Therefore, the mask silicon film 3 cannot be made very thin, and the actual situation requires a film thickness of at least 500 angstroms. Therefore, as mentioned above, there is a restriction on making the groove 7 shallower.

The present invention has been made to solve these problems, and it is possible to make the mask silicon film effective as a mask against wet etching even if the film thickness is thin, and by extension to form a gate electrode. The purpose of this invention is to make it possible to make shallow the grooves caused by the difference in the thickness of the silicon film between the buried contact and the other parts by selective etching.

[0008]

[Means for solving the problems] Static RA of the present invention
The manufacturing method of M is characterized in that the mask silicon film is formed by CVD so as to become amorphous.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a static RAM according to the present invention will be explained in detail below according to the illustrated embodiments. FIGS. 1A to 1E are cross-sectional views showing one embodiment of a method for manufacturing a static RAM according to the present invention in the order of steps. (A) As shown in FIG. 1A, a mask silicon film 3a is formed on the gate insulating film 2 on the surface of the semiconductor substrate 1 by CVD. This CVD process is performed at a low temperature of 575° C. or lower, and the film thickness is made thinner than conventional ones, for example, to 400 angstroms.

CVD under low temperature conditions of 575°C or less
The reason for performing this is to make the film quality of the mask silicon film 3a amorphous. The film quality of the mask silicon film 3a is made amorphous by a natural oxide film (described later).
This is to strengthen the permeation resistance of the etching solution for wet etching 9), so that a sufficient masking effect can be exerted on the gate insulating film 2 even if the film is thinner than before. That is, when a silicon film is grown by ordinary CVD at a temperature of 600° C. or higher, a polysilicon film is formed, but since the polysilicon film is strictly porous, it cannot be said that the etching resistance is sufficiently high. Therefore,
It was necessary to increase the thickness of the mask silicon film to a certain extent. However, if the temperature during CVD is lower than 575° C., the film quality becomes amorphous and denseness appears. Therefore, the permeation resistance of the etching liquid becomes stronger, and even if the film thickness is made thinner, the permeation resistance of the etching liquid can be increased. The reason for reducing the thickness of the mask silicon film 3a is as follows.
This is to make the groove 7 formed in the substrate 1 shallower as described above.

(B) Next, the mask silicon film 3a is patterned, and then, as shown in FIG. 1(B), the gate insulating film 2 is etched using the mask silicon film 3a and the resist film 8 as a mask. Buried contact part 5
expose. (C) Next, in order to remove the native oxide film 9 naturally formed on the surface of the buried contact portion 5, light wet etching is performed using an etching solution 10 as shown in FIG. 1C. (D) Next, as shown in FIG. 1D, a polysilicon film (1Poly) 4 is formed by CVD, and a tungsten silicide film 6 is further formed. (E) After that, as shown in (E) of FIG.
Patterning is performed by selectively etching the gate electrodes 6, 4, and 3a using 1 as a mask. Then,
Although the gate electrodes 6, 4, and 3a are patterned, grooves 7 are formed on the surface of the semiconductor substrate 1 as a side effect.

This groove 7 is caused by the difference in film thickness between the buried contact portion of the gate electrode and the non-buried contact portion, and the difference in film thickness is the thickness of the mask silicon film 3a.
As mentioned above, the depth of the groove 7 is proportional to this, but in this static RAM manufacturing method, the thickness of the mask silicon film 3a is made thinner, so the groove 7 formed is
It only needs to be shallow. In fact, the groove 7 could be made shallower by 20% or more than before.

[0013]

[Effects of the Invention] The method for manufacturing a static RAM of the present invention is characterized in that the method for manufacturing a mask polysilicon buried contact type static RAM is characterized in that the mask silicon film is formed by CVD in which the film quality becomes amorphous. . Therefore, the static RA of the present invention
According to the manufacturing method M, since the mask silicon film is formed in an amorphous state, it can have stronger resistance to etching solution than a porous polysilicon film. Therefore, even if the mask silicon film is thin, the mask effect against etching for removing the native oxide film on the surface of the buried contact region, which is performed as a pretreatment for CVD of the polysilicon film formed as the upper layer of the mask silicon film, can be exerted. be able to. Therefore, it becomes possible to make the groove in the semiconductor substrate shallow, the depth of which is proportional to the thickness of the mask silicon film.

[Brief explanation of the drawing]

[Fig. 1] (A) to (E) are static RAMs of the present invention.
FIG. 3 is a cross-sectional view showing one embodiment of the manufacturing method in the order of steps.

FIG. 2 is a sectional view for explaining a conventional example.

[Explanation of symbols]

1 Semiconductor substrate 2 Gate insulating film 3a Amorphous mask silicon film 4 Polysilicon film (1Poly) 5 Buried contact region 7 Groove formed in the substrate

Claims (1)

[Claims] 1. A mask silicon film is formed on the surface of a semiconductor substrate via a gate insulating film, the gate insulating film is etched using the mask silicon film as a mask to open the semiconductor substrate surface, and a polysilicon film is further formed. In the method for manufacturing a static RAM in which a buried contact is formed with the surface of the semiconductor substrate through the opening, and the two-layer silicon film is used as a silicon gate electrode, the mask silicon film is formed by CVD so that the film quality becomes amorphous. A method for manufacturing a static RAM characterized by