KR20030049590A - Method for forming transistor of semiconductor decice - Google Patents
Method for forming transistor of semiconductor decice Download PDFInfo
- Publication number
- KR20030049590A KR20030049590A KR1020010079832A KR20010079832A KR20030049590A KR 20030049590 A KR20030049590 A KR 20030049590A KR 1020010079832 A KR1020010079832 A KR 1020010079832A KR 20010079832 A KR20010079832 A KR 20010079832A KR 20030049590 A KR20030049590 A KR 20030049590A
- Authority
- KR
- South Korea
- Prior art keywords
- gate oxide
- film
- psg film
- solution
- oxide layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims description 12
- 238000004140 cleaning Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000012298 atmosphere Substances 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 239000005360 phosphosilicate glass Substances 0.000 abstract description 21
- 238000005468 ion implantation Methods 0.000 abstract description 12
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- OYLRFHLPEAGKJU-UHFFFAOYSA-N phosphane silicic acid Chemical compound P.[Si](O)(O)(O)O OYLRFHLPEAGKJU-UHFFFAOYSA-N 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 게이트 전극 형성 후 PSG(Phospho-silicate glass) 필름을 증착하여 어닐링 함으로써 PSG 필름내에 존재하는 P(인) 성분의 불순물을 확산시켜 LDD를 위한 이온 주입 공정을 생략하고 얕은 접합을 형성할 수 있는 반도체 소자의 트랜지스터 형성 방법에 관한 것이다.According to the present invention, after forming a gate electrode, a PSG (Phospho-silicate glass) film is deposited and annealed to diffuse impurities of the P (phosphorus) component present in the PSG film, thereby eliminating an ion implantation process for LDD and forming a shallow junction. The present invention relates to a method for forming a transistor of a semiconductor device.
일반적으로, 반도체 메모리 소자인 디램은 하나의 캐패시터와 하나의 트랜지스터로 구성된다.In general, a DRAM, a semiconductor memory device, is composed of one capacitor and one transistor.
이때, 상기 트랜지스터는 반도체소자가 고집적화 됨에 따라 소자의 크기가 감소하는데 소자의 크기 특히 게이트의 길이가 작은 MOSFET 에서 상기 소자의 특성 열화는 매우 중요해 진다.At this time, the transistor size of the transistor decreases as the semiconductor device is highly integrated. In the MOSFET having a small size, especially a gate length, deterioration of the device characteristic becomes very important.
이와 같은 소자의 특성열화를 줄이기 위하여 여러가지 구조를 사용하는데 대표적인 것이 엘.디.디. ( LDD : light dopeddrain, 이하에서 LDD 라 함 ) 구조이다. 상기 LDD 구조는 가볍게 불순물을 주입시켜 드레인을 형성한 것으로서 채널의 전계를 감소시켜 소자의 특성열화를 감소시킨다.In order to reduce the deterioration of the characteristics of such a device, a typical structure is used L.D.D. (LDD: light doped drain, hereinafter referred to as LDD) structure. The LDD structure is a lightly implanted impurity to form a drain to reduce the electric field of the channel to reduce the deterioration of the characteristics of the device.
도1a 내지 도1d는 종래 기술에 의한 반도체 소자의 트랜지스터 제조 공정을 나타낸 단면도들이다.1A to 1D are cross-sectional views illustrating a transistor manufacturing process of a semiconductor device according to the prior art.
먼저, 도1a에 도시된 바와 같이 반도체 기판(10) 상부에 게이트 산화막(11) 및 게이트 전극(12)을 차례로 증착한 후 감광막 패턴(13)을 형성한다.First, as shown in FIG. 1A, the gate oxide film 11 and the gate electrode 12 are sequentially deposited on the semiconductor substrate 10, and then the photoresist pattern 13 is formed.
그런 다음, 도1b에 도시된 바와 같이 상기 감광막 패턴(13)을 이용하여 게이트 산화막(11) 및 게이트 전극(12)을 식각하여 패터닝 한 후 도1c에 도시된 바와같이 후속 이온 주입 공정시 데미지와 채널링을 방지하기 위하여 희생산화막(14)으로 비정질 산화막을 증착한다.Next, as shown in FIG. 1B, the gate oxide layer 11 and the gate electrode 12 are etched and patterned using the photoresist pattern 13, and then, as shown in FIG. In order to prevent channeling, an amorphous oxide layer is deposited on the sacrificial oxide layer 14.
이어서, 도1d에 도시된 바와 같이 희생 산화막(14)이 형성된 결과물 상에 불순물 이온 주입 공정을 통해 LDD(lightly doped drain : 15)를 형성한다.Subsequently, as shown in FIG. 1D, a lightly doped drain (LDD) 15 is formed through the impurity ion implantation process on the resultant product on which the sacrificial oxide film 14 is formed.
그러나, 이러한 종래 기술에 의해 LDD를 형성하게 되면 하부층에 남아있는 게이트 산호막의 두께가 균일하지 않아 LDD 이온 주입 공정의 프로필이 불안하여 누설 전류를 유발하고 이온 주입에 의한 데미지로 인해 게이트 산화막의 특성을 저하시키는 문제가 있었다.However, when the LDD is formed by the conventional technology, the thickness of the gate coral film remaining in the lower layer is not uniform, resulting in an unstable profile of the LDD ion implantation process, causing leakage current, and the characteristics of the gate oxide film due to damage caused by ion implantation. There was a problem of deterioration.
또한, 이온 주입후 후속 공정인 사이드월 스페이서 증착할 때 균일성의 문제로 인해 스페이서 식각 마진이 부족한 문제가 있었다.In addition, when the sidewall spacer is deposited after the ion implantation, there is a problem that the spacer etching margin is insufficient due to the uniformity problem.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 게이트 전극 형성 후 PSG(Phospho-silicate glass) 필름을 증착하여 어닐링 함으로써 PSG 필름내에 존재하는 P(인) 성분의 불순물을 확산시켜 LDD를 위한 이온 주입 공정을 생략하고 얕은 접합을 형성할 수 있는 반도체 소자의 트랜지스터 형성 방법을 제공하는 것이다.The present invention has been made to solve the above problems, and an object of the present invention is to deposit an annealing by depositing a phospho-silicate glass (PSG) film after annealing to form an impurity of a P (phosphorus) component present in the PSG film. It is to provide a method of forming a transistor of a semiconductor device that can be diffused to omit an ion implantation process for LDD and form a shallow junction.
도1a 내지 도1d는 종래 기술에 의한 반도체 소자의 트랜지스터 제조 공정을 나타낸 단면도들이다.1A to 1D are cross-sectional views illustrating a transistor manufacturing process of a semiconductor device according to the prior art.
도2a 내지 도2d는 본 발명에 의한 반도체 소자의 트랜지스터 제조 공정을 나타낸 단면도들이다.2A to 2D are cross-sectional views illustrating a transistor manufacturing process of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
20 : 반도체 기판 21 : 게이트 산화막20 semiconductor substrate 21 gate oxide film
22 : 게이트 전극 24 : 감광막 패턴22 gate electrode 24 photosensitive film pattern
25 : 소오스/드레인 영역25 source / drain regions
상기와 같은 목적을 실현하기 위한 본 발명은 반도체 기판 상부에 게이트 산화막 및 게이트 전극을 차례로 증착한 후 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 이용하여 게이트 산화막 및 게이트 전극을 식각하여 패터닝 하고 HF+H2O 용액을 이용하여 잔류된 게이트 산화막을 제거하는 단계와, 상기 잔류된 게이트 산화막이 제거된 결과물 상에 P이 도핑된 PSG 필름을 증착하는 단계와, 상기 PSG 필름이 형성된 결과물 상에 어닐링 공정을 진행하여 불순물인 P을 실리콘 기판에 확산시킨 후 HF+H2O 용액을 이용한 세정 공정을 진행하여 PSG 필름을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.According to an aspect of the present invention, a gate oxide film and a gate electrode are sequentially deposited on a semiconductor substrate to form a photoresist pattern, and the gate oxide film and the gate electrode are etched and patterned using the photoresist pattern, and HF Removing the remaining gate oxide film using a + H 2 O solution, depositing a P-doped PSG film on the resultant product from which the remaining gate oxide film is removed, and annealing the resultant product on which the PSG film is formed. The process of the present invention relates to a method for manufacturing a transistor of a semiconductor device, comprising the step of diffusing P as an impurity onto a silicon substrate and then performing a cleaning process using an HF + H 2 O solution to remove the PSG film.
이때, 상기 HF+H2O 용액을 이용한 세정 공정 대신 BOE 용액을 이용한 세정 공정을 진행하고, 상기 PSG 필름은 불순물 농도를 1wt%~100wt%의 농도로 200~900℃의 온도 범위 내에서 100~10000Å의 두께로 LP-CVD 또는 PE-CVD 방식을 이용하여 증착하는 것을 특징으로 한다.At this time, the cleaning process using a BOE solution instead of the cleaning process using the HF + H 2 O solution, the PSG film is 100 ~ within the temperature range of 200 ~ 900 ℃ at a concentration of 1wt% ~ 100wt% impurity concentration It is characterized in that the deposition using a LP-CVD or PE-CVD method with a thickness of 10000Å.
또한, 상기 어닐링 공정은 N2분위기 또는 Ar 분위기에서 500~1000℃의 온도 범위 내에서 10초~100분 정도로 실시하고, 상기 어닐링 공정은 대기압 또는 1Torr 이하의 저압에서 실시하는 것을 특징으로 한다.In addition, the annealing process is carried out in a temperature range of 500 ~ 1000 ℃ in N 2 atmosphere or Ar atmosphere for about 10 seconds to 100 minutes, the annealing process is characterized in that carried out at atmospheric pressure or low pressure of 1Torr or less.
또한, 상기 P를 이용한 PSG필름 대신에 보론 계열의 불순물을 이용하여 P-형 LDD를 형성하는 것을 특징으로 한다.In addition, the P-type LDD may be formed by using boron-based impurities instead of the PSG film using P.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as the conventional configuration using the same reference numerals and names.
도2a 내지 도2d는 본 발명에 의한 반도체 소자의 트랜지스터 제조 공정을 나타낸 단면도들이다.2A to 2D are cross-sectional views illustrating a transistor manufacturing process of a semiconductor device according to the present invention.
먼저, 도2a에 도시된 바와 같이 반도체 기판(20) 상부에 게이트 산화막(21) 및 게이트 전극(22)을 차례로 증착한 후 감광막 패턴(23)을 형성한다.First, as shown in FIG. 2A, the gate oxide film 21 and the gate electrode 22 are sequentially deposited on the semiconductor substrate 20, and then the photoresist pattern 23 is formed.
그런 다음, 도2b에 도시된 바와 같이 상기 감광막 패턴(23)을 이용하여 게이트 산화막(21) 및 게이트 전극(22)을 식각하여 패터닝 하고 HF+H2O 용액을 이용하여 잔류된 게이트 산화막을 제거한 후 도2c에 도시된 바와 같이 P(인)이 도핑된 PSG(Phospho-silicate glass : 24) 필름을 100~10000Å의 두께로 증착한다.Next, as shown in FIG. 2B, the gate oxide film 21 and the gate electrode 22 are etched and patterned using the photoresist pattern 23, and the remaining gate oxide film is removed using an HF + H 2 O solution. Then, as shown in FIG. 2C, a PG (phosphorus-silicate glass) doped PSG film is deposited to a thickness of 100 to 10000 mm 3.
이때, 상기 HF+H2O 용액 대신 BOE 용액을 이요하여 세정 공정을 진행 할 수 있고, 상기 PSG 필름(24)은 불순물을 1~100wt%의 농도로 200~900℃의 온도 범위 내에서 LP-CVD 또는 PE-CVD 방식을 이용하여 증착한다.In this case, the cleaning process may be performed by using a BOE solution instead of the HF + H 2 O solution, and the PSG film 24 has an impurity concentration of 1-100 wt% in the range of 200-900 ° C. Deposition using CVD or PE-CVD method.
이어서, 도2d에 도시된 바와 같이 PSG 필름(24)이 형성된 결과물 상에 어닐링 공정을 진행하여 불순물인 P(인)을 실리콘 기판에 확산시킴으로써 소오스/드레인 영역(15)를 형성시킨 후 세정 공정을 진행하여 PSG 필름(24)을 제거한다.Next, as shown in FIG. 2D, an annealing process is performed on the resultant on which the PSG film 24 is formed to diffuse the impurity P (phosphorus) onto the silicon substrate to form the source / drain regions 15, and then the cleaning process may be performed. Proceeding to remove the PSG film 24.
이때, 상기 어닐닝 공정은 N2또는 Ar 분위기에서 500~1000℃의 온도로 10초~100분간 실시한다.At this time, the annealing process is performed for 10 seconds to 100 minutes at a temperature of 500 ~ 1000 ℃ in N 2 or Ar atmosphere.
또한, 상기 어닐링 공정은 대기압 또는 1Torr 이하의 저압에서 실시한다.In addition, the annealing process is carried out at atmospheric pressure or low pressure of 1 Torr or less.
상기한 바와 같이 본 발명은 게이트 전극 형성 후 PSG(Phospho-silicate glass) 필름을 증착하여 어닐링 함으로써 PSG 필름내에 존재하는 P(인) 성분의 불순물을 확산시켜 LDD를 위한 이온 주입 공정을 생략하고 얕은 접합을 형성할 수 있어 이온 주입에 따른 데미지가 없기 때문에 누설 전류를 감소시킬 수 있으며 자기 확산을 이용하기 때문에 숏 채널 소자에서도 활용이 가능한 이점이 있다.As described above, in the present invention, after forming the gate electrode, a PSG film is deposited and annealed to diffuse impurities of P (phosphorus) present in the PSG film, thereby eliminating an ion implantation process for the LDD, and shallow bonding. Since there is no damage due to ion implantation, leakage current can be reduced, and self-diffusion can be used, and thus it can be utilized in short channel devices.
또한, 이온 주입 공정을 생략함으로써 이온 주입에 의한 측면 확산을 방지하여 숏 채널 효과를 방지하고 PSG 필름을 전면에 증착하기 때문에 이온 주입시 발생되는 활성 영역과의 분리막 경계에서 발생되는 누설 소스가 없어져 소자 분리 공정 마진이 확보되어 소자의 수율을 향상시킬 수 있는 이점이 있다.In addition, by eliminating the ion implantation process, the side diffusion caused by the ion implantation is prevented to prevent the short channel effect and the PSG film is deposited on the entire surface, thereby eliminating the leakage source generated at the boundary of the separator from the active region generated during the ion implantation. Separation process margin is secured, there is an advantage that can improve the yield of the device.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010079832A KR20030049590A (en) | 2001-12-15 | 2001-12-15 | Method for forming transistor of semiconductor decice |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010079832A KR20030049590A (en) | 2001-12-15 | 2001-12-15 | Method for forming transistor of semiconductor decice |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030049590A true KR20030049590A (en) | 2003-06-25 |
Family
ID=29575387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010079832A KR20030049590A (en) | 2001-12-15 | 2001-12-15 | Method for forming transistor of semiconductor decice |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030049590A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416310A (en) * | 2019-06-26 | 2019-11-05 | 西交利物浦大学 | A kind of film transistor device and preparation method improving radiation resistance with hydrogen peroxide |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08186082A (en) * | 1994-12-28 | 1996-07-16 | Nec Corp | Manufacture of semiconductor device |
| KR960026929A (en) * | 1994-12-16 | 1996-07-22 | 김주용 | Transistor Manufacturing Method |
| KR19990005997A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Manufacturing method of semiconductor device |
| KR20010008563A (en) * | 1999-07-02 | 2001-02-05 | 김영환 | Method for fobricating a transistor of a semiconductor device |
-
2001
- 2001-12-15 KR KR1020010079832A patent/KR20030049590A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960026929A (en) * | 1994-12-16 | 1996-07-22 | 김주용 | Transistor Manufacturing Method |
| JPH08186082A (en) * | 1994-12-28 | 1996-07-16 | Nec Corp | Manufacture of semiconductor device |
| KR19990005997A (en) * | 1997-06-30 | 1999-01-25 | 김영환 | Manufacturing method of semiconductor device |
| KR20010008563A (en) * | 1999-07-02 | 2001-02-05 | 김영환 | Method for fobricating a transistor of a semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110416310A (en) * | 2019-06-26 | 2019-11-05 | 西交利物浦大学 | A kind of film transistor device and preparation method improving radiation resistance with hydrogen peroxide |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20010063781A (en) | Fabricating method for semiconductor device | |
| KR19980084215A (en) | Method of manufacturing transistor of semiconductor device | |
| KR20050070932A (en) | Fabricating method of semiconductor device | |
| KR20030049590A (en) | Method for forming transistor of semiconductor decice | |
| KR20030049602A (en) | Method for forming transistor of semiconductor decice | |
| KR19980046001A (en) | Semiconductor device and manufacturing method thereof | |
| KR100336771B1 (en) | Transistor forming method | |
| KR100244413B1 (en) | Method for forming source/drain of semiconductor device | |
| KR100680943B1 (en) | Method for forming transistor in semiconductor device | |
| KR0124642B1 (en) | Manufacture of semiconductor device | |
| KR100239723B1 (en) | Method for manufacturing semiconductor device | |
| KR100368971B1 (en) | Gate of soi device and method for fabricating the same | |
| KR930011176B1 (en) | Manufacturing method of semiconductor device with ldd structure | |
| KR0175035B1 (en) | Method of manufacturing metal silicide gate electrode using double spacer | |
| KR100503745B1 (en) | Method for fabricating semiconductor device | |
| KR100540339B1 (en) | Method For Making Gate Structure In The Semiconductor Device Manufacture Processing | |
| KR100223795B1 (en) | Manufacturing method of semiconductor memory device | |
| KR100429229B1 (en) | Method for Fabricating of Semiconductor Device | |
| JPH11176959A (en) | Manufacture of semiconductor device | |
| KR100223918B1 (en) | Structure of semiconductor devices and the manufacturing method thereof | |
| KR101024339B1 (en) | Semiconductor device and method for fabricating the same | |
| KR930009477B1 (en) | Manufacturing method of impurity region in semiconductor device | |
| KR100689677B1 (en) | A semiconductor device and method for manufacturing the same | |
| KR100274341B1 (en) | Method of manufacturing a semiconductor device | |
| KR100477542B1 (en) | Method of manufacturing short-channel transistor in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |