KR100274341B1 - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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KR100274341B1
KR100274341B1 KR1019970028489A KR19970028489A KR100274341B1 KR 100274341 B1 KR100274341 B1 KR 100274341B1 KR 1019970028489 A KR1019970028489 A KR 1019970028489A KR 19970028489 A KR19970028489 A KR 19970028489A KR 100274341 B1 KR100274341 B1 KR 100274341B1
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gate electrode
silicon substrate
tungsten silicide
forming
high concentration
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KR1019970028489A
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Korean (ko)
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KR19990004398A (en
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박민규
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors

Abstract

PURPOSE: A fabrication method of a semiconductor devices is provided to prevent current losses and structural defects of a gate electrode by oxidation processing using He gas after forming the gate electrode of polycide structure. CONSTITUTION: After forming a gate oxide(3) on a silicon substrate(1), a polycide gate electrode stacked a polysilicon layer(4) and a tungsten silicide(5) is formed on the gate oxide. By implanting lightly doped dopants into the entire surface of the silicon substrate, the structural defects of the tungsten silicide(5) are removed and a lightly doped impurity region(6) is formed in the silicon substrate. After forming spacers(7) at both sidewalls of the polycide gate electrode, NMOS source and drain regions(9) are formed by implanting heavily doped dopants. An oxidation process is performed at He gas atmosphere. PMOS source and drain regions(11) are formed by implanting heavily doped dopants.

Description

반도체 소자의 제조 방법{Method of manufacturing a semiconductor device}Method of manufacturing a semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 폴리실리콘과 텅스텐 실리사이드의 이중 구조의 게이트 전극을 갖는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a double structure gate electrode of polysilicon and tungsten silicide.

반도체 소자의 게이트 물질로 종전에는 폴리실리콘이 주로 사용되어 왔으나 소자의 집적도가 증가함에 따라 빠른 속도를 요구하게 되어 금속 물질인 텅스텐 실리사이드를 폴리실리콘 상부에 증착한 폴리사이드 구조를 사용한다. 이러한 폴리실리콘과 텅스텐 실리사이드 구조를 이용하여 게이트 전극을 형성하기 위한 공정은 다음과 같다. 폴리실리콘 상부에 텅스텐 실리사이드를 증착한 후 패터닝하여 게이트 전극을 형성하고, 폴리실리콘 산화 공정에 의해 결정 재구조를 형성한 후 저농도 N형 불순물 주입 공정을 실시한다. 그러면 불순물이 주입되는 부분의 텅스텐 실리사이드는 불순물 주입에 의한 손상에 의해 다시 비정질 상태가 되고 불순물이 주입되지 않는 부분의 텅스텐 실리사이드는 결정 재구조를 갖추게 된다. 이 상태에서 900℃의 온도에서 산화 공정을 실시한다. 여기서 산소를 제외한 상태에서 텅스텐 실리사이드를 관찰하면 이온이 주입되지 않은 텅스텐 실리사이드에 침전/석출이 심하게 나타난다. 이러한 텅스텐 실리사이드의 침전/석출에 의해 게이트 전극의 전류 손실 및 후속 공정후의 패터닝시 단차에 의한 구조적 결함이 발생하게 된다.In the past, polysilicon has been mainly used as a gate material of a semiconductor device, but as the integration degree of the device increases, a high speed is required, and thus a polyside structure in which tungsten silicide, which is a metal material, is deposited on the polysilicon is used. The process for forming the gate electrode using the polysilicon and tungsten silicide structure is as follows. After depositing tungsten silicide on the polysilicon and patterning it, a gate electrode is formed, a crystal restructure is formed by a polysilicon oxidation process, and then a low concentration N-type impurity implantation process is performed. Then, the tungsten silicide in the portion where the impurity is implanted becomes amorphous again by damage caused by the impurity implantation, and the tungsten silicide in the portion where the impurity is not implanted has a crystal restructure. In this state, an oxidation process is performed at a temperature of 900 ° C. When tungsten silicide is observed in the state excluding oxygen, precipitation / precipitation is severely observed in tungsten silicide to which ions are not implanted. Due to the precipitation / precipitation of the tungsten silicide, structural defects due to the current loss of the gate electrode and the step difference in the patterning after the subsequent process are generated.

따라서, 본 발명은 텅스텐 실리사이드의 침전 및 석출 발생을 억제하여 상술한 문제점을 해결할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above-described problems by suppressing the precipitation and precipitation of tungsten silicide.

상술한 목적을 달성하기 위한 본 발명은 실리콘 기판 상부에 폴리실리콘 및 텅스텐 실리사이드가 적층된 폴리사이드 구조의 게이트 전극을 형성하는 단계와, 상기 실리콘 기판의 전면에 저농도의 불순물을 주입하는 단계와, 상기 게이트 전극 측면에 스페이서를 형성한 후 실리콘 기판의 선택된 영역에 고농도의 N형 불순물을 주입하는 단계와, 헬륨 가스 분위기에서 산화 공정을 실시하는 단계와, 상기 실리콘 기판중 고농도의 N형 불순물이 주입되지 않은 영역에 고농도의 P형 불순물을 주입하는 단계로 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a gate electrode having a polyside structure in which polysilicon and tungsten silicide are stacked on a silicon substrate, and implanting a low concentration of impurities into the entire surface of the silicon substrate; After forming a spacer on the side of the gate electrode, implanting a high concentration of N-type impurities in the selected region of the silicon substrate, performing an oxidation process in a helium gas atmosphere, and a high concentration of N-type impurities in the silicon substrate is not implanted Injecting a high concentration of P-type impurities in the non-region.

도 1(a) 내지 도 1(d)는 본 발명의 일 실시 예에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film

3 : 게이트 산화막 4 : 폴리실리콘막3: gate oxide film 4: polysilicon film

5 : 텅스텐 실리사이드막 6 : 저농도 N형 불순물 주입 영역5: tungsten silicide film 6: low concentration N-type impurity implantation region

7 : 스페이서 8 : 제 1 마스크7: spacer 8: first mask

9 : NMOS 소오스/드레인 영역9: NMOS source / drain area

10 : 제 2 마스크 11 : PMOS 소오스/드레인 영역10 second mask 11 PMOS source / drain region

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

도 1(a) 내지 도 1(d)는 본 발명의 일 실시 예에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도로서, CMOS 트랜지스터를 예로 설명하기로 한다.1A to 1D are cross-sectional views of devices sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, and a CMOS transistor will be described as an example.

도 1(a)에 도시된 바와 같이 실리콘 기판(1) 상의 선택된 영역에 필드 산화막(2)을 형성한다. 전체 구조 상부에 게이트 산화막(3), 폴리실리콘막(4) 및 텅스텐 실리사이드막(5)을 순차적으로 형성한다. 텅스텐 실리사이드막(5)은 WF6와 SiH4를 350∼450℃에서 350 mTorr 정도의 낮은 압력에서 증착하며, 이때의 텅스텐 실리사이드의 조성비가 W1Si2.5로 되게 가스량을 조절하여 약 1500Å의 두께로 증착한다. 폴리실리콘막(4)의 산화 공정을 실시한 후 마스크 및 식각 공정에 의해 텅스텐 실리사이드막(5), 폴리실리콘막(4) 및 게이트 산화막(3)을 선택적으로 식각하여 게이트 구조를 형성한다. 이후 마스크 공정없이 불순물을 주입하는 블랭킷 방법으로 저농도의 N형 불순물을 주입하여 텅스텐 실리사이드막(5)이 비정질 구조를 갖게 하는 한편 노출된 실리콘 기판(1)상에 저농도 불순물 주입 영역(6)을 형성한다. 이때 주입되는 저농도의 N형 불순물로 인(phosphorus) 이온을 1.3×1015의 양으로 30keV의 에너지에서 주입한다.As shown in FIG. 1A, a field oxide film 2 is formed in a selected region on the silicon substrate 1. The gate oxide film 3, the polysilicon film 4, and the tungsten silicide film 5 are sequentially formed on the entire structure. The tungsten silicide film 5 deposits WF 6 and SiH 4 at a low pressure of 350 mTorr at 350 to 450 ° C., and adjusts the amount of gas so that the composition ratio of tungsten silicide is W 1 Si 2.5 to a thickness of about 1500 kPa. Deposit. After the oxidation process of the polysilicon film 4 is performed, the tungsten silicide film 5, the polysilicon film 4, and the gate oxide film 3 are selectively etched by a mask and an etching process to form a gate structure. Thereafter, a low concentration N-type impurity is implanted by a blanket method in which impurities are implanted without a mask process so that the tungsten silicide layer 5 has an amorphous structure, and a low concentration impurity implantation region 6 is formed on the exposed silicon substrate 1. do. At this time, phosphorus (phosphorus) ions are implanted at an energy of 30 keV in an amount of 1.3 × 10 15 as low concentration N-type impurities to be injected.

도 1(b)에 도시된 바와 같이 전체 구조 상부에 산화막을 LPCVD 방법으로 500∼600℃에서 증착한 후 전면 식각하여 게이트 구조의 측벽에 스페이서(7)를 형성한다. 이렇게 하면 텅스텐 실리사이드막(5)이 헥사고날(hexagonal) 구조 및 약간의 테트라고날(tetragonal) 구조를 갖게 된다. 그리고 전체 구조 상부에 감광막을 도포한 후 마스크 및 식각 공정을 실시하여 PMOS 트랜지스터가 형성될 지역에만 제 1 마스크(8)를 형성한다. 그리고 전면에 고농도의 N형 불순물을 주입한다. 이렇게 하면 NMOS 트랜지스터 영역에 형성된 저농도 불순물 주입 영역(6)을 침투하여 고농도 불순물 주입 영역이 형성되므로 소오스/드레인 영역(9)이 형성된다. 이때 고농도 불순물로 비소 이온을 1.8×1015의 양으로 60keV의 에너지 상태에서 주입한다. 제 1 마스크(8)을 제거한 후 산화 공정을 실시하여 실리콘 및 비소가 비정질 상태에서 재결정 구조를 가지게 한다. 그리고 텅스텐 실리사이드막(5)을 2차적으로 어닐하여 테트라고날 구조가 형성되게 하여 완전한 결정 구조를 갖게 만든다. 이때 산화 공정은 900℃의 LPCVD 장비에서 분위기 가스로서 He를 주입시켜 실시한다. 이렇게 하면 산소가 폴리실리콘막(4)과 반응하여 SiO2가 형성되거나 텅스텐 실리사이드막(5)의 실리콘 성분이 산소와 반응하여 텅스텐 실리사이드막 결정비, 즉 조성비가 불안정하게 되지 않는다.As shown in FIG. 1B, an oxide film is deposited on the entire structure at 500 to 600 ° C. by LPCVD, and then etched to form a spacer 7 on the sidewall of the gate structure. This causes the tungsten silicide film 5 to have a hexagonal structure and a slight tetragonal structure. After the photoresist is applied over the entire structure, a mask and an etching process are performed to form the first mask 8 only in the region where the PMOS transistor is to be formed. And a high concentration of N-type impurities are injected into the front side. This penetrates the low concentration impurity implantation region 6 formed in the NMOS transistor region to form a high concentration impurity implantation region, so that the source / drain region 9 is formed. At this time, as a high concentration of impurities, arsenic ions are implanted in an energy state of 60 keV in an amount of 1.8 × 10 15 . After the first mask 8 is removed, an oxidation process is performed so that silicon and arsenic have a recrystallized structure in an amorphous state. Then, the tungsten silicide film 5 is secondarily annealed to form a tetragonal structure, resulting in a complete crystal structure. At this time, the oxidation process is performed by injecting He as an atmosphere gas in the LPCVD equipment at 900 ℃. In this way, the oxygen reacts with the polysilicon film 4 to form SiO 2 or the silicon component of the tungsten silicide film 5 reacts with oxygen, so that the crystal ratio of the tungsten silicide film, i.e., the composition ratio, is not unstable.

도 1(c)에 도시된 바와 같이 전체 구조 상부에 제 2 감광막을 도포한 후 마스크 및 식각 공정을 실시하여 NMOS 트랜지스터가 형성된 부분에 제 2 마스크(10)을 형성한다. 전면에 고농도의 P형 불순물을 주입하여 PMOS 영역에 소오스/드레인 영역(11)을 형성한다. 이때 고농도의 P형 불순물은 약 2.5×1015의 양으로 40keV의 에너지로 주입한다.As shown in FIG. 1C, a second photoresist film is coated on the entire structure, and a mask and an etching process are performed to form a second mask 10 in a portion where an NMOS transistor is formed. A source / drain region 11 is formed in the PMOS region by implanting a high concentration of P-type impurities into the entire surface. At this time, a high concentration of P-type impurities is injected at an energy of 40 keV in an amount of about 2.5 × 10 15 .

도 1(d)는 제 2 마스크(10)를 제거하여 트랜지스터를 형성한 단면도이다.FIG. 1D is a cross-sectional view of a transistor formed by removing the second mask 10.

상술한 바와 같이 본 발명에 의하면 폴리사이드 구조의 게이트 전극을 형성한 후 저농도의 불순물 주입을 전면에 실시하고 산화 공정을 He 가스를 이용하여 실시함으로써 텅스텐 실리사이드의 침전 및 석출에 의한 결함으로 인하여 발생되는 게이트 전극의 전류 손실 및 후속 공정 후의 패터닝시 편차에 의한 구조적 결함을 해결할 수 있다.As described above, according to the present invention, a gate electrode having a polyside structure is formed, and then a low concentration of impurity is injected to the entire surface, and an oxidation process is performed using He gas, thereby resulting from defects due to precipitation and precipitation of tungsten silicide. Structural defects due to current loss of the gate electrode and deviation in patterning after subsequent processing can be solved.

Claims (3)

실리콘 기판 상부에 폴리실리콘 및 텅스텐 실리사이드가 적층된 폴리사이드 구조의 게이트 전극을 형성하는 단계와,Forming a gate electrode having a polyside structure in which polysilicon and tungsten silicide are stacked on a silicon substrate; 상기 실리콘 기판의 전면에 저농도의 불순물을 주입하는 단계와,Injecting a low concentration of impurities into the entire surface of the silicon substrate; 상기 게이트 전극 측면에 스페이서를 형성한 후 실리콘 기판의 선택된 영역에 고농도의 N형 불순물을 주입하는 단계와,Forming a spacer on the side of the gate electrode and implanting a high concentration of N-type impurities into a selected region of the silicon substrate; 헬륨 가스 분위기에서 산화 공정을 실시하는 단계와,Performing an oxidation process in a helium gas atmosphere, 상기 실리콘 기판중 고농도의 N형 불순물이 주입되지 않은 영역에 고농도의 P형 불순물을 주입하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 제조 방법.And injecting a high concentration of P-type impurities into a region where the high concentration of N-type impurities is not implanted in the silicon substrate. 제 1 항에 있어서, 상기 산화 공정은 900℃의 LPCVD 장비에서 실시하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the oxidation process is performed at 900 ° C. LPCVD equipment. 제 1 항에 있어서, 상기 고농도의 P형 불순물은 2.5×1015정도의 양으로 40keV의 에너지에서 주입하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the high concentration of P-type impurities is injected at an energy of 40 keV in an amount of about 2.5 × 10 15 .
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