KR930011176B1 - Manufacturing method of semiconductor device with ldd structure - Google Patents

Manufacturing method of semiconductor device with ldd structure Download PDF

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KR930011176B1
KR930011176B1 KR1019910000564A KR910000564A KR930011176B1 KR 930011176 B1 KR930011176 B1 KR 930011176B1 KR 1019910000564 A KR1019910000564 A KR 1019910000564A KR 910000564 A KR910000564 A KR 910000564A KR 930011176 B1 KR930011176 B1 KR 930011176B1
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oxide film
ldd structure
nitride film
gate
film
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KR1019910000564A
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Korean (ko)
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KR920015636A (en
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서재범
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The semiconductor device having a LDD structure is prepared by coating an oxide film on a substrate, forming a larger nitride film area than gate area thereon, undercutting the substrate by istropically etching with a nitride film mask, implanting the high concn. impurity of LDD structure with a nitride film mask, removing the remaining nitride and oxide films, forming a gate oxide film, a polysilicon film and a CVD oxide film at gate forming area in order, implanting the low concn. impurity of LDD structure at the displayed substrate.

Description

LDD구조의 반도체장치 제조방법LDD structure semiconductor device manufacturing method

제1a-d도는 종래의 제조공정도.1a-d are conventional manufacturing process diagrams.

제2a-f도는 본발명의 1실시예에 따른 제조공정도이다.2a-f is a manufacturing process chart according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 반도체 기판 12 : 산화막11 semiconductor substrate 12 oxide film

13 : 질화막 14 : 게이트산화막13 nitride film 14 gate oxide film

15 : 폴리실리콘 16 : CVD산화막15 polysilicon 16 CVD oxide film

본 발명은 반도체 장치에 관한 것으로, 특히 긴 채널을 갖는 LDD(Lighty Doped Drain)구조의 반도체 장치 제조방법에 관한 것이다. 종래에는, 제1a-d도에 도시한 바와 같이 우선 반도체 기판(1)상에 게이트산화막(2), 폴리실리콘(3)을 차례로 증착한 후(제1a도), 게이트영역이외의 폴리실리콘(3) 게이트산화막(2)을 제거하고(제1b도), 노출된 부분에 LDD구조의 n-형 불순물 예를 들어 인을 주입한 다음(제1c도), CVD(Chemical Vapour Deposition)산화막으로 된 측벽을 형성하고 LDD구조의 n+형 불순물, 예를 들어 비소를 재차 주입한 후 소정의 열처리를 하여(제1d도), LDD구조의 반도체 장치를 제조하였다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a light doped drain (LDD) structure having a long channel. Conventionally, as shown in Figs. 1A-D, first, the gate oxide film 2 and the polysilicon 3 are sequentially deposited on the semiconductor substrate 1 (Fig. 1A), and then polysilicon other than the gate region (Fig. 3) The gate oxide film 2 is removed (FIG. 1B), n - type impurities of LDD structure, for example, phosphorus is injected into the exposed portion (FIG. 1C), and then a CVD (Chemical Vapor Deposition) oxide film is formed. A sidewall was formed, n + -type impurities of the LDD structure, for example, arsenic were re-injected, and then subjected to a predetermined heat treatment (FIG. 1d) to manufacture a semiconductor device of the LDD structure.

그러나, 이러한 종래기술은 채널이 평평하므로 채널길이가 짧아 쇼트채널효과등의 문제를 야기시킨다. 또한 인(n-형 불순물)을 비소(n+형 불순물)보다 먼저 이온 주입하는데 인의 확산도가 비소보다 크므로 열처리후 인이 비소를 둘러싼 구조로 형성되는 문제점이 있었다.However, this conventional technique causes a problem such as short channel effect because the channel length is short because the channel is flat. In addition, phosphorus (n - type impurity) is ion-injected before arsenic (n + type impurity), but since phosphorus diffusion is greater than that of arsenic, there is a problem that phosphorus is formed into a structure surrounding arsenic after heat treatment.

본발명은 이와 같은 문제점을 해결하기 위한 것으로, 등방성 에치를 이용하여 소오스와 드레인 사이의 간격을 넓히고 n+형 불순물을 n-형 불순물보다 먼저 이온주입하여 완벽한 LDD구조의 반도체 장치 제조방법을 제공하는 것이다.The present invention has been made to solve the above problems, by using an isotropic etch to widen the gap between the source and drain, and ion implantation of n + type impurities before n - type impurities to provide a method of manufacturing a semiconductor device of a perfect LDD structure will be.

이와 같은 목적을 달성하기 위한 본발명의 특징은 반도체 기판상에 산화막을 도포한 후 그 위에 게이트 영역보다 넓은 범위로 제한된 질화막을 형성하는 공정과, 질화막을 마스크로 사용하여 반도체 기판을 등방성 에치로 언더컷하는 공정과, 질화막을 마스크로 사용하여 LDD구조의 고농도 불순물을 이온주입하는 공정과, 남아있는 질화막, 산화막을 제거한 후 게이트 형성영역으로 제한된 게이트산화막, 폴리실리콘, CVD산화막을 차례로 형성하는 공정과, 노출된 반도체 기판에 LDD구조의 저농도 불순물을 이온 주입하는 공정으로 이루어진 LDD구조의 반도체 장치 제조방법에 있다.In order to achieve the above object, the present invention provides a process for forming an nitride film limited to a wider range than a gate region after applying an oxide film on the semiconductor substrate, and using the nitride film as a mask to undercut the semiconductor substrate with an isotropic etch. A process of ion implanting a high concentration impurity of an LDD structure using a nitride film as a mask, a process of forming a gate oxide film, a polysilicon, and a CVD oxide film limited to a gate formation region after removing the remaining nitride film and the oxide film; A method of manufacturing an LDD structure semiconductor device comprising a step of ion implanting low concentration impurities of an LDD structure into an exposed semiconductor substrate.

이하, 본발명을 첨부도면에 의하여 상세히 설명한다.Hereinafter, the present invention will be described in detail by the accompanying drawings.

제2a-f도는 본발명의 1실시예에 따른 제조공정도로서, 우선 제2a도에 도시한 바와 같이 반도체 기판(11)상에 산화막(12), 질화막(13)을 차례로 도포하고 소정의 부분, 즉 게이트영역을 포함하고 게이트영역보다 어느 정도 넓은 부분으로 남기고 질화막(13)을 제거한 후, 제2b도와 같이 질화막(13)을 마스크로 사용하여 습식 식각으로 등방성 에치하여 반도체 기판(11)이 질화막(13)의 양단으로 침투해서 식각되는 언더컷(Undercut)현상이 발생되도록 한다.2A to 2F are manufacturing process diagrams according to one embodiment of the present invention. First, as shown in FIG. 2A, an oxide film 12 and a nitride film 13 are sequentially applied onto a semiconductor substrate 11, and a predetermined portion, namely, After removing the nitride film 13 including the gate area and leaving the part somewhat wider than the gate area, the semiconductor substrate 11 is isotropically etched by wet etching using the nitride film 13 as a mask as shown in FIG. Penetrate into both ends to cause undercut etch.

그후, 제2c도에 도시한 바와 같이 질화막(13)을 마스크로 사용하여 n+형 불순물, 예를 들어 비소를 이온 주입하고 열처리하여 n+형 접합을 형성한 후, 제2d도와 같이 남아있는 질화막(13), 산화막(12)를 제거하고 전면에 게이트산화막(14), 폴리실리콘(15), CVD산화막(16)을 차례로 도포한다. 그 다음, 제2e도에 도시한 바와 같이 게이트영역이외의 CVD산화막(16), 폴리실리콘(15), 게이트산화막(14)을 제거하고 노출된 반도체 기판(11)에 n-형 불순물, 예를 들어 인을 이온 주입하면 제2f도와 같은 본발명의 LDD구조의 트랜지스터를 얻을 수 있게 된다.Thereafter, using the nitride film 13 as a mask as shown in FIG. 2C, an n + type impurity such as arsenic is ion-implanted and heat treated to form an n + type junction, and the remaining nitride film as shown in FIG. 2D (13), the oxide film 12 is removed, and the gate oxide film 14, the polysilicon 15, and the CVD oxide film 16 are sequentially applied to the entire surface. Next, as shown in FIG. 2E, the CVD oxide film 16, the polysilicon 15, and the gate oxide film 14 other than the gate region are removed, and n − type impurities are exposed to the exposed semiconductor substrate 11, for example. For example, by implanting phosphorus, a transistor of the LDD structure of the present invention as shown in Fig. 2f can be obtained.

이상 설명한 바와 같이, 본발명에 따르면 등방성 에치에 의하여 생긴 단차로 인하여 소오스와 드레인 사이의 간격을 넓혀 쇼트채널효과를 방지시킬 수 있으며 질화막을 마스크로 사용하여 n+형 불순물을 먼저 주입함으로써 완벽한 LDD구조를 얻을 수 있는 효과가 있다.As described above, the present invention due to the looking step by the isotropic etch can be widened prevent short channel effect the spacing between the source and the drain, and complete LDD structure by a nitride implantation of n + type impurity, first, using as a mask. There is an effect that can be obtained.

Claims (1)

반도체 기판상에 산화막을 도포한 후 그 위에 게이트 영역보다 넓은 범위로 제한된 질화막을 형성하는 공정과, 상기 질화막을 마스크로 사용하여 상기 반도체 기판을 등방성 에치로 언더컷하는 공정과, 상기 질화막을 마스크로 사용하여 LDD구조의 고농도 불순물을 이온 주입하는 공정과, 남아있는 상기 질화막, 상기 산화막을 제거한 후 상기 게이트 형성 영역으로 제한된 게이트산화막, 폴리실리콘, CVD산화막을 차례로 형성하는 공정과, 노출된 상기 반도체 기판에 LDD구조의 저농도 불순물을 이온 주입하는 공정으로 이루어진 LDD구조의 반도체 장치 제조방법.Forming a nitride film limited to a wider range than the gate region after applying an oxide film on the semiconductor substrate, undercutting the semiconductor substrate with an isotropic etch using the nitride film as a mask, and using the nitride film as a mask Ion-implanting a high concentration impurity of an LDD structure, sequentially removing the remaining nitride film and the oxide film, and then forming a gate oxide film, a polysilicon, and a CVD oxide film limited to the gate formation region, and exposing the exposed semiconductor substrate. A method for manufacturing a semiconductor device of an LDD structure, comprising a step of ion implanting low concentration impurities of an LDD structure.
KR1019910000564A 1991-01-15 1991-01-15 Manufacturing method of semiconductor device with ldd structure KR930011176B1 (en)

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KR930011176B1 true KR930011176B1 (en) 1993-11-24

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