KR20030042098A - Method of forming contact hole of semiconductor device - Google Patents
Method of forming contact hole of semiconductor device Download PDFInfo
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- KR20030042098A KR20030042098A KR1020010072612A KR20010072612A KR20030042098A KR 20030042098 A KR20030042098 A KR 20030042098A KR 1020010072612 A KR1020010072612 A KR 1020010072612A KR 20010072612 A KR20010072612 A KR 20010072612A KR 20030042098 A KR20030042098 A KR 20030042098A
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- layer
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 61
- 239000011229 interlayer Substances 0.000 claims abstract description 44
- 125000006850 spacer group Chemical group 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 32
- 238000005498 polishing Methods 0.000 claims description 2
- 238000003860 storage Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 10
- 229920000642 polymer Polymers 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치의 형성 방법에 관한 것으로, 보다 상세하게는 반도체 장치의 콘택 홀 형성 방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a contact hole in a semiconductor device.
반도체 장치의 소자 고집적화 경향에 따라 디램 등의 메모리 장치 디자인 룰이 줄어들게 된다. 그리고, 좁은 공간에 많은 소자와 배선을 형성하게 되면서 공정 불량의 가능성은 점차 높아진다. 가령, 게이트 전극이나 비트라인 사이에 콘택을 형성할 때 노광 정렬 상의 부정확성으로 콘택 플러그가 게이트 전극 혹은 비트라인과 전기적 단락을 일으킬 가능성이 높다.Memory device design rules, such as DRAM, are reduced according to the trend toward higher integration of semiconductor devices. In addition, as many devices and wirings are formed in a narrow space, the possibility of process failure increases gradually. For example, when forming a contact between a gate electrode or a bitline, the contact plug is likely to cause an electrical short with the gate electrode or bitline due to inaccuracy in the exposure alignment.
이런 문제를 막기 위해 게이트 전극이나 비트라인 사이에 형성되는 콘택을 자기정렬형으로 형성하는 경우가 일반화된다. 이하 도1과 같이 디램의 워드 라인 사이에 비트라인 콘택을 형성하는 경우를 참조하면서 통상의 자기 정렬형 콘택 형성 방법을 살펴본다. 통상의 자기 정렬형 콘택을 형성할 때는 먼저, 층간 절연막(21)과 식각 선택성을 가지는 재질로 이루어진 캡핑층(15)과 스페이서(17)가 도전층(13,131)으로 이루어진 게이트 전극이나 비트라인 상부 및 측벽에 설치된 상태로 도전 패턴을 형성한다. 이들 도전 패턴 위로 층간 절연막(21)을 형성한다. 그리고, 층간 절연막(21)에 도전층 패턴 사이를 관통하는 콘택 홀(23)을 형성한다. 따라서, 정렬상의 실수 혹은 노광 공정의 한계로 콘택 홀(23)이 형성되는 영역이 도전 패턴과 일부 겹치는 경우에도 캡핑층(15) 및 스페이서(17)가 식각 저지막으로 작용함으로써 도전 패턴과 형성될 콘택 플러그가 전기적으로 접속되는 단락을 방지한다.In order to prevent this problem, it is common to form a self-aligned contact formed between the gate electrode and the bit line. Hereinafter, a conventional self-aligned contact forming method will be described with reference to a case in which bit line contacts are formed between word lines of a DRAM as shown in FIG. 1. When forming a conventional self-aligned contact, first, the capping layer 15 and the spacer 17 made of a material having an etch selectivity with the interlayer insulating film 21 and the upper portion of the gate electrode or bit line made of the conductive layers 13 and 131, and A conductive pattern is formed in the state provided in the side wall. An interlayer insulating film 21 is formed over these conductive patterns. A contact hole 23 penetrating between the conductive layer patterns is formed in the interlayer insulating film 21. Therefore, even when the contact hole 23 is partially overlapped with the conductive pattern due to misalignment or limitation of the exposure process, the capping layer 15 and the spacer 17 act as an etch stop layer to form the conductive pattern. Prevent short circuits in which contact plugs are electrically connected.
그러나, 반도체 장치의 디자인 룰이 가령, 0.13um 이하로 더 줄어들면 스페이서로 인해 콘택 플러그가 하부 도전 영역과 만나는 면적이 줄어들어 콘택 저항을 높이게 된다. 이런 문제를 막기 위해, 고집적화가 계속되면 도2와 같이 스페이서(17)의 두께도 줄어들게 된다. 얇은 스페이서(17)로 콘택 홀 형성시 게이트 전극이나 비트라인을 보호하기 위해서는 콘택 홀 형성을 위해 식각되는 층간 절연막(21)과 스페이서(17)의 식각 선택비가 가령, 30:1 정도로 매우 높게 유지되도록 스페이서(17) 재질과 식각 조건을 선택해야 한다. 또한, 스페이서(17)가 모두 손상되지 않는 경우에도 기생 용량(parasitic capacitance)의 증가를 막기 위해 스페이서(17)는 일정 두께 이상으로 유지되는 것이 요청된다.However, if the design rule of the semiconductor device is further reduced to, for example, 0.13 um or less, the area where the contact plug meets the lower conductive region due to the spacers is reduced, thereby increasing the contact resistance. In order to prevent such a problem, if the high integration continues, the thickness of the spacer 17 is also reduced as shown in FIG. In order to protect the gate electrode or the bit line when forming the contact hole with the thin spacer 17, the etching selectivity of the interlayer insulating layer 21 and the spacer 17 etched to form the contact hole is maintained to be very high, for example, about 30: 1. The material and etching conditions of the spacer 17 must be selected. In addition, even when all of the spacers 17 are not damaged, the spacers 17 are required to be kept above a predetermined thickness in order to prevent an increase in parasitic capacitance.
그러나, 통상 공정을 통해 층간 절연막(21)을 실리콘 산화막으로, 스페이서(17)를 실리콘 질화막으로 형성하고, 통상의 식각 조건으로 콘택 홀을 형성할 경우, 이런 높은 식각 선택비를 가지기 어렵다. 가령, 층간 절연막(21)과 10:1 이하의 저선택비를 가지도록 스페이서(17) 및 식각 조건을 선택할 경우, 도2와 같이 층간 절연막(21)에 콘택 홀을 형성하는 과정에서 스페이서(17)가 손상되어 비트라인 콘택 플러그(33)와 게이트 전극의 도전층(13,131) 사이에 단락이 발생할 수 있다.However, when the interlayer insulating film 21 is formed of a silicon oxide film and the spacer 17 is formed of a silicon nitride film through a normal process, and a contact hole is formed under normal etching conditions, it is difficult to have such a high etching selectivity. For example, when the spacer 17 and the etching conditions are selected to have a low selectivity of 10: 1 or less with the interlayer insulating film 21, the spacers 17 may be formed in the process of forming contact holes in the interlayer insulating film 21 as shown in FIG. 2. ) May be damaged to cause a short circuit between the bit line contact plug 33 and the conductive layers 13 and 131 of the gate electrode.
또한, 통상 스페이서로 사용되는 실리콘 질화막에 대해 고도의 선택성을 가지는 조건으로 콘택 홀 형성을 위한 층간 절연막 식각을 실시할 경우, 실리콘 기판에 결정 손상 깊이가 증가되고 콘택 홀 내에 탄소-불소 계열의 폴리머 부착이 증가한다. 이런 현상들은 후속적으로 이루어질 콘택의 저항을 높이는 원인이 될 수 있다.In addition, when the interlayer insulating film etching for forming the contact hole is performed under the condition of having a high selectivity to the silicon nitride film, which is usually used as a spacer, the crystal damage depth is increased in the silicon substrate and the carbon-fluorine-based polymer is deposited in the contact hole. This increases. These phenomena can cause a higher resistance of subsequent contacts.
한편, 종래에는 주어진 장비에서 콘택 홀의 폭을 줄이는 데 한계가 있다. 그러므로, 도체 패턴 사이의 간격이 콘택 홀의 폭보다 작을 경우, 콘택 홀 형성을 위한 식각시 도체 패턴의 상면이 드러난다. 따라서, 도체 패턴의 최상층에는 도체층 패턴을 보호하기 위해 층간 절연막과의 선택비가 큰 절연성 캡핑막이 필요하다. 그런데, 캡핑막으로 사용되는 실리콘 질화막은 패터닝 공정에서 선폭 조절을 어렵게하는 문제점이 있다.On the other hand, conventionally there is a limit to reducing the width of the contact hole in a given equipment. Therefore, when the distance between the conductor patterns is smaller than the width of the contact holes, the top surface of the conductor patterns is exposed when etching for forming the contact holes. Therefore, in order to protect the conductor layer pattern, the uppermost layer of the conductor pattern requires an insulating capping film having a large selectivity with respect to the interlayer insulating film. However, the silicon nitride film used as the capping film has a problem of making line width control difficult in the patterning process.
본 발명은 상술한 문제점을 해결하기 위한 것으로, 고집적 반도체 장치 형성에 있어서 저선택비 식각 공정으로도 얇은 스페이서가 설치된 도전 패턴에서 도전층을 드러내지 않고 콘택 홀을 형성할 수 있는 방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for forming a contact hole without exposing a conductive layer in a conductive pattern provided with a thin spacer even in a low selectivity etching process in forming a highly integrated semiconductor device. It is done.
본 발명은 또한, 노광 공정에 의한 최소 형성 폭보다 좁은 폭을 가진 콘택 홀을 형성할 수 있는 방법을 제공하는 것을 목적으로 한다.The present invention also aims to provide a method capable of forming a contact hole having a width narrower than the minimum formation width by an exposure process.
도1은 종래의 비트라인 콘택 홀 형성 태양을 나타내는 공정 단면도,1 is a process cross-sectional view showing a conventional bit line contact hole formation aspect;
도2는 종래의 비트라인 콘택 홀 형성의 문제점을 설명하기 위한 공정 단면도,2 is a cross-sectional view illustrating a problem of conventional bit line contact hole formation;
도3 내지 도6은 본 발명의 콘택 홀 형성 방법의 각 단계를 나타내는 공정 단면도들이다.3 to 6 are process cross-sectional views showing respective steps of the method for forming a contact hole of the present invention.
상기 목적을 달성하기 위한 본 발명의 반도체 장치 콘택 홀 형성 방법은, 기판에 도전 패턴을 형성하는 단계, 도전 패턴의 측벽에 스페이서를 형성하는 단계, 스페이서가 형성된 기판에 스페이서와 식각 선택비를 가지는 층간 절연막을 형성하는 단계, 층간 절연막 위에 층간 절연막과 식각 선택비를 가지는 보조막을 형성하는 단계, 패터닝을 통해 콘택이 형성될 영역을 포함하면서 콘택이 형성될 영역의 일 단과 일치하는 경계부를 가진 제1 윈도우가 있는 보조막 패턴을 형성하는 단계, 제1 윈도우 위에 콘택이 형성될 영역을 포함하면서 콘택이 형성될 영역의 상기 일 단과 반대편에 위치하는 타 단과 일치하는 경계부를 가진 제2 윈도우가 있는 포토레지스트 패턴을 형성하는 단계, 포토레지스트 패턴과 보조막 패턴을 식각 마스크로 층간 절연막을 식각하여 상기 기판을 드러내는 콘택 홀을 형성하는 단계를 구비하여 이루어진다.The semiconductor device contact hole forming method of the present invention for achieving the above object comprises the steps of: forming a conductive pattern on the substrate, forming a spacer on the sidewall of the conductive pattern, interlayer having a spacer and an etch selectivity on the substrate on which the spacer is formed Forming an insulating film, forming an auxiliary film having an etch selectivity with an interlayer insulating film on the interlayer insulating film, and a first window having a boundary portion corresponding to one end of the region where the contact is to be formed, including a region through which patterning is to be formed; Forming an auxiliary layer pattern having a second photoresist pattern, the photoresist pattern having a second window including a region where a contact is to be formed on the first window and having a boundary portion that is opposite to the other end of the region where the contact is to be formed; Forming an interlayer insulating film using the photoresist pattern and the auxiliary layer pattern as an etching mask; And it is achieved by having the step of forming a contact hole to expose the substrate.
본 발명에서 보조막 패턴이 형성된 뒤, 추가 층간 절연막을 형성하는 단계가 더 구비되고, 포토레지스트 패턴은 추가 층간 절연막 위에 형성되어 콘택 홀을 형성하는 단계에서 식각은 층간 절연막 및 추가 층간 절연막 모두에 대해 이루어질 수 있다.In the present invention, after the auxiliary film pattern is formed, the method may further include forming an additional interlayer insulating film, and the photoresist pattern may be formed on the additional interlayer insulating film to etch the etching layer in both the interlayer insulating film and the additional interlayer insulating film. Can be done.
통상, 층간 절연막 적층 뒤에는 기판 평탄화를 위한 CMP(Chemical Mechanical Polishing)나 리프로우(reflow)가 이루어진다.In general, CMP (Chemical Mechanical Polishing) or reflow is performed after the interlayer insulating film is stacked.
본 발명에서 도전 패턴은 디램의 게이트 전극 혹은 비트라인이 될 수 있고, 각각의 경우, 콘택 홀은 비트라인 콘택 홀 혹은 스토리지 노드 콘택 홀이 된다.In the present invention, the conductive pattern may be a gate electrode or a bit line of the DRAM, and in each case, the contact hole may be a bit line contact hole or a storage node contact hole.
본 발명에서 도전 패턴은 도전층만으로 이루어지거나, 도전층 위에 절연성 캡핑막을 더 가질 수 있다. 캡핑막은 층간 절연막과 식각 선택비를 가지지 않는 것도 가능하다.In the present invention, the conductive pattern may be made of only a conductive layer, or may further have an insulating capping film on the conductive layer. The capping film may not have an etching selectivity with the interlayer insulating film.
이하 도면을 참조하면서 실시예를 통해 본 발명을 좀 더 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
도3과 관련하여 그 형성 공정을 살펴보면, 먼저, 웰 형성 및 소자 분리가 이루어진 기판(10)에 게이트 절연막(11), 폴리실리콘막, 텅스텐 실리사이드막, HTO(Hihg Temperature Oxide)막이 차례로 형성된다. 통상의 포토리소그래피와 식각을 이용하는 패터닝 작업을 통해 HTO층(151), 텅스텐 실리사이드층(131), 폴리실리콘층(13)을 가진 게이트 전극이 형성된다. 실리콘 질화막을 기판 전면에 CVD(Chemical Vapor Deposition)로 적층하고 전면 이방성 식각을 통해 게이트 전극 측벽에 스페이서(17)를 형성한다. 이어서, 기판 전면에 콘포말하게 얇은 실리콘 산화막(19)을 형성하고, 층간 절연막(21)으로서 BPSG(Boro-Phospho Silicate Glass)막을 기판 전면에 가령 2000 옹스트롬 정도 두께로 형성한다. 기판 평탄화를 위해 층간 절연막(21)을 리플로우를 실시하거나, 보다 바람직하게는 CMP를 실시한다. 이때, 스페이서(17) 형성을 전후하여 기판(10)에 대한 저농도 및 고농도 이온주입 공정이 이루어진 뒤이므로 도시되지 않으나 기판(10)에는 이미 LDD(Lightly Doped Drain)형 소오스/드레인 영역이 형성된 상태이다.Referring to FIG. 3, first, a gate insulating film 11, a polysilicon film, a tungsten silicide film, and a HTO (Hihg Temperature Oxide) film are sequentially formed on the substrate 10 on which well formation and device isolation are performed. Patterning operations using conventional photolithography and etching form a gate electrode having an HTO layer 151, a tungsten silicide layer 131, and a polysilicon layer 13. The silicon nitride film is deposited on the entire surface of the substrate by CVD (chemical vapor deposition), and spacers 17 are formed on the sidewalls of the gate electrodes through front side anisotropic etching. Subsequently, a conformally thin silicon oxide film 19 is formed on the entire surface of the substrate, and a BPSG (Boro-Phospho Silicate Glass) film is formed on the entire surface of the substrate, for example, about 2000 angstroms thick as the interlayer insulating film 21. In order to planarize the substrate, the interlayer insulating film 21 is reflowed, or more preferably, CMP is performed. At this time, the low concentration and high concentration ion implantation processes are performed on the substrate 10 before and after the formation of the spacer 17. However, although not shown, the substrate 10 is already formed with a lightly doped drain (LDD) type source / drain region. .
그리고, 통상의 비트라인 콘택 홀 형성 공정과 달리, 보조막으로서 실리콘 질화막을 두께 500 옹스트롬 정도로 적층하고 하드 마스크막으로서 HTO막을 두께 100 옹스트롬 정도 적층한다. 하드 마스크막 위에 제1 포토레지스트 패턴(127)을 형성한다. 그리고, 제1 포토레지스트 패턴을 식각 마스크로 보조막에 대한 식각을 실시하여 제1 윈도우를 가지는 보조막 패턴(123) 및 하드 마스크(125)를 형성한다. 이때, 제1 윈도우의 영역(129)은, 그 경계부의 일부를 일 단(130)이라면, 이 일 단(130)이 이후 비트라인 콘택이 형성될 영역(128)의 일 단과 일치하도록 형성하며, 비트라인 콘택이 형성될 영역(128)을 포함하도록 형성한다. 즉, 비트라인 콘택을 형성할 영역(128)이 제1 윈도우 영역(129)에 내접하도록 형성한다. 또한, 이 일 단(130)에서 하방으로 연장된 가상선이 게이트 전극 외측, 즉, 게이트 전극을 기준으로 할 때 스페이서(17) 바깥쪽에 떨어지거나 스페이서(17) 위에 떨어지도록 한다. 보조막(123) 식각 과정에서 하드 마스크막(125)도 보조막(123)과 동일하게 패터닝된다. 식각은 가령, 실리콘 산화막에 대해 실리콘 질화막이 두배의 선택비를 가지는 조건에서 실리콘 질화막 700 옹스트롬 두께를 대상으로 하는 이방성 식각을 실시하면 된다. 식각 가스로는 탄소에 대한 불소의 비중이 높도록 CHF3, CF4 등의 분압을 높인 것을 사용하는 것이 바람직하다.And unlike the usual bit line contact hole forming process, a silicon nitride film is laminated | stacked about 500 angstroms thick as an auxiliary film, and an HTO film | membrane about 100 angstroms thick is laminated | stacked as a hard mask film. The first photoresist pattern 127 is formed on the hard mask layer. The auxiliary layer is etched using the first photoresist pattern as an etching mask to form the auxiliary layer pattern 123 and the hard mask 125 having the first window. In this case, the region 129 of the first window is formed such that one end 130 of the first window 130 corresponds to one end of the region 128 where a bit line contact is to be formed. The bit line contact is formed to include an area 128 to be formed. That is, the region 128 for forming the bit line contact is formed to be inscribed with the first window region 129. In addition, the imaginary line extending downward from the one end 130 may fall outside the spacer 17 or fall on the spacer 17 when the gate electrode is outside, that is, based on the gate electrode. During the etching of the auxiliary layer 123, the hard mask layer 125 is also patterned in the same manner as the auxiliary layer 123. For example, the etching may be performed by anisotropic etching for the silicon nitride film 700 angstrom thickness under the condition that the silicon nitride film has twice the selectivity with respect to the silicon oxide film. As the etching gas, it is preferable to use one having a high partial pressure such as CHF 3 or CF 4 so that the specific gravity of fluorine to carbon is high.
도3에서 도4의 상태를 형성하기 위해, 제1 포토레지스트 패턴(127)은 애싱을통해 제거하고 기판 세정을 한다. 제1 윈도우를 가지는 보조막 패턴(123) 및 하드 마스크(125) 위에 바로 제2 포토레지스트 패턴을 형성할 수 있으나, 바람직하게는 추가 층간 절연막(131)을 1000 옹스트롬 정도 더 적층한 뒤 추가 층간 절연막(131) 위에 제2 포토레지스트 패턴(133)을 형성한다. 포토마스크 노광과 현상을 통해 형성되는 제 2 포토레지스트 패턴(133)은 제2 윈도우 영역(135)을 가지도록 한다. 이때, 제2 윈도우 영역(135)은 콘택이 형성될 영역(128)을 포함한다. 동시에, 콘택이 형성될 영역(128)과 제2 윈도우 영역(135)이 내접하는 경계부의 일부를 타 단(136)이라 할 때, 콘택이 형성될 영역(128)의 폭은 일 단(130)에서 타 단(136)의 거리와 같게 한다. 이 타 단(136)에서 하방으로 연장된 가상선도 다른 게이트 전극의 외측에 떨어지도록 한다.3 to 4, the first photoresist pattern 127 is removed through ashing and substrate cleaned. A second photoresist pattern may be formed directly on the auxiliary layer pattern 123 and the hard mask 125 having the first window, but preferably, the additional interlayer insulating layer 131 is further stacked by about 1000 angstroms, and then the additional interlayer insulating layer is formed. The second photoresist pattern 133 is formed on the 131. The second photoresist pattern 133 formed through photomask exposure and development has a second window region 135. In this case, the second window area 135 includes an area 128 in which a contact is to be formed. At the same time, when the area 128 where the contact is to be formed and the part of the boundary where the second window area 135 is inscribed is called the other end 136, the width of the area 128 where the contact is to be formed is one end 130. It is equal to the distance of the other end 136 in. The virtual line extending downward from the other end 136 is also dropped on the outside of the other gate electrode.
도4 및 도5를 참조하여 설명하면, 제2 포토레지스트 패턴(133)을 식각 마스크로 추가 층간 절연막(131)과 층간 절연막(21)을 식각하여 비트라인 콘택 홀(137)을 형성한다. 추가 층간 절연막(131)과 층간 절연막(21)은 동일한 조건으로 연속적으로 식각하거나, 2단계로 식각할 수 있다. 2단계 식각에서는 보조막(123)이 노출되기 전인 초기 단계에 실리콘 질화막과 실리콘 산화막의 선택비가 낮은 식각 조건을 사용하고, 보조막이 노출된 후기 단계에서는 두 막의 선택비가 10:1 정도 되는 식각 조건을 사용할 수 있다. 두 막에 대한 선택비를 높이기 위해 식각 가스에서 탄소에 대한 불소의 비중이 상대적으로 낮은 CH2F2, C4F8 등 가스의 분압을 높여 사용할 수 있다. 식각 단계를 통해 보조막 패턴(123)과 제2 포토레지스트 패턴(133)이 식각 마스크의 역할을 하므로 제1 윈도우의 영역(129)과 제2 윈도우의영역(135)이 겹친 부분에만 하부 기판(10)이 노출되는 비트라인 콘택 홀(137)이 이루어진다. 이어서 애싱을 통해 제2 포토레지스트 패턴(133)을 제거하고, 세정을 실시한다.Referring to FIGS. 4 and 5, the bit line contact hole 137 is formed by etching the additional interlayer insulating layer 131 and the interlayer insulating layer 21 using the second photoresist pattern 133 as an etching mask. The additional interlayer insulating layer 131 and the interlayer insulating layer 21 may be continuously etched under the same conditions, or may be etched in two steps. In the second stage etching, an etching condition having a low selectivity between the silicon nitride layer and the silicon oxide layer is used in the initial stage before the auxiliary layer 123 is exposed.In the late stage in which the auxiliary layer is exposed, an etching condition in which the selectivity of the two layers is about 10: 1 is used. Can be used. In order to increase the selectivity for the two membranes, the partial pressure of gases such as CH2F2 and C4F8, which have relatively low fluorine to carbon ratio in the etching gas, can be used. Since the auxiliary layer pattern 123 and the second photoresist pattern 133 serve as an etching mask through the etching step, the lower substrate may be formed only at a portion where the region 129 of the first window and the region 135 of the second window overlap. The bit line contact hole 137 is exposed. Subsequently, the second photoresist pattern 133 is removed through ashing, and cleaning is performed.
도5 및 도6을 참조하면, 비트라인 콘택 홀(137)이 형성된 기판에 스탭 커버리지(step coverage)가 뛰어난 폴리실리콘을 충분히 적층하고 전면 이방성 식각이나 CMP 등의 리세스 단계를 통해 비트라인 콘택 플러그(139)가 형성된다. 이후, 도전막 적층과 패터닝을 통해 비트라인 콘택 플러그(139)와 접속되는 비트라인이 형성된다.5 and 6, polysilicon having excellent step coverage is sufficiently stacked on a substrate on which the bitline contact hole 137 is formed, and the bitline contact plug is formed through a recess step such as anisotropic etching or CMP. 139 is formed. Thereafter, a bit line connected to the bit line contact plug 139 is formed by stacking and patterning the conductive film.
이와 같은 실시예를 통해 볼 때, 본 발명은 고집적 반도체 장치에서 도체 패턴 사이로 콘택이 형성될 때 콘택 홀 형성시 식각 선택비가 낮고, 도체 패턴 측벽의 스페이서가 얇은 경우에도 도체 패턴과 콘택 플러그가 전기 단락되는 것을 방지할 수 있다.According to this embodiment, when the contact is formed between the conductor patterns in the high-density semiconductor device, the etching selectivity is low when forming contact holes, and the conductor pattern and the contact plug are short-circuited even when the spacers on the sidewalls of the conductor pattern are thin. Can be prevented.
또한, 정렬 조작을 통해 노광 장비의 한계보다 폭이 적은 콘택 홀을 형성할 수 있으므로 노광 장비의 개선이 없이도 폭이 좁은 콘택을 형성할 수 있다. 따라서, 본 발명을 이용하면 도체 패턴 최상층에 실리콘 질화막으로 된 캡핑막을 사용할 필요가 없으므로 게이트 패턴 등 도체 패턴의 선폭 조절이 용이해진다.In addition, since the contact hole having a width smaller than the limit of the exposure equipment can be formed through the alignment operation, a narrow contact can be formed without improvement of the exposure equipment. Therefore, by using the present invention, it is not necessary to use a capping film made of a silicon nitride film on the uppermost layer of the conductor pattern, so that the line width of the conductor pattern such as the gate pattern can be easily adjusted.
그리고, 스페이서와 층간 절연막 사이의 식각 선택비를 높이하는 콘택 홀 형성 과정에서 발생하는 기판 손상과 폴리머 생성을 줄여 형성될 콘택의 저항을 줄일 수 있다.In addition, the resistance of the contact to be formed may be reduced by reducing the substrate damage and the polymer generated during the contact hole formation process to increase the etch selectivity between the spacer and the interlayer insulating layer.
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| JPH10223897A (en) * | 1997-01-31 | 1998-08-21 | Nippon Steel Corp | Semiconductor device and its manufacture |
| JPH10256368A (en) * | 1997-03-12 | 1998-09-25 | Sony Corp | Manufacture of semiconductor device |
| KR100586538B1 (en) * | 1999-12-30 | 2006-06-07 | 주식회사 하이닉스반도체 | Method for forming contact hole of semiconductor device |
-
2001
- 2001-11-21 KR KR10-2001-0072612A patent/KR100429008B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI786559B (en) * | 2021-03-02 | 2022-12-11 | 南亞科技股份有限公司 | Semiconductor structure and forming method thereof |
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| KR100429008B1 (en) | 2004-04-29 |
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