KR20010038144A - Masking method of bit line and word line in semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for masking a bit line and a word line is to protect the word line and the bit line when forming an opening to be provided with a storage electrode of a capacitor by using an SAC(self aligned contact) etching process. CONSTITUTION: An isolation layer(310) is formed on a semiconductor substrate(300). A gate oxide layer, a word line conductive layer, the first masking layer, and the second masking layer are formed in this order on an active region of the substrate defined by the isolation layer. A word line(330') with an upper part thereof masked is formed by patterning the gate oxide layer, the word line conductive layer, the first masking layer, and the second masking layer, using a photolithography. A source region(360) and a drain region(370) are formed by implanting a low concentration conductive impurity into the substrate by using the masked word line as an ion implantation mask. A spacer(380) is formed to mask the sidewall of the masked word line. An LDD(lightly doped drain) structure is formed by implanting a high concentration conductive impurity into the substrate by using the masked word line as an ion implantation mask.

Description

Masking method of bit line and word line in semiconductor memory device

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of masking word lines and bit lines of a semiconductor memory device.

As semiconductor memory devices are highly integrated, there are various problems due to the limitation of photolithography technology when forming direct contact (DC) contacts that connect bit lines and burried contact (BC) contacts that connect storage nodes of capacitors. For example, when a contact hole in which a DC contact and a BC contact are to be formed in the interlayer insulating film is formed by using a photolithography technique, there is a problem that the contact hole does not open. In addition, the reduction of the area of the DC contact and the BC contact due to the high integration of the semiconductor memory device causes the contact resistance to increase, thereby reducing the operating speed of the semiconductor memory device. As a result, when the increase in the contact resistance due to the reduction in the cross-sectional area of the DC contact and the BC contact exceeds the limit, the semiconductor memory device may fail.

Therefore, in the manufacture of ultra-high density semiconductor memory devices, in order to increase the process margin of the photolithography process and improve the operating characteristics of the semiconductor memory device, SAC (Self Aligned Contact) etching technology is in the spotlight. For example, when a storage node of a capacitor is formed by performing a node separation process to form a capacitor of a semiconductor memory device in a COB structure, a SAC etching technique is used. However, when forming the storage node using the SAC etching technique, it is necessary to protect the word line and the bit line from the etching etchant. Therefore, in the SAC etching technique according to the related art, a method of masking word lines and bit lines with a capping layer and a nitride spacer formed of a nitride layer is mainly used. However, when the word line and the bit line are masked as described above, a problem arises when forming a predetermined opening using the SAC etching technique. Therefore, hereinafter, a method of masking word lines and bit lines according to the prior art will be described with reference to the accompanying drawings. Next, when masking the word line and the bit line according to the prior art, the problem occurring in the opening forming step using the SAC etching technique will also be described.

Referring to FIG. 1A, in the word line masking method of a semiconductor memory device according to the related art, an upper portion of a gate electrode 120 used as a word line with a gate insulating layer 110 interposed may be masked with a capping nitride layer 130 and then gated. Sidewalls of the electrode 120 are masked by the nitride film spacer 140. In order to mask the gate electrode 120 as described above, first, the gate insulating film 110, the gate electrode conductive film 120, and the capping nitride film 130 are sequentially formed on the active region on the semiconductor substrate 100. Thereafter, a photolithography process is performed to pattern the gate insulating layer 110, the gate electrode conductive layer 120, and the capping nitride layer 130. As a result, the gate electrode 120 whose upper surface is masked by the capping nitride film 130 is formed. Then, the nitride film spacer 140 masking the sidewall of the gate electrode 120 is formed in a conventional manner.

Referring to FIG. 1B, in the method of masking a bit line 150 of a semiconductor memory device according to the related art, similarly to the masking method of the word line 120, an upper portion of the bit line 150 is masked by a capping nitride layer 130 ′. The sidewalls of the bit line 150 are masked by the nitride film spacer 140 '. As described above, in order to mask the bit line 150, the bit line conductive layer 150 and the capping nitride layer 130 ′ are sequentially stacked on the interlayer insulating layer 160 formed on the entire surface of the semiconductor substrate 100. Then, the photolithography process is performed to pattern the bit line conductive layer 150 and the capping nitride layer 130 ′ to form the bit line 150 masked with the top portion shown in FIG. 1B. Subsequently, a nitride film spacer 140 'that masks the sidewall of the bit line 150 is formed by a conventional method.

However, when the word line 150 and the bit line 120 are masked as described above, a problem occurs when an opening is formed in the insulating layer by using the SAC etching technique to form the storage node of the capacitor in a subsequent process. do. Therefore, hereinafter, a case in which the word line is masked using the word line masking method according to the prior art will be described as a problem that may occur in the opening forming step using the SAC etching technique.

After forming the word line 120 masking the top and sidewalls as described above, an ion implantation process for forming a source / drain region and a process of forming a polysilicon pad on the source / drain region are performed.

Referring to FIG. 1C, which is an enlarged view of part I of FIG. 1A, a process proceeding after forming the masked word line 120, in particular, a process of forming the polysilicon pad 165, is performed. The capping nitride film 130 and the nitride film spacer 140 are consumed at the upper corner portion of the capping nitride film 130. As a result, the masking layer of the left and right upper corner portions of the word line 120 is rounded.

As described above, when the masking layer of the upper and left upper corner portions of the word line 120 is rounded, a problem occurs when an opening is formed in the insulating layer using SAC etching technology to form a storage node of the capacitor.

Referring to FIG. 1D, the opening 180 is formed in the insulating layer 170 formed on the front surface of the semiconductor substrate 100 to form the storage node 160 of the capacitor connected to the polysilicon pad 190 formed on the source region. Form. At this time, the SAC etching technique is used. In other words, since the capping nitride film 130 and the nitride film spacer 140 masking the oxide film-based insulating film 170 and the word line 120 have an etching selectivity, the opening 180 is self-aligned using the SAC etching technique. Can be formed in a manner. However, the gapping nitride layer 130 and the nitride layer spacer 140 may also be partially etched to expose the word line 120 while the opening 180 is formed. As a result, when the storage node 160 is formed in the opening 180, a short circuit 200 may be caused between the word line 120 and the storage node 160. In addition, when the gap between the polysilicon pad 210 formed on the drain region and the storage node 160 becomes weak, the position of the opening 180 is misaligned during the formation of the opening 180 using the SAC etching technique. Short circuits may also occur between the polysilicon pad 210 and the storage electrode 160 formed on the drain region.

Accordingly, a technical object of the present invention is to provide a method of masking word lines and bit lines to protect word lines and bit lines when the openings in which the storage electrodes of the capacitor are to be formed using SAC etching techniques. It is.

1A is a cross-sectional view illustrating a word line masking method according to the prior art.

1B is a cross-sectional view illustrating a bit line masking method according to the prior art.

1C and 1D illustrate problems of the word line masking method according to the related art.

2A through 2E are cross-sectional views illustrating a preferred embodiment of the word line masking method according to the present invention.

3A to 3G are cross-sectional views illustrating a preferred embodiment of the bit line masking method according to the present invention.

Hereinafter, a preferred embodiment of a method for masking a word line and a bit line according to the present invention will be described in detail. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. The following description with reference to the drawings is provided to more completely explain the present invention to those having average knowledge in the related art. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. In the drawings like reference numerals refer to like elements. In addition, if a layer is described as being on top of another layer or substrate, the layer may be present directly on top of the other layer or substrate, and a third layer may be interposed therebetween. On the other hand, the Cartesian spatial coordinate system is shown on the left side of each drawing for better understanding of the drawings. The X-axis direction, the Y-axis direction and the Z-axis direction are the word line advancing direction, the bit line advancing method, and the stacking direction of various patterns, respectively.

Referring to FIG. 2A, in the word line masking method according to the preferred embodiment of the present invention, first, an isolation layer 310 is formed on a semiconductor substrate 300. For example, the device isolation layer 310 may be formed by a LOCOS (LOCal Oxidation of Silicon) method or a trench device isolation method. Thereafter, the gate oxide layer 320, the word line conductive layer 330, the first masking layer 340, and the second mask layer 350 are sequentially formed on the active region defined by the device isolation layer 310. do. The gate oxide film 320 may be formed by a conventional method, such as a thermal oxidation method, a dry oxidation method or a wet oxidation method.

The word line conductive layer 330 may be formed using a conventional method such as a chemical vapor deposition (CVD) method, a low pressure chemical vapor deposition (LPCVD) method, or a plasma enhanced chemical vapor deposition (PECVD) method. The word line conductive layer 330 may be formed of a single layer made of a polysilicon layer or a silicide layer (eg, a tungsten silicide layer) or may be formed of a polyside structure. However, when the word line is formed of a polycide structure, the conductive film 330 for the word line may be formed of multiple layers. For example, the polysilicon film and the silicide film may be sequentially formed in order to form the double-layered conductive film 330 for the word line. The silicide film may be a silicide film of a high melting point metal. For example, the silicide layer may be a silicide layer of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), chromium (Cr), iridium (Ir), or rubidium (Ru). The word line conductive film can be formed to a thickness of between 1000 mW and 2000 mW. When the conductive film for the word line is formed of a double film in which a polysilicon film and a silicide film are sequentially stacked, the polysilicon film can be formed to a thickness of 500 kPa to 1000 kPa, and the silicide film can be formed to a thickness of 1000 kPa to 2000 kPa. have.

The first masking film 340 may be formed of a nitride film by CVD, LPCVD, PECVD, Sub-Atmospheric Chemical Vapor Deposition (SACVD), sputtering, or atomic layer deposition. When the first masking film 340 is formed of a nitride film, it can be formed of a conventional silicon nitride film having a refractive index of about 2, and more preferably a silicon-rich nitride film having a refractive index of 2.2 to 2.5. Because the silicon-rich nitride film is 1/2 to 1/3 less stress than the conventional silicon nitride film, even if the first masking film 340 is formed thick, cracks caused by stress can be prevented, This is because the etching resistance is large with respect to the etchant for etching the insulating film. The formation thickness of the first masking layer 340 is determined in consideration of a function performed by the first masking layer 340 in a subsequent SAC etching step. The first masking film 340 is preferably formed to a thickness between 500 kPa and 2000 kPa.

The second masking film 350 may be formed of a polysilicon film using a CVD method, an LPCVD method, a PECVD method, a semi-Atmospheric Chemical Vapor Deposition (SACVD), a sputtering method, or an atomic layer deposition method. The reason why the second masking film 350 is formed of a polysilicon film will be described later. The formation thickness of the second masking film 350 may be determined in consideration of the function performed by the second masking film 350. Therefore, it is preferable that the second masking film 350 is formed to have a thickness between 500 kPa and 2000 kPa.

The first masking film 340 and the second masking film 350 are preferably formed in a time series in the same device in order to reduce the number of process steps. Of course, the first masking film 340 and the second masking film 350 may be formed in different devices. For example, when the first masking film 340 and the second masking film 350 are formed by using a PECVD method, the first masking film 340 and the second masking film 350 may be formed using the same apparatus. At this time, the supply gas supplied into the chamber of the apparatus should be different when forming the first masking film 340 and when forming the second masking film 350.

Referring to FIG. 2B, the upper portion is masked by patterning the gate oxide layer 320, the word line conductive layer 330, the first masking layer 340, and the second masking layer 350 by performing a photolithography process. The word line 330 'is formed. Subsequently, the source region 360 and the drain region 370 are formed by implanting a low concentration of conductive impurities such as n-type impurities into the semiconductor substrate 100 using the masked word line 330 'as an ion implantation mask. . A spacer 380 is then formed to mask the sidewalls of the wordline 330 '. The spacer 380 is preferably formed of a nitride film. For example, after the silicon nitride film is formed to a predetermined thickness on the entire surface of the semiconductor substrate 300, an anisotropic etching process is performed until the spacer 380 is formed.

After the spacer 380 is formed as described above, an upper portion of the word line 330 'is masked by the first masking layer 340' and the second masking layer 350 'and the sidewalls of the word line 330'. Is masked by the spacer 380. Masking the word line 330 'in this way, several advantages are found in subsequent steps. Accordingly, the following describes the effect of the wordline masking method according to the present invention by further explaining the subsequent steps performed after masking the wordline 330 '.

After forming the spacer 380 masking the sidewall of the word line 330 ', a high concentration of conductive impurities are implanted into the semiconductor substrate 300 using the masked word line 330' as an ion implantation mask. Form an LDD structure.

Referring to FIG. 2C, a first interlayer insulating layer 390 is formed on the entire surface of the semiconductor substrate 300 to fill between the masked word lines. The first interlayer insulating layer 390 may be formed of a BoroPhosphoSilicate Glass (BPSG) film, a Plasma Enhanced TetraEthlyOrthoSilicate Glass (PE-TEOS) film, an ozone-TEOS film, or an Undopped Silicate Glass (USG) film. The first interlayer insulating film can be formed using a CVD method, an LPCVD method or a PECVD method. Subsequently, the first interlayer insulating film 390 is planarized to substantially the same level as the second masking film 350 '. In order to planarize the first interlayer insulating layer 390, a chemical mechanical polishing method or an etch back method may be used. At this time, the second masking film 350 'is used as the planarization stop film. Particularly, when the second masking film 350 'is formed of a polysilicon film, the planarization stoppage is very large because the etching selectivity between the polysilicon film and the first interlayer insulating film 390 formed of an oxide-based insulating film is about 1:40. Excellent ability

Referring to FIG. 2D, to form a polysilicon pad on the source region 360 and the drain region 370, a contact hole exposing the source region 360 and the drain region 370 by performing a photolithography process may be performed. 400 is formed in the first interlayer insulating film 390. In particular, when the second masking film 350 ′ is formed of a polysilicon film, the second masking film 350 ′ is hardly etched in the process of forming the contact hole 400. This is because the etching selectivity between the first interlayer insulating film 390 and the second masking film 350 'made of an oxide-based insulating film is very large, such as 40: 1. As a result, it is possible to prevent the profile of the left and right upper corner portions II of the word line 330 'from being curved. After the contact hole 400 is formed as described above, a polysilicon film for filling the contact hole 400 is formed on the entire surface of the semiconductor substrate 300.

Referring to FIG. 2E, the polysilicon film 400 formed on the entire surface of the semiconductor substrate 300 using the first masking film 340 'as the planarization stop film is substantially formed on the upper surface of the first masking film 340'. Leveling to the same level. Then, a first poly pad 410 is formed on the source region 360, and a second poly pad 420 is formed on the drain region 370. Since the first masking film 340 'is used as the planarization stop film of the polysilicon film 400, the second masking film 350' is removed when the planarization step is completed. Therefore, it is possible to prevent the adjacent first poly pad 410 and the second poly pad 420 from being electrically connected to each other.

As described above, when the word line 330 'is masked by using the word line masking method according to the present invention, a material film for masking the upper and left upper corners of the word line 330' may be formed of the first poly pad 410 and the first poly pad 410. 2 is not consumed in the process of forming the poly pad 420. As a result, it is possible to prevent a short circuit between the storage node and the word line when forming the opening in which the storage node of the capacitor is to be formed in the insulating film by using the SAC etching technique in a subsequent step.

Hereinafter, a preferred embodiment of the bit line masking method according to the present invention will be described in detail with reference to FIGS. 3A to 3G. 3A to 3G are cross-sectional views of the semiconductor substrate 300 viewed in the direction in which the bit lines travel (the Y-axis direction). In addition, FIGS. 3A to 3G illustrate process steps performed after forming the first poly pad 410 and the second poly pad (see 420 of FIG. 2E) in different directions.

Referring to FIG. 3A, after forming the first poly pad 410 and the second poly pad (420 of FIG. 2E), a second interlayer insulating film 430 is formed on the entire surface of the semiconductor substrate 300. Then, the bit line conductive film 440, the first masking film 450, and the second masking film 460 are sequentially formed.

Although not shown in the drawings, a barrier film may be formed on the second interlayer insulating film 430 before the bit line conductive film 440 is formed. For example, a double film made of a Ti film / TiN film can be formed. However, it is natural to those skilled in the art that the barrier film is not limited to a double film made of a Ti film / TiN film.

The bit line conductive film 440 may be formed of a polysilicon film or a silicide film (eg, a tungsten silicide film). In addition, when the bit line is formed of a polyside structure, the conductive film 440 for the bit line may be formed in multiple layers. For example, when the bit line conductive film 440 is formed as a double film, the first masking film 450 and the second masking film 460 are sequentially formed after the polysilicon film and the silicide film are sequentially formed. Can be formed. Preferred Material Films and Forming Methods That Can Be Formed with Silicide Films The embodiments of the word line masking method according to the present invention have been described. In addition, the preferred material film, the formation method, and the formation thickness that can be formed of the first and second masking films 450 and 460 have been described with reference to the embodiment of the word line masking method according to the present invention. .

Although not specifically illustrated in the drawings, the first masking film 450 or the second masking film 460 is further stacked instead of sequentially stacking the first masking film 450 and the second masking film 460. It can also form only.

Referring to FIG. 3B, a bit line conductive layer 440, a first masking layer 450, and a second masking layer 460 are patterned by performing a photolithography process, thereby forming an upper portion of the bit line 440 ′. To form. A spacer 470 is then formed to mask the sidewall of the bit line 440 '. The spacer 470 is preferably formed of a nitride film. The method of forming the spacer 470 has been described with reference to an embodiment of the word line masking method according to the present invention.

After forming the spacers 470 masking sidewalls of the bit lines 440 ', a third interlayer insulating film 480 is formed on the entire surface of the semiconductor substrate 300. The third interlayer insulating film 480 can be formed using the same method as that which can be used to form the first interlayer insulating film (see 390 in FIG. 2C). The third interlayer insulating film 480 may be formed of the same kind of material film as the material film that can be formed of the first interlayer insulating film (see 390 of FIG. 2C). Then, using the second masking film 460 'as the planarization stop film, the upper surface of the third interlayer insulating film 480 is planarized to substantially the same level as the upper surface of the second masking film 460'. The planarization of the third interlayer insulating film 480 may be performed using a chemical mechanical polishing method or an etch back method. In particular, when the second masking film 460 'is formed of a polysilicon film, the second masking film 480' functions as an excellent planarization stop film. This is because the etching selectivity between the second masking film 480 'made of the polysilicon film and the third interlayer insulating film 480 made of the oxide film-based insulating film is very large, such as 1:40.

Referring to FIG. 3C, the second masking layer 460 ′ is removed using a wet etching method. For example, when the second masking layer 460 ′ is formed of a polysilicon layer, the second masking layer may be removed using a wet etching method using a polyetchant as an etchant. Meanwhile, a portion of the third interlayer insulating film 480 is also removed in the process of removing the second masking film 460 '. Therefore, the upper surface of the third interlayer insulating film 480 that is substantially at the same level as the upper surface of the second masking film 460 'is lowered in the process of removing the second masking film 460'. As a result, when the second masking film 460 'is removed, the upper end portion of the spacer 470' is exposed.

Referring to FIG. 3D, a stopper nitride film 490 is formed on the entire surface of the semiconductor substrate 300. The stopper nitride film 490 is preferably formed to a thickness between 100 mW and 500 mW using the LPCVD method, the PECVD method or the SACVD method. When the stopper nitride film 490 is formed, the masking film thickness of the upper and left upper corner portions III of the bit line 440 'is reinforced. In some cases, a silicon film or a silicon nitride film having a refractive index of 2.2 to 2.5 may be formed instead of the stopper nitride film 490.

As described above, in the bit line masking method according to the present invention, the upper portion of the bit line 440 'is masked by a double layer formed of the first masking layer 450' and the second masking layer 460 '. The sidewall of the bit line 440 'is masked by the nitride film spacer 470, and the thickness of the masking film of the upper and left upper corner portions III of the bit line 440' is reinforced by the stopper nitride film 490. As such, masking the upper portion of the bit line 440 with a double layer and reinforcing the thickness of the masking layer of the upper and left upper corner portions III of the bit line 440 'may increase the process margin in a subsequent SAC etching step. do. Therefore, hereinafter, the following description will be made of the subsequent process performed after masking the bit line 440 ', thereby describing the technical effect generated by the technical idea according to the present invention.

Referring to FIG. 3E, after the stopper nitride film 490 is formed, a fourth interlayer insulating film 500 is formed on the entire surface of the semiconductor substrate 300. The type of material film that can be formed of the fourth interlayer insulating film 500 and the method of forming the same are the same as the type of material film that can form the first interlayer insulating film (see 390 in FIG. 2C) and the method of forming the same. Subsequently, a photo process is performed to form the photoresist pattern 510 on the fourth interlayer insulating film 500. The photoresist pattern 510 is used as an etching mask in a subsequent etching step.

Referring to FIG. 3F, by etching the fourth interlayer insulating film 500 using the photoresist pattern 510 as an etching mask, a first etching step of exposing the stopper nitride film 490 is performed. The first etching step may be a dry etching method using CF ₄ gas or C ₄ F ₈ gas as an etching gas, for example, a magnetic enhanced reactive ion etching (MERIE) method or a reactive ion etching (RIE) method.

Referring to FIG. 2G, a second etching step of removing the stopper nitride film 490 exposed by the etching step is performed. In the second etching step, a dry etching method using CF ₄ gas as an etching gas, for example, a MERIE method or a RIE method is preferably used.

After removing the exposed stopper nitride layer 490 by performing the second etching step, the first poly pad 410 is removed by removing the third interlayer insulating layer 480 formed under the exposed stopper nitride layer 490. Proceed to the SAC etching step. When the upper surface of the first poly pad 410 is exposed by the SAC etching step, an opening 520 in which a storage node of the capacitor is formed is formed. The SAC etching step may be a dry etching method using a CF ₄ gas or a C ₄ F ₈ gas as an etching gas, for example, a MERIE method or a RIE method.

In the above, three etching steps were performed to form the openings 520. However, in some cases, the opening 520 may be formed by performing a single etching step.

After the opening 52 is formed, a storage electrode (not shown) of a capacitor is formed in the opening 520. However, since the thickness of the masking film on the left and right upper corner portions of the bit line 440 'is reinforced by the stopper nitride film 490, the bit line 440' is prevented from being exposed to the outside during the opening 520 process. can do. As a result, an electrical short may be prevented between the storage node (not shown) of the capacitor formed in the opening 520 and the bit line 440 ′.

In the above, the present invention has been described with reference to the embodiments, which are merely exemplary. Thus, it will be apparent to those skilled in the art that various modifications or other equivalent embodiments may be devised from the disclosed embodiments.

The method for masking a word line according to the present invention may prevent the masking layer of the upper and left upper corner portions of the word line from being rounded off while forming the poly pad on the source and drain regions. As a result, it is possible to prevent the word line from being exposed during the opening process by the subsequent SAC etching.

In the method for masking a bit line according to the present invention, the bit line may be prevented from being exposed in the opening process by subsequent SAC etching by reinforcing the thickness of the masking layer of the upper and left upper corner portions of the bit line.

Claims (6)

Sequentially forming a gate oxide film, a word line conductive film, a first masking film and a second masking film on an active region defined by the device isolation film; Patterning the gate oxide layer, the word line conductive layer, the first masking layer, and the second masking layer to form a word line, the upper side of which is masked with a double layer; And Forming a nitride spacer that masks the sidewalls of the wordline. The method of claim 1, And the first masking film is a silicon nitride film having a refractive index of 2.2 to 2.5, and the second masking film is a polysilicon film. Sequentially forming a bit line conductive film, a first masking film, and a second masking film on the interlayer insulating film formed on the entire surface of the semiconductor substrate; Patterning the bit line conductive layer, the first masking layer, and the second masking layer to form a bit line having an upper portion masked with a double layer; And Forming a nitride spacer to mask sidewalls of the bitlines. The method of claim 3, wherein after forming the nitride film spacer, Forming an insulating film on the same level as the upper surface of the second masking film, the insulating film filling the gap between the bit lines masked by the first and second masking layers and the sidewalls of the first and second masking layers; Removing the second masking film using a wet etching method; And Forming a nitride film, a silicon film, or a silicon nitride film having a refractive index of 2.2 to 2.5 on the front surface of the semiconductor substrate to increase the masking film thickness of the upper and left upper corner portions of the bit line. How to mask. The method according to claim 3 or 4, The first masking film is a silicon nitride film having a refractive index of 2.2 to 2.5, And said second masking film is a polysilicon film. The method of claim 4, wherein And the nitride film, the silicon film, or the silicon nitride film having a refractive index of 2.2 to 2.5 is formed to a thickness of between 100 mW and 500 mW.