KR20030041655A - method of excluding smut from oxidized surface of heating slug in semiconductor package - Google Patents
method of excluding smut from oxidized surface of heating slug in semiconductor package Download PDFInfo
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- KR20030041655A KR20030041655A KR1020010072583A KR20010072583A KR20030041655A KR 20030041655 A KR20030041655 A KR 20030041655A KR 1020010072583 A KR1020010072583 A KR 1020010072583A KR 20010072583 A KR20010072583 A KR 20010072583A KR 20030041655 A KR20030041655 A KR 20030041655A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
Description
본 발명은 비전도성 및 접착성의 향상을 위해 반도체 패키지용 방열판의 표면에 형성시키는 산화피막층에 입상으로 붙어 있는 스머트(smut)를 제거하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for removing smut granularly attached to an oxide film layer formed on a surface of a heat sink for semiconductor packages to improve nonconductivity and adhesion.
정보통신기술의 지속적인 발달과 함께 반도체 기술 또한 고도로 발달하고 있는 가운데, 반도체 패키지를 소형화하고 집적화 하는데 있어서 현재에는 반도체 패키지의 열적 문제와 전기적 그라운딩 문제가 가장 큰 해결과제로 대두되고 있다.With the continuous development of information and communication technology, semiconductor technology is also highly developed, and thermal and electrical grounding problems of semiconductor packages are the biggest challenges in miniaturizing and integrating semiconductor packages.
이러한 반도체 패키지의 소형화 및 집적화 경향에 따라 PBGA(Plastic Ball Grid Array) 및 FCBGA(Flip-Chip Ball Grid Array) 등 현재 개발되어 많이 사용되고 있는 반도체 패키지는 칩에서 발생하는 열을 별도의 방열판을 부착함으로써 상기한 열적 문제를 해결해 나가고 있다.In accordance with the trend of miniaturization and integration of such semiconductor packages, semiconductor packages, such as plastic ball grid array (PBGA) and flip-chip ball grid array (FCBGA), which are being developed and used a lot, are attached to a heat sink to separate heat generated from a chip. I am solving a thermal problem.
뿐만 아니라 고집적화를 위해서는 많은 게이트(Gate)를 확보함과 동시에 전기적 안정성을 확보하기 위한 그라운딩 문제가 대두 되었는데, 최근에는 이 또한 상기한 방열판을 PCB기판이 그라운드영역과 전기적으로 접속시킴으로써 해결해 나가고 있다.In addition, the grounding problem for securing a large number of gates (Gate) and at the same time to ensure electrical stability has been raised for high integration, and recently, the heat sink is also solved by electrically connecting the heat sink to the PCB.
이러한 반도체 패키지용 방열판은 PBGA의 경우 일반적으로 도 1 및 도 2에서 도시하는 바와 같이 장착되어 사용되는데, 최근에는 구리(Cu)로 이루어진 베이스메탈(5a)의 접착성(PCB기판(1)과의 접착성 및 몰딩성을 높이기 위한)을 향상시키고 비전도성을 확보하기 위해 베이스메탈(5a) 표면에 산화피막층(5b)을 형성하여 사용하기도 한다. 도면의 미설명 부호 (2), (3), (4)는 순차적으로 솔더볼과 칩 및 와이어본드이다.In the case of a PBGA, such a heat sink for a semiconductor package is generally mounted and used as shown in FIGS. 1 and 2, and recently, adhesiveness of a base metal 5a made of copper (Cu) with a PCB substrate 1 In order to improve the adhesion and molding property) and to secure non-conductivity, an oxide film layer 5b may be formed on the surface of the base metal 5a. Reference numerals (2), (3), and (4) in the drawings are sequentially solder balls, chips, and wire bonds.
상기와 같이 산화처리를 통해 베이스메탈(5a)의 표면에 산화피막층(5b)이 형성된 방열판(5)의 산화피막층(5b)은 도 3에서 도시하는 바와 같이 산화구리(CuO)를 주성분으로 하는 침상구조(5b′)와 상기 침상구조(5b′) 상측에 입상으로 붙어 있는 스머트(5b″)로 이루어져 있다. 여기서 상기 스머트(smut)는 산화구리와 각종 이온결합물의 입상구조체이다.As shown in FIG. 3, the oxide film layer 5b of the heat sink 5 having the oxide film layer 5b formed on the surface of the base metal 5a through the oxidation treatment is made of copper oxide (CuO) as a main component. It consists of the structure 5b 'and the smut 5b ″ which is granularly attached to the acicular structure 5b'. Here, the smut is a granular structure of copper oxide and various ionic bonds.
이러한 산화처리된 방열판(5)은 침상구조(5b′)와 스머트(5b″)로 이루어진 산화피막층(5b)으로 인해 몰딩영역(5d)에서는 접착성이 향상되어 몰딩화합물(6)과의 몰딩이 용이해지고 신뢰성이 향상되는 장점이 있지만, 노출영역(5c)에서는 만질 경우 상기 침상구조(5b′) 상측에 입상으로 붙어 있는 스머트(5b″)가 쉽게 묻어 나오고 외관상으로도 시각효과가 상당히 떨어지며, 제원 및 상표 표기를 위한 마킹성이 현저하게 저하되어 패키지 제품의 상품성이 저하되는 문제가 있다. 그러므로 현재까지는 산화처리된 방열판(5)의 경우 노출영역(5c)에 해당하는 부분은 산화피막층을 박리하고 니켈이나 크롬을 도금하여 사용해 왔으나 이는 원가상승의 요인으로 작용하였다.Such an oxidized heat sink 5 has improved adhesion in the molding region 5d due to the oxide film layer 5b composed of a needle-like structure 5b 'and a smut 5b ″, thereby forming a molding with the molding compound 6. Although there is an advantage in that the ease and reliability are improved, in the exposed area 5c, when touched, the smut 5b ″, which is attached to the upper side of the needle-like structure 5b ', is easily buried, and the visual effect is considerably inferior in appearance. In addition, there is a problem that the marking property for the specification and trademark marking is significantly reduced, thereby reducing the productability of the packaged product. Therefore, up to now, in the case of the oxidized heat sink 5, the portion corresponding to the exposed area 5c has been used by peeling the oxide film layer and plating nickel or chromium, but this has caused a cost increase.
본 발명은 상기의 문제를 해결하기 위해 안출된 것으로, 방열판 산화피막층에 입상으로 형성되어 있는 스머트를 제거함으로써 시각효과를 높이고, 절연성 및 마킹성을 높여 패키지 제품의 상품성을 향상시키기 위한 반도체 패키지용 방열판의산화처리표면 스머트 제거방법을 제공함에 그 목적이 있다.The present invention has been made to solve the above problems, the semiconductor package for improving the visual effect, the insulation and marking properties to improve the productability of the package product by removing the smut formed granular in the heat sink oxide film layer It is an object of the present invention to provide a method for removing smut of an oxidized surface of a heat sink.
상기의 목적을 달성하기 위한 본 발명에 의한 방법은 산화처리된 반도체 패키지용 방열판의 산화피막층에 샌드블래스터입자를 강한 압력으로 분사하여 침상구조 상측에 입상으로 붙어 있는 스머트를 제거하는 것을 특징으로 한다.The method according to the present invention for achieving the above object is characterized in that sandblasting particles are sprayed with a strong pressure on the oxide film layer of the heat-dissipating plate for the oxidized semiconductor package to remove the smurt stuck in the granular structure on the upper side of the needle structure. .
도 1은 반도체 패키지용 방열판의 일실시예 사용 상태 단면도1 is a cross-sectional view of an embodiment using a heat sink for a semiconductor package
도 2는 반도체 패키지용 방열판의 일실시예 사용 상태 사시도Figure 2 is a perspective view of an embodiment using a heat sink for a semiconductor package
도 3은 산화처리된 반도체 패키지용 방열판의 산화피막층 구조를 도시한 확대 단면도3 is an enlarged cross-sectional view illustrating an oxide film layer structure of a heat sink for an oxidized semiconductor package;
도 4는 본 발명의 스머트 제거 원리를 도시한 개념도4 is a conceptual diagram illustrating the smut removal principle of the present invention.
도 5는 본 발명에 의해 스머트가 제거된 방열판의 산화피막층 구조를 도시한 확대 단면도Figure 5 is an enlarged cross-sectional view showing the oxide film layer structure of the heat sink in which the smut is removed by the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 베이스메탈20 : 산화피막층10: base metal 20: oxide film layer
21 : 침상구조22 : 스머트21: needle structure 22: smut
30 : 노출영역40 : 몰딩영역30: exposure area 40: molding area
50 : 볼록부60 : 샌드블래스터입자50: convex portion 60: sand blaster particles
100 : 방열판100: heat sink
이하 첨부된 도면을 참조한 상세한 설명으로 본 발명의 구체적인 특징 및 이점은 더욱 명확해 질 것이다.DETAILED DESCRIPTION Specific features and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.
첨부된 도면, 도 4는 본 발명의 스머트 제거 원리를 도시한 개념도이고, 도 5는 본 발명에 의해 스머트가 제거된 방열판의 산화피막층 구조를 도시한 확대 단면도이다.4 is a conceptual diagram illustrating a smut removal principle of the present invention, and FIG. 5 is an enlarged cross-sectional view illustrating an oxide film layer structure of a heat sink in which a smut is removed by the present invention.
본 발명은 상기 도면에서 도시한 바와 같이 샌드블래스트가공을 통해 침상구조(21) 상측에 입상으로 붙어 있는 스머트(22)를 강제로 제거하는 방법을 제시해 주는바 그 자세한 내용은 다음과 같다.The present invention suggests a method of forcibly removing the smurts 22 which are granularly attached to the upper side of the needle-like structure 21 through sand blasting as shown in the drawings.
일반적으로 반도체 패키지용 방열판(100)은 구리로 이루어진 베이스메탈(10) 원자재를 프레스가공한 후, 이를 산계열의 약품으로 산화처리하여 그 표면에 산화피막층(20)을 형성하게 된다.In general, the heat dissipation plate 100 for a semiconductor package press-processes a base metal 10 raw material made of copper, and then oxidizes it with an acid-based chemical to form an oxide film layer 20 on the surface thereof.
이와 같이 베이스메탈(10)의 표면에 산화피막층(20)이 형성된 방열판(100)은 일반적으로 노출영역(30) 부분이 외부로 노출되므로 본 발명에서는 이 부분의 스머트(22)를 제거하게 된다.As described above, the heat sink 100 having the oxide film layer 20 formed on the surface of the base metal 10 generally exposes the exposed area 30 to the outside, thereby removing the smut 22 of the portion. .
본 발명에서는 침상구조(21)의 상측에 입상으로 붙어있는 스머트(22)를 제거하기 위해서 도 4에서 도시하는 바와 같이 샌드블래스터(Sand Blaster)를 이용하여 수많은 샌드블래스터입자(60)를 상기 방열판(100)의 노출영역(30)을 향해 분사하게 되는데, 이때 샌드블래스터입자(60)의 분사압력은 1∼2㎏f/㎠가 바람직하다. 또한 상기 샌드블래스터입자(60)의 크기(Grain Size) 3∼5㎛가 바람직하며, 가공시간은 2∼3초가 바람직하다.In the present invention, as shown in Figure 4 in order to remove the smut 22 attached to the upper side of the needle-like structure (21) by using a sand blaster (Sand Blaster) a large number of sand blaster particles (60) to the heat sink It is sprayed toward the exposed area 30 of the (100), wherein the injection pressure of the sand blaster particles 60 is preferably 1 to 2kgf / ㎠. In addition, the grain size (Grain Size) of the sandblast 60 is preferably 3 to 5㎛, the processing time is preferably 2-3 seconds.
상기와 같은 조건에서 샌드블래스트가공된 산화피막층(20)의 표면은 도 5에서 도시하는 바와 같이 침상구조(21)의 상측에 붙어 있던 스머트(22)가 완전 제거된 상태를 이루게 됨으로써 외부에서 노출영역(30)을 만지더라도 묻어나오지 않게 되어 제품의 상품성이 향상된다.Under the above conditions, the surface of the sandblasted oxide film layer 20 is exposed to the outside by completely removing the smut 22 attached to the upper side of the needle structure 21 as shown in FIG. 5. Even if the area 30 is touched, it is not buried, and thus the productability of the product is improved.
뿐만아니라, 점착제 및 접착테이프 또는 몰딩화합물과 접하는 몰딩영역(40)은 접착성 및 몰딩성이 유지되고, 노출영역(30)에 제품의 제원 및 상표 등을 표기하기 위해 인쇄 등을 하기 위한 마킹성은 한층 더 향상되게 된다. 물론, 가공된 면 또한 침상구조를 이루기 때문에 접착성이 좋다.In addition, the molding region 40 in contact with the adhesive and the adhesive tape or molding compound is maintained in the adhesiveness and molding properties, the marking properties for printing, etc. to display the specifications and trademarks of the product in the exposed region 30 It will be further improved. Of course, the processed surface also forms a needle-like structure, the adhesion is good.
그리고 본 발명에 의한 방법으로 가공되어 스머트(22)가 제거된 방열판(100)의 산화피막층(20) 표면은 외관상 일반적인 몰딩화합물과 같은 무광의 흑색을 띠게 되는데, 이를 PBGA에 사용할때 노출영역(30)에 도금 등 별도의 조치를 취하지 않더라도 시각효과가 뛰어난 장점이 있다.And the surface of the oxide film layer 20 of the heat sink 100 is removed by the process according to the present invention, the smut 22 is removed to have a matte black color as the general molding compound in appearance, when used in PBGA exposed areas ( The visual effect is excellent even if no action is taken, such as plating.
또한, 상기 침상구조(21)가 비전도성을 띠기 때문에 방열판(100)의 사용시 비전도성이 요구될 경우에도 유용하게 사용할 수 있다.In addition, since the needle structure 21 is non-conductive, it may be usefully used even when non-conductivity is required when using the heat sink 100.
한편, 본 발명에 의한 방법은 상기한 PBGA에 사용되는 방열판 뿐만아니라FCBGA에 사용되는 방열판의 외부 노출영역을 가공하는데도 동일하게 적용할 수 있다.On the other hand, the method according to the present invention is equally applicable to processing not only the heat sink used for the PBGA but also the external exposed area of the heat sink used for the FCBGA.
이상의 명백한 설명과 같이 본 발명은 산화피막층(20)에 입상으로 형성되어 있는 스머트(22)를 제거함으로써 높은 시각효과를 얻을 수 있어 제품의 상품가치를 높일 수 있고, 절연성이 유지되며, 제원 및 상표 등의 표기를 위한 마킹성이 향상되는 효과가 있다.As described above, the present invention can obtain a high visual effect by removing the smut 22 formed granularly in the oxide film layer 20, thereby increasing the product value of the product, maintaining insulation, and There is an effect of improving the marking properties for the representation of the trademark.
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010072583A KR20030041655A (en) | 2001-11-21 | 2001-11-21 | method of excluding smut from oxidized surface of heating slug in semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020010072583A KR20030041655A (en) | 2001-11-21 | 2001-11-21 | method of excluding smut from oxidized surface of heating slug in semiconductor package |
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| KR20030041655A true KR20030041655A (en) | 2003-05-27 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5610577A (en) * | 1979-07-06 | 1981-02-03 | Agency Of Ind Science & Technol | Adhesion method |
| JPS59126773A (en) * | 1982-12-29 | 1984-07-21 | Fujitsu Ltd | Production of hammer |
| US4935058A (en) * | 1989-04-14 | 1990-06-19 | Core-Guard Industries, Inc. | Coating composition to prevent corrosion on metals |
| US5407544A (en) * | 1993-07-21 | 1995-04-18 | Dynamotive Corporation | Method for removal of certain oxide films from metal surfaces |
| US5672390A (en) * | 1990-11-13 | 1997-09-30 | Dancor, Inc. | Process for protecting a surface using silicate compounds |
-
2001
- 2001-11-21 KR KR1020010072583A patent/KR20030041655A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5610577A (en) * | 1979-07-06 | 1981-02-03 | Agency Of Ind Science & Technol | Adhesion method |
| JPS59126773A (en) * | 1982-12-29 | 1984-07-21 | Fujitsu Ltd | Production of hammer |
| US4935058A (en) * | 1989-04-14 | 1990-06-19 | Core-Guard Industries, Inc. | Coating composition to prevent corrosion on metals |
| US5672390A (en) * | 1990-11-13 | 1997-09-30 | Dancor, Inc. | Process for protecting a surface using silicate compounds |
| US5407544A (en) * | 1993-07-21 | 1995-04-18 | Dynamotive Corporation | Method for removal of certain oxide films from metal surfaces |
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