KR100501879B1 - Substrate for semiconductor and its manufacturing method - Google Patents
Substrate for semiconductor and its manufacturing method Download PDFInfo
- Publication number
- KR100501879B1 KR100501879B1 KR10-2000-0032218A KR20000032218A KR100501879B1 KR 100501879 B1 KR100501879 B1 KR 100501879B1 KR 20000032218 A KR20000032218 A KR 20000032218A KR 100501879 B1 KR100501879 B1 KR 100501879B1
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- circuit pattern
- semiconductor package
- film
- ball
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 37
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000010931 gold Substances 0.000 claims abstract description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052737 gold Inorganic materials 0.000 claims abstract description 14
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 14
- 239000010408 film Substances 0.000 claims description 41
- 239000010409 thin film Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 238000003486 chemical etching Methods 0.000 claims description 4
- 229920001187 thermosetting polymer Polymers 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 abstract description 16
- 230000001070 adhesive effect Effects 0.000 abstract description 16
- 239000003566 sealing material Substances 0.000 abstract description 2
- 239000008393 encapsulating agent Substances 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Chemically Coating (AREA)
Abstract
본 발명은 반도체패키지용 섭스트레이트 및 그 제조 방법에 관한 것으로, 섭스트레이트에 형성된 회로패턴중 일정 부분에만 도금을 수행함으로써 반도체패키지의 구성 요소인 섭스트레이트와 봉지재 및 접착제 사이의 접착력을 향상시키기 위해, 필름을 중심으로 그 일표면에는 반도체칩이 접착될 수 있도록 칩탑재영역이 구비되고, 상기 칩탑재영역의 내측 또는 그 외주연으로는 방사상의 본드핑거 및 볼랜드를 포함하는 다수의 회로패턴이 형성되어 이루어진 반도체패키지용 섭스트레이트에 있어서, 상기 회로패턴중 반도체칩과 도전성와이어로 접속되는 본드핑거 및 도전성볼이 융착되는 볼랜드의 표면에만 금/니켈로 일정 두께의 도금층이 형성된 것을 특징으로 함.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for a semiconductor package and a method of manufacturing the same, in order to improve adhesion between the substrate and the sealing material and the adhesive, which are components of the semiconductor package, by plating only a portion of a circuit pattern formed on the substrate. A chip mounting area is provided on one surface of the chip mounting area so that the semiconductor chip can be bonded. A plurality of circuit patterns including radial bond fingers and ball lands are formed on the inner or outer circumference of the chip mounting area. In the substrate package made of a semiconductor package, a plating layer having a predetermined thickness of gold / nickel is formed only on the surface of the ball pattern in which the bond finger connected to the semiconductor chip and the conductive wire and the ball of the conductive ball are fused.
Description
본 발명은 반도체패키지용 섭스트레이트 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 섭스트레이트에 형성된 회로패턴중 일정 부분에만 도금층을 형성함으로써, 차후 반도체패키지의 구성 요소인 봉지재 및 접착제와 그 섭스트레이트 사이의 접착력을 향상시킬 수 있는 반도체패키지용 섭스트레이트 및 그 제조 방법에 관한 것이다.The present invention relates to a substrate for a semiconductor package and a method of manufacturing the same. More specifically, the plating layer is formed only on a predetermined portion of a circuit pattern formed on the substrate, so that an encapsulant and an adhesive, which is a component of a semiconductor package, and its substation. The present invention relates to a substrate for a semiconductor package capable of improving the adhesive force between straight lines and a manufacturing method thereof.
통상 반도체패키지용 섭스트레이트는 반도체칩이 탑재되는 부재로서, 상기 반도체칩의 전기적 입출력신호가 마더보드에 전달될 수 있도록 전달해주는 역할과 상기 반도체칩 등이 마더보드 상에서 일정한 형태로 견고히 고정될 수 있도록 하는 역할을 한다.Substrate for a semiconductor package is a member on which a semiconductor chip is mounted, and serves to transmit electrical input / output signals of the semiconductor chip to the motherboard and to securely fix the semiconductor chip to a certain shape on the motherboard. It plays a role.
이러한 반도체패키지용 섭스트레이트는 구리 또는 구리 합금 등을 주재료로 하는 리드프레임, 열경화성 필름 및 구리 박막 등을 주재료로 하는 인쇄회로기판, 가요성 필름 및 구리 박막 등을 주재료로 하는 써킷필름, 가요성 테이프 및 구리 박막 등을 주재료로 하는 써킷 테이프 등 그 종류는 매우 다양하게 존재한다.Such substrates include semiconductors such as lead frames based on copper or copper alloys, printed circuit boards based on thermosetting films and copper thin films, circuit films based on flexible films and copper thin films, and flexible tapes. And circuit tapes mainly containing copper thin films and the like exist in a wide variety.
도1a는 상기한 섭스트레이트(10')의 한 종류를 도시한 평면도이며, 도1b 및 도1c는 상기 섭스트레이트(10')를 이용한 반도체패키지(PKG)를 도시한 단면도이다.FIG. 1A is a plan view showing one kind of the above-mentioned substrate 10 ', and FIGS. 1B and 1C are cross-sectional views illustrating a semiconductor package PKG using the substrate 10'.
이하의 설명에서, 상기 섭스트레이트(10')는 써킷 필름을 예로 하여 설명한다.In the following description, the substrate 10 'will be described using a circuit film as an example.
도시된 바와 같이 섭스트레이트(10')는 가요성 필름(11)을 중심으로 상면에는 다수의 도전성 회로패턴이 형성되고, 하면에는 상기 도전성 회로패턴의 소정 부분과 대응하는 부분에 다수의 통공(19)이 형성되어 있다.As illustrated, the substrate 10 ′ has a plurality of conductive circuit patterns formed on the upper surface of the substrate 10 ′, and a plurality of through holes 19 formed on the lower surface of the substrate 10 ′ corresponding to a predetermined portion of the conductive circuit pattern. ) Is formed.
상기 도전성 회로패턴은 주지된 바와 같이 구리 박막 또는 구리 합금 박막 계열이고, 이는 화학적 에칭에 의해 소정 형상으로 형성된 것이다. 상기 도전성 회로패턴은 필름(11)의 상면 중앙에 대략 바둑판 형상으로 다수의 더미패턴(15)이 형성되어 있고, 상기 더미패턴(15)의 외주연인 필름(11) 상면에는 다수의 본드핑거(13) 및 볼랜드(14)가 형성되어 있다. 물론, 상기 볼랜드(14)는 필름의 하면의 통공(19)을 통하여 외측으로 오픈된 부분을 지칭한다. 또한, 한조의 본드핑거(13) 및 볼랜드(14)는 회로패턴에 의해 서로 연결되어 외측으로 연장되어 있다. 또한, 상기 더미패턴(15)도 소정의 볼랜드(14)에 회로패턴으로 연결될 수 있다.As is well known, the conductive circuit pattern is a copper thin film or a copper alloy thin film series, which is formed in a predetermined shape by chemical etching. The conductive circuit pattern has a plurality of dummy patterns 15 formed in a substantially checkerboard shape at the center of the upper surface of the film 11, and a plurality of bond fingers 13 on the upper surface of the film 11, which is an outer circumference of the dummy pattern 15. ) And the borland 14 are formed. Of course, the ball land 14 refers to a portion opened outward through the through hole 19 of the lower surface of the film. In addition, the pair of bond fingers 13 and the borland 14 are connected to each other by a circuit pattern and extend outward. In addition, the dummy pattern 15 may also be connected to a predetermined ball land 14 in a circuit pattern.
더불어, 상기 더미패턴(15)의 하면인 필름(11)에도 통공(19)이 형성되어 랜드가 형성될 수 있으며, 경우에 따라서는 상기 더미패턴(15) 자체가 형성되지 않을 수도 있다. 도면중 미설명 부호 18은 차후 반도체칩이 탑재되는 칩탑재 영역이다.In addition, a through hole 19 may be formed in the film 11, which is a lower surface of the dummy pattern 15, so that lands may be formed. In some cases, the dummy pattern 15 itself may not be formed. In the figure, reference numeral 18 denotes a chip mounting region in which semiconductor chips are subsequently mounted.
이러한 섭스트레이트(10')를 이용한 반도체패키지(PKG)는 도1b 및 도1c에 도시된 바와 같이 상기 섭스트레이트(10')의 더미패턴(15) 상부에 접착제(22)가 개재되어 반도체칩(20)이 접착되어 있다. 여기서, 상기 더미패턴(15) 측부의 회로패턴 상부에까지 연장된 반도체칩(20)이 탑재될 수도 있다. 또한, 상기 반도체칩(20)과 회로패턴중 본드핑거(13)는 도전성와이어(21)에 의해 서로 접속되어 있다. 또한, 상기 회로패턴중 볼랜드(14)에는 각각 솔더볼과 같은 도전성볼(24)이 융착되어 있다. 더불어, 상기 섭스트레이트(10') 상면의 반도체칩(20), 도전성와이어(21) 등은 외부 환경으로부터 보호될 수 있도록 봉지재(23)로 봉지되어 있다.In the semiconductor package PKG using the substrate 10 ', the adhesive 22 is interposed on the dummy pattern 15 of the substrate 10' as shown in FIGS. 1B and 1C. 20) is bonded. Here, the semiconductor chip 20 extending to the upper portion of the circuit pattern of the dummy pattern 15 side may be mounted. The semiconductor chip 20 and the bond fingers 13 of the circuit patterns are connected to each other by conductive wires 21. Further, conductive balls 24 such as solder balls are fused to the ball lands 14 of the circuit patterns, respectively. In addition, the semiconductor chip 20, the conductive wire 21, and the like on the upper substrate 10 ′ are encapsulated with an encapsulant 23 so as to be protected from an external environment.
한편, 상기 섭스트레이트(10')의 더미패턴(15), 본드핑거(13) 및 볼랜드(14)를 포함하는 회로패턴 전체에는 금/니켈(Au/Ni) 등으로 일정 두께의 도금층(16)이 형성되어 있다. 이와 같이 도금층(16)을 형성하는 이유는 도전성와이어(21)와 본드핑거(13)의 접속력을 강화시키고, 또한 도전성볼(24)과 볼랜드(14)의 접속력을 강화시키기 위함이다.Meanwhile, the entire plating pattern including the dummy pattern 15, the bond finger 13, and the borland 14 of the substrates 10 ′ is plated with a predetermined thickness of gold / nickel (Au / Ni). Is formed. The reason why the plating layer 16 is formed as described above is to reinforce the connecting force between the conductive wire 21 and the bond finger 13 and to reinforce the connecting force between the conductive ball 24 and the ball land 14.
그러나, 이러한 도금층은 다음과 같은 문제를 야기하는 단점이 있다.However, such a plating layer has a disadvantage of causing the following problems.
첫째, 통상 금/니켈과 유기 화합물은 접착력이 약한 것으로 알려져 있다. 즉, 극성을 띄는 유기고분자 화합물(예를 들면, 상기 봉지재 및 접착제)은 비극성이고 반응성이 적은 금속(예를 들면, 상기 금/니켈)과의 접착력이 약하기 때문이다. 따라서, 상기 완성된 반도체패키지는 상기 섭스트레이트에 형성된 도금층과 봉지재, 도금층과 접착제 사이에서 계면박리가 빈번히 발생하게 되고, 더불어 상기 몸체의 외곽부에서 섭스트레이트가 쉽게 떼어지기도 한다.First, gold / nickel and organic compounds are generally known to have poor adhesion. That is, the polar organic polymer compound (eg, the encapsulant and adhesive) has a weak adhesion with a nonpolar and less reactive metal (eg, the gold / nickel). Accordingly, the completed semiconductor package frequently causes interfacial peeling between the plating layer and the encapsulant formed on the substrate, the plating layer and the adhesive, and the substrate is easily detached from the outer portion of the body.
둘째, 실제로 상기 금/니켈 도금층이 필요한 부분은 도전성와이어가 접속되는 본드핑거와 도전성볼이 융착되는 볼랜드(필름의 개구부를 통해 하부로 오픈된 영역)뿐이다. 그럼에도 불구하고 상기 본드핑거 및 볼랜드를 포함하는 회로패턴 및 더미패턴 모두에 도금층을 형성하는 이유는 제조 공정이 단순해지기 때문이다. 그러나, 상기와 같이 불필요한 부분에도 모두 금/니켈의 도금층을 형성함으로써 섭스트레이트 및 반도체패키지의 가격을 상승시키는 원인이 되고 있다.Second, the only part where the gold / nickel plating layer is actually required is the bond finger to which the conductive wire is connected and the ball land (the area opened downward through the opening of the film) to which the conductive ball is fused. Nevertheless, the reason why the plating layer is formed on both the circuit pattern and the dummy pattern including the bond finger and the ball land is because the manufacturing process is simplified. However, by forming the gold / nickel plating layer on all unnecessary portions as described above, it is a cause of increasing the price of the substrate and the semiconductor package.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 섭스트레이트에 형성된 회로패턴중 일정 부분에만 도금을 수행함으로써 반도체패키지의 구성 요소인 섭스트레이트와 봉지재 및 접착제 사이의 접착력을 향상시킬 수 있는 반도체패키지용 섭스트레이트 및 그 제조 방법을 제공하는데 있다.Therefore, the present invention has been made to solve the above-mentioned conventional problems, and by performing plating only a portion of the circuit pattern formed on the substrate to improve the adhesion between the substrate and the sealing material and the adhesive component of the semiconductor package; The present invention provides a substrate for a semiconductor package and a method of manufacturing the same.
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지용 섭스트레이트는 필름을 중심으로 그 일표면에는 반도체칩이 접착될 수 있도록 칩탑재영역이 구비되고, 상기 칩탑재영역의 내측 또는 그 외주연으로는 방사상의 본드핑거 및 볼랜드를 포함하는 다수의 회로패턴이 형성되어 이루어진 반도체패키지용 섭스트레이트에 있어서, 상기 회로패턴중 반도체칩과 도전성와이어로 접속되는 본드핑거 및 도전성볼이 융착되는 볼랜드의 표면에만 금/니켈로 일정 두께의 도금층이 형성된 것을 특징으로 한다.In order to achieve the above object, the substrate for semiconductor package according to the present invention is provided with a chip mounting area such that a semiconductor chip can be adhered to one surface of the film center, and the inner or outer circumference of the chip mounting area. Is a substrate for semiconductor packages in which a plurality of circuit patterns including radial bond fingers and ball lands are formed, wherein only the surfaces of the ball lands where the bond fingers and conductive balls fused to the semiconductor chip and the conductive wires of the circuit patterns are fused. Gold / nickel is characterized in that a plated layer of a predetermined thickness is formed.
여기서, 상기 도금층이 형성되지 않은 회로패턴에는 일정 두께의 산화막이 더 형성될 수 있다.Here, an oxide film having a predetermined thickness may be further formed on the circuit pattern in which the plating layer is not formed.
상기 필름은 열경화성 수지, 가요성 필름 또는 가요성 테이프중 어느 하나일 수 있다.The film may be any one of a thermosetting resin, a flexible film, or a flexible tape.
또한, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지용 섭스트레이트의 제조 방법은 다수의 통공이 어레이되어 형성된 필름의 일면에 일정 두께의 금속박막층이 형성된 원판을 제공하는 단계와; 상기 원판의 금속박막층에 포토마스킹 및 화학적 에칭을 가하여 본드핑거 및 상기 통공을 통해 외측으로 오픈되는 볼랜드 등을 포함하는 다수의 회로패턴을 형성하는 패터닝 단계와; 상기 회로패턴중 본드핑거를 제외한 회로패턴 일면에 레지스트를 도포하는 단계와; 상기 레지스트 외측으로 오픈된 본드핑거 표면과 상기 필름의 통공을 통해 외측으로 노출된 볼랜드 표면에 금/니켈로 일정 두께의 도금층을 형성하는 단계와; 상기 회로패턴에 형성된 레지스트를 제거하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, the method for producing a substrate for a semiconductor package according to the present invention in order to achieve the above object comprises the steps of providing a disc formed with a metal thin film layer of a predetermined thickness on one surface of the film formed by the array of a plurality of holes; A patterning step of forming a plurality of circuit patterns including a bond finger and a ball land open to the outside through the through hole by applying photomasking and chemical etching to the metal thin film layer of the original plate; Applying a resist to one surface of the circuit pattern except for the bond finger of the circuit pattern; Forming a plating layer having a predetermined thickness of gold / nickel on the bond finger surface opened to the outside of the resist and the ball land surface exposed to the outside through a through hole of the film; And removing the resist formed on the circuit pattern.
여기서, 상기 레지스트 제거 단계 후 도금이 형성되지 않은 회로패턴 표면에 산화막을 형성하는 단계가 더 포함될 수도 있다.Here, after the resist removing step, the step of forming an oxide film on the surface of the circuit pattern where the plating is not formed may be further included.
상기와 같이 하여 본 발명에 의한 반도체패키지용 섭스트레이트 및 그 제조 방법에 의하면 섭스트레이트에 형성된 회로패턴중 일정 부분에만 도금을 수행함으로써, 반도체패키지의 구성 요소가 되는 섭스트레이트와 봉지재, 섭스트레이트와 접착제 사이의 접착력이 향상된다.As described above, according to the present invention for the semiconductor package substrate and the manufacturing method thereof, by plating only a portion of the circuit pattern formed on the substrate, the substrate, the encapsulant, the substrate and The adhesion between the adhesives is improved.
또한, 실제로 도금이 필요한 영역 즉, 본드핑거 및 볼랜드에만 도금층을 형성함으로써, 그 도금에 사용되는 재료를 절약할 수 있음은 물론, 그 섭스트레이트 및 반도체패키지의 제조비를 절감할 수 있게 된다.In addition, by forming the plating layer only in the area where the plating is actually required, that is, the bond finger and the borland, the material used for the plating can be saved, and the manufacturing cost of the substrate and the semiconductor package can be reduced.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도2a는 본 발명의 제1실시예에 의한 반도체패키지용 섭스트레이트(10)를 도시한 평면도이고, 도2b는 상기 섭스트레이트(10)를 이용한 반도체패키지의 일부를 도시한 단면도이다.FIG. 2A is a plan view showing a substrate 10 for semiconductor package according to the first embodiment of the present invention, and FIG. 2B is a cross-sectional view showing a part of the semiconductor package using the substrate 10.
도시된 바와 같이 필름(11)을 중심으로 그 일표면에는 반도체칩(20)이 접착될 수 있도록 칩탑재영역(18)이 구비되어 있고, 상기 칩탑재영역(18)의 내측 또는 그 외주연으로는 방사상의 본드핑거(13) 및 볼랜드(14)를 포함하는 다수의 회로패턴이 형성되어 있다.As shown, a chip mounting region 18 is provided on one surface of the film 11 to bond the semiconductor chip 20 to the inner surface of the chip mounting region 18. The plurality of circuit patterns including the radial bond finger 13 and the ball land 14 is formed.
여기서, 상기 필름(11)은 열경화성수지, 필름 또는 테이프 등일 수 있다. 또한 상기 볼랜드(14)는 본드핑거(13)가 형성된 동일면에 형성되어 있으나, 통상 도2b에서처럼 필름(11)에 형성된 통공(12)을 통해 오픈된 영역을 지칭한다.Here, the film 11 may be a thermosetting resin, a film or a tape. In addition, although the ball land 14 is formed on the same surface on which the bond finger 13 is formed, it generally refers to a region opened through the through hole 12 formed in the film 11 as shown in FIG.
또한, 상기 칩탑재영역(18)에는 전체적인 섭스트레이트(10)의 휨 현상을 방지하고, 또한 차후 반도체칩(20)의 그라운드/파워신호를 처리하기 위한 더미패턴(15)이 형성될 수 있다.In addition, a dummy pattern 15 may be formed in the chip mounting region 18 to prevent warpage of the overall substrate 10 and to process a ground / power signal of the semiconductor chip 20 later.
상기 회로패턴중 반도체칩(20)과 도전성와이어(21)로 접속되는 본드핑거(13) 및 도전성볼(24)이 융착되는 볼랜드(14)의 표면에는 금/니켈 등의 금속으로 일정 두께의 도금층(16)이 전해 또는 무전해 도금되어 있다.In the circuit pattern, the surface of the bond finger 13 connected to the semiconductor chip 20 and the conductive wire 21 and the ball land 14 to which the conductive ball 24 is fused are made of a metal such as gold / nickel and has a predetermined thickness. (16) is electrolytically or electrolessly plated.
또한, 상기 본드핑거(13) 이외의 회로패턴과 더미패턴(15)에는 도금층(16)이 전혀 형성되어 있지 않다.In addition, the plating layer 16 is not formed at all on the circuit pattern and the dummy pattern 15 other than the bond finger 13.
따라서, 봉지재(23) 또는 접착제(22)와 접착력이 비교적 양호한 필름(11), 본드핑거(13)를 제외한 회로패턴 및 더미패턴(15)이 차후 상기 봉지재(23) 및 접착제(22)와 직접 접착하게 됨으로써 종래의 계면박리 현상이 저하된다.Accordingly, the encapsulant 23 or the adhesive 22 and the film 11 having a relatively good adhesive strength and the circuit pattern and the dummy pattern 15 except for the bond finger 13 are subsequently formed on the encapsulant 23 and the adhesive 22. By adhering directly with, the conventional interface peeling phenomenon is lowered.
도면중 대략 사각 띠 모양으로 도시한 도면부호 PL은 금/니켈 등으로 도금되는 도금 영역이며, 상기 도금 영역 중에서 본드핑거(13) 표면에 일정 두께의 도금층(16)이 형성된다.In the figure, the reference numeral PL shown in a substantially square band shape is a plating region plated with gold / nickel or the like, and a plating layer 16 having a predetermined thickness is formed on the surface of the bond finger 13 among the plating regions.
한편, 도3a는 본 발명의 제2실시예에 의한 반도체패키지용 섭스트레이트(10)를 도시한 평면도이고, 도3b는 상기 섭스트레이트(10)를 이용한 반도체패키지의 일부를 도시한 단면도이다.3A is a plan view showing a substrate 10 for semiconductor packages according to a second embodiment of the present invention, and FIG. 3B is a cross-sectional view showing a part of a semiconductor package using the substrate 10.
도시된 바와 같이 섭스트레이트(10)의 금/니켈 도금층(16)이 형성되지 않은 회로패턴 및 더미패턴(15)에는 일정두께의 산화막(17)이 더 형성되어 있다. 통상 상기 산화막(17)은 봉지재 및 접착제(22)와의 접착력이 우수하다. 따라서, 차후 반도체패키지의 구성 요소가 되는 봉지재(23) 및 접착제(22)가 상기 섭스트레이트(10) 및 회로패턴에 더욱 강하게 접착됨으로써 계면박리 현상을 한층 억제할 수 있게 된다.As illustrated, an oxide film 17 having a predetermined thickness is further formed on the circuit pattern and the dummy pattern 15 in which the gold / nickel plating layer 16 of the substrate 10 is not formed. Usually, the oxide film 17 has excellent adhesion with the encapsulant and the adhesive 22. Accordingly, the encapsulant 23 and the adhesive 22, which are components of the semiconductor package in the future, are more strongly adhered to the substrate 10 and the circuit pattern, thereby further suppressing the interface peeling phenomenon.
도면중 도금 영역(PL)의 내측 및 바깥쪽에 도시된 도면 부호 OL은 산화막이 형성되는 영역이다. 실제 본드핑거(13) 및 필름(11)의 통공(19)을 통해 외측으로 노출된 볼랜드(14)를 제외한 영역 즉, 차후 봉지재(23)와 접착제(22)로 접착되는 영역의 회로패턴 표면에 산화막(17)이 형성된다.In the figure, reference numeral OL shown inside and outside the plating region PL is a region where an oxide film is formed. The surface of the circuit pattern of the area except the ball land 14 exposed to the outside through the actual bond finger 13 and the through hole 19 of the film 11, that is, the area that is subsequently bonded with the encapsulant 23 and the adhesive 22. An oxide film 17 is formed in the film.
도4는 본 발명에 의한 반도체패키지용 섭스트레이트(10)의 제조 방법을 도시한 순차 설명도이고, 도5a 내지 도5f는 본 발명에 의한 반도체패키지용 섭스트레이트(10)의 제조 방법을 도시한 부분 단면도이다.4 is a sequential explanatory view showing a method for manufacturing a semiconductor package substratum 10 according to the present invention, and FIGS. 5A to 5F show a method for manufacturing a semiconductor package substratum 10 according to the present invention. It is a partial cross section.
1. 원판 제공 단계로서, 다수의 통공(12)이 어레이되어 형성된 필름(11)의 일면에 일정두께의 금속박막층(M, 예를 들면 구리박막층)이 형성된 원판을 제공한다.(도5a 참조)1.A disc providing step, which provides a disc having a metal thin film layer (M, for example, a copper thin film layer) of a predetermined thickness on one surface of the film 11 formed by arranging a plurality of through holes 12 (see Fig. 5a).
2. 패터닝 단계로서, 상기 원판의 금속박막층(M)상에 통상적인 포토마스킹 및 화학적 에칭을 수행하여 본드핑거(13) 및 볼랜드(14)를 포함하는 회로패턴을 형성한다. 이때, 전술한 바와같은 더미패턴(15)을 형성할 수도 있다. 여기서, 상기 필름(11)의 통공(12)을 통해서는 볼랜드(14)가 오픈되도록 한다.(도5b 참조)2. As a patterning step, conventional photomasking and chemical etching are performed on the metal thin film layer M of the original plate to form a circuit pattern including the bond finger 13 and the ball land 14. At this time, the dummy pattern 15 as described above may be formed. Here, the borland 14 is opened through the through hole 12 of the film 11 (see FIG. 5B).
3. 부분 레지스트 도포 단계로서, 상기 회로패턴중 본드핑거(13)를 제외한 회로패턴 일면에 레지스트(R)를 도포한다. 이때, 상기 본드핑거(13)가 형성된 면에만 레지스트(R)를 도포하고 그 반대면에는 레지스트를 도포하지 않는다.(도5c 참조)3. As a partial resist coating step, a resist R is applied to one surface of the circuit pattern except for the bond finger 13 of the circuit pattern. At this time, the resist R is applied only to the surface on which the bond finger 13 is formed, and the resist is not applied to the opposite surface thereof (see FIG. 5C).
4. 도금 단계로서, 상기 레지스트 외측으로 오픈된 본드핑거(13) 표면과 상기 필름(11)의 통공(12)을 통해 외측으로 오픈된 볼랜드(14) 표면에 금/니켈 등의 금속으로 일정 두께의 도금층(16)을 형성한다. 상기 도금 방법은 주지된 바와 같이 전해 도금 또는 무전해 도금 방법을 이용할 수 있으며, 상기 두가지 방법을 병행할 수도 있다.(도 5d 참조)4. As a plating step, a predetermined thickness of metal such as gold / nickel on the surface of the bond finger 13 opened to the outside of the resist and the surface of the ball land 14 opened to the outside through the through hole 12 of the film 11. Plating layer 16 is formed. The plating method may use an electrolytic plating or an electroless plating method as is well known, and the two methods may be used in parallel (see FIG. 5D).
5. 레지스트 제거 단계로서, 상기 회로패턴에 형성된 레지스트를 제거한다. 상기와 같이 레지스트가 제거된 섭스트레이트는 제품으로서 바로 출하 가능하다.(도 5e 참조)5. As a resist removing step, the resist formed in the circuit pattern is removed. The substrate having the resist removed as described above can be shipped as a product (see FIG. 5E).
6. 산화막(17) 형성 단계로서, 상기 도금층(16)이 형성되지 않은 회로패턴 표면에 일정 두께의 산화막(17)을 더 형성하여 제품으로 출하한다. 이때 상기 산화막(17) 형성 방법은 공기중에 장시간 섭스트레이트(10)를 노출시키거나 또는 일정한 열을 가하여 그 산화막(17) 형성 시간을 단축시킬 수도 있다.(도5f 참조)6. As an oxide film 17 forming step, an oxide film 17 having a predetermined thickness is further formed on the surface of the circuit pattern on which the plating layer 16 is not formed and shipped as a product. In this case, the oxide film 17 may be formed by exposing the substrate 10 for a long time in air or by applying a constant heat to shorten the formation time of the oxide film 17 (see FIG. 5F).
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
상기와 같이 하여 본 발명에 의한 반도체패키지용 섭스트레이트 및 그 제조 방법에 의하면 섭스트레이트에 형성된 회로패턴중 일정 부분에만 도금을 수행함으로써, 반도체패키지의 구성 요소가 되는 섭스트레이트와 봉지재, 섭스트레이트와 접착제 사이의 접착력이 향상되는 효과가 있다.As described above, according to the present invention for the semiconductor package substrate and the manufacturing method thereof, by plating only a portion of the circuit pattern formed on the substrate, the substrate, the encapsulant, the substrate and There is an effect that the adhesion between the adhesives is improved.
또한, 실제로 도금이 필요한 영역 즉, 본드핑거 및 볼랜드에만 도금층을 형성함으로써, 그 도금에 사용되는 재료를 절약할 수 있음은 물론, 그 섭스트레이트 및 반도체패키지의 제조비를 절감할 수 있는 효과가 있다.In addition, by forming the plating layer only in the area that actually requires plating, that is, the bond finger and the borland, the material used for the plating can be saved, and the manufacturing cost of the substrate and the semiconductor package can be reduced.
도1a는 종래의 반도체패키지용 섭스트레이트를 도시한 평면도이고, 도1b는 상기 섭스트레이트를 이용한 반도체패키지의 단면도이며, 도1c는 상기 반도체패키지의 부분 학대도이다.FIG. 1A is a plan view showing a conventional semiconductor package substrate, FIG. 1B is a cross-sectional view of a semiconductor package using the substrate, and FIG. 1C is a partial abuse view of the semiconductor package.
도2a는 본 발명의 제1실시예에 의한 반도체패키지용 섭스트레이트를 도시한 평면도이고, 도2b는 상기 섭스트레이트를 이용한 반도체패키지의 일부를 도시한 단면도이다.FIG. 2A is a plan view showing a substrate for a semiconductor package according to a first embodiment of the present invention, and FIG. 2B is a cross-sectional view showing a part of a semiconductor package using the substrate.
도3a는 본 발명의 제2실시예에 의한 반도체패키지용 섭스트레이트를 도시한 평면도이고, 도3b는 상기 섭스트레이트를 이용한 반도체패키지의 일부를 도시한 단면도이다.FIG. 3A is a plan view showing a substrate for a semiconductor package according to a second embodiment of the present invention, and FIG. 3B is a cross-sectional view showing a portion of a semiconductor package using the substrate.
도4는 본 발명에 의한 반도체패키지용 섭스트레이트의 제조 방법을 도시한 순차 설명도이다.4 is a sequential explanatory diagram showing a method for manufacturing a substrate for semiconductor package according to the present invention.
도5a 내지 도5f는 본 발명에 의한 반도체패키지용 섭스트레이트의 제조 방법을 도시한 부분 단면도이다.5A to 5F are partial cross-sectional views showing a method for manufacturing a substrate for semiconductor package according to the present invention.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
10; 본 발명에 의한 반도체패키지용 섭스트레이트10; Substrate for semiconductor package according to the present invention
11; 필름 12; 통공11; Film 12; Through
13; 본드핑거 14; 볼랜드13; Bondfinger 14; Borland
15; 더미패턴 16; 도금층15; Dummy pattern 16; Plated layer
17; 산화막 18; 칩탑재영역17; Oxide film 18; Chip loading area
19; 통공19; Through
20; 반도체칩 21; 도전성와이어20; Semiconductor chip 21; Conductive Wire
22; 접착제 23; 봉지재22; Adhesive 23; Encapsulant
24; 도전성볼24; Conductive ball
PKG; 본 발명에 의한 섭스트레이트를 이용한 반도체패키지PKG; Semiconductor Package Using Substrate According to the Present Invention
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0032218A KR100501879B1 (en) | 2000-06-12 | 2000-06-12 | Substrate for semiconductor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0032218A KR100501879B1 (en) | 2000-06-12 | 2000-06-12 | Substrate for semiconductor and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010111662A KR20010111662A (en) | 2001-12-20 |
| KR100501879B1 true KR100501879B1 (en) | 2005-07-18 |
Family
ID=43671668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0032218A KR100501879B1 (en) | 2000-06-12 | 2000-06-12 | Substrate for semiconductor and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100501879B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02172265A (en) * | 1988-12-23 | 1990-07-03 | Mitsubishi Electric Corp | Resin seal type semiconductor device |
| JPH0982870A (en) * | 1995-09-14 | 1997-03-28 | Toshiba Corp | Semiconductor device, lead frame, and manufacture thereof |
| JPH11260962A (en) * | 1998-03-12 | 1999-09-24 | Hitachi Ltd | Ball grid array type of semiconductor device |
| KR20010055009A (en) * | 1999-12-09 | 2001-07-02 | 윤종용 | Pre Plated Frame having plating areas separated |
-
2000
- 2000-06-12 KR KR10-2000-0032218A patent/KR100501879B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02172265A (en) * | 1988-12-23 | 1990-07-03 | Mitsubishi Electric Corp | Resin seal type semiconductor device |
| JPH0982870A (en) * | 1995-09-14 | 1997-03-28 | Toshiba Corp | Semiconductor device, lead frame, and manufacture thereof |
| JPH11260962A (en) * | 1998-03-12 | 1999-09-24 | Hitachi Ltd | Ball grid array type of semiconductor device |
| KR20010055009A (en) * | 1999-12-09 | 2001-07-02 | 윤종용 | Pre Plated Frame having plating areas separated |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010111662A (en) | 2001-12-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8115104B2 (en) | Circuit board with buried conductive trace formed thereon and method for manufacturing the same | |
| JP3578770B2 (en) | Semiconductor device | |
| US6507096B2 (en) | Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same | |
| KR100237328B1 (en) | Structure of semiconductor package and manufacturing method | |
| US20030014863A1 (en) | Method for manufacturing a printed circuit board | |
| US4965700A (en) | Thin film package for mixed bonding of chips | |
| KR100501879B1 (en) | Substrate for semiconductor and its manufacturing method | |
| JP2949969B2 (en) | Film carrier semiconductor device | |
| US8298865B2 (en) | Method for manufacturing a substrate for a semiconductor package | |
| JPH08288316A (en) | Semiconductor device | |
| KR100549299B1 (en) | Semiconductor package and its manufacturing method | |
| JP3672885B2 (en) | Semiconductor device | |
| KR100708045B1 (en) | Semiconductor package and its manufacturing method | |
| KR101187913B1 (en) | Leadframe for semiconductor package and the fabrication method thereof | |
| KR100401497B1 (en) | Stack type Multi Chip Package and Manufacture Method the same | |
| KR100355798B1 (en) | Printed circuit board for semiconductor package and its manufacturing method | |
| JPH09246416A (en) | Semiconductor device | |
| KR100708041B1 (en) | semiconductor package and its manufacturing method | |
| KR100708042B1 (en) | Manufacturing method of substrate for semiconductor package | |
| KR100411812B1 (en) | Manufacturing method of semiconductor package | |
| KR100708044B1 (en) | Multi-layer circuit tape and its manufacturing method and semiconductor package using it | |
| JPH11102942A (en) | Manufacture of tab tape for t-bga | |
| JP3257931B2 (en) | Semiconductor package, method of manufacturing the same, and semiconductor device | |
| KR100337461B1 (en) | Semiconductor package and manufacturing method | |
| EP1065718A1 (en) | Semiconductor chip module and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |